CN111232915B - Multi-layer mask layer structure, preparation method thereof and MEMS device - Google Patents

Multi-layer mask layer structure, preparation method thereof and MEMS device Download PDF

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CN111232915B
CN111232915B CN202010066075.5A CN202010066075A CN111232915B CN 111232915 B CN111232915 B CN 111232915B CN 202010066075 A CN202010066075 A CN 202010066075A CN 111232915 B CN111232915 B CN 111232915B
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layer
annealing
mask layer
mask
plating
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CN111232915A (en
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梁立兴
朱京
张琳琳
裴志强
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Beijing Chenjing Electronics Co ltd
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Beijing Chenjing Electronics Co ltd
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388Etch mask forming
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388Etch mask forming
    • B81C1/00396Mask characterised by its composition, e.g. multilayer masks

Abstract

The application discloses a multi-layer mask layer structure, which comprises a base layer and at least three mask layers sequentially stacked on the base layer, wherein the thickness of an n+1th mask layer is 1.2-3 times of that of the n mask layer. The application also discloses a preparation method of the multilayer mask layer structure, which comprises the steps of firstly cleaning a base layer and drying the base layer; and then plating three or more mask layers on the base layer, wherein each plating is finished and annealed by using specific annealing parameters. The application also discloses an MEMS device manufactured by the multi-layer mask layer structure. The application starts with the design of the relative thickness between the multiple film layers of the multi-layer mask layer and the parameters of each technological process in the preparation method, ensures the corrosion resistance of the multi-layer mask layer, avoids the phenomena of peeling, delamination or infirm adhesion, and simultaneously can effectively avoid the problems of serial layer etching and side etching uniformity of different pattern layers in the subsequent pattern definition release etching process of photoetching and etching.

Description

Multi-layer mask layer structure, preparation method thereof and MEMS device
Technical Field
The application relates to the field of MEMS device preparation, in particular to a multi-layer mask layer structure, a preparation method thereof and an MEMS device.
Background
In recent years, with the development of Micro-Electro-Mechanical System (MEMS) technology, the complexity of a simple device structure is becoming more and more complex, and the precise control of an in-plane two-dimensional structure of a MEMS device can be basically solved by using conventional technologies such as micromachining lithography. However, based on device factors, precise control of quartz and other substrates in the longitudinal depth, especially in multilayer depth structures, is still not well achieved. The method is mainly characterized in that photoresist layer by layer definition is generally selected in the traditional planar multi-layer definition process, photoresist with non-interference of a two-phase removal process is mainly selected to realize multi-part pattern definition at one time, the technology has the defects that the types of the photoresist which can realize mutual compatibility (the removal process is non-interference) are limited, the multi-layer photoresist, especially more than three layers of photoresist, is very difficult to match, the photoresist storage time is limited (or the storage condition is harsh), the method has no mass storage meaning, the semi-finished products of the predefined layer are difficult to realize the mass related commercial buying and selling and exchanging values, and the deep development of related industries cannot be promoted; on the other hand, the structure of the substrate (quartz) after the definition of the primary deep etching is damaged to a certain extent, and the structure cannot bear the secondary or even tertiary pattern definition process (such as photoetching, etching, bonding and the like).
The multi-layer predefining technology of the quartz substrate refers to an etching control technology for accurately controlling the three-dimensional structure of a device by predefining and defining a multi-step pattern to be defined in a quartz mask layer in advance and releasing the corresponding definition layer-etching through a serial single step in a subsequent etching process. Meanwhile, to ensure the smooth implementation of the technology, a stable, reliable and reliable multilayer mask manufacturing technology is an important basis of the method.
At present, a Cr/Au or Ti/Au mask is generally preferred for a mask layer of a quartz substrate, wherein the main function of the Cr layer is to improve the bonding force between the Au layer and the quartz substrate, and the Au layer is mainly used for blocking etching of quartz by etching liquid. Although double-layer Cr/Au/Cr/Au films are researched in the practical literature, the main research content is generally focused on the research of the deposition process of the films, and the compatibility design of the relative thicknesses and the relative process parameters among three or more layers of Cr/Au films and multiple layers of films on the subsequent photoetching process is less. In the actual processing process, the main reason that the application of the three-layer and above Cr/Au thin film is limited is that the relative thickness parameters between the two layers of thin films are rarely considered in the preparation process of the traditional double-layer Cr/Au thin film, so that a serious side etching phenomenon occurs in the subsequent photoetching process; meanwhile, the annealing temperature generally selected by the traditional annealing process is higher, so that the gradient distinguishing annealing design of different coatings is not realized; when three or more Cr/Au films are manufactured, the relative thickness and relative processing technological parameters of the multi-layer films are required to be designed, otherwise, the phenomena of process layer strings, inconsistent side etching of the pattern edges and the like occur among mask layers in the subsequent photoetching-etching pattern layer definition technological process because of unreasonable technological parameter design among the films, and even the product failure is caused because of insufficient corrosion resistance of the film layers.
Disclosure of Invention
Therefore, the technical problem to be solved by the application is to overcome the defects that in the prior art, due to unreasonable parameter design, the problems of serial layer etching and side etching uniformity easily occur in the subsequent pattern definition release etching process, and therefore, the MEMS device with three or more mask layers cannot be manufactured, thereby providing a multi-layer mask layer structure, a preparation method thereof and the MEMS device.
The application adopts the following technical scheme:
the application provides a multi-layer mask layer structure, which comprises the following steps:
a base layer, and, in addition,
and sequentially stacking at least three mask layers arranged on the base layer, wherein the thickness of the n+1th mask layer is 1.2-3 times that of the n mask layer, n is a natural number except 0, and the specific range is determined according to the practical process design redundancy limit.
Specifically, the base layer is quartz or AlN, znO, liNbO 3 、LiTaO 3 Any one of MEMS process functional materials, metal, ceramic, glass and organic materials;
the mask layer is one of a metal film, ceramic, glass or an organic coating film, and the metal film is a single-layer or double-layer metal film formed by one or two of a Au, cr, ti, ni film and a W film.
Preferably, the base layer is made of any quartz cut quartz material, including fused quartz.
Preferably, the mask layer is a double-layer metal film composed of an auxiliary layer formed by one of Cr and Ti and a gold layer formed by Au, and the auxiliary layer is arranged on one side of the mask layer, which is close to the base layer.
Further, the thickness of the n+1th auxiliary layer is 1.3-3 times of that of the n auxiliary layer, and the thickness of the n+1th gold layer is 1.2-3 times of that of the n gold layer; preferably, the thickness of the first auxiliary layer in the first mask layer is 5-50nm, and the thickness of the first gold layer is 50-500nm.
The application also provides a preparation method of the multi-layer mask layer structure, which comprises the following steps:
s1: taking the functional material of the MEMS technology with a smooth surface as a base layer, and carrying out a cleaning technology and a drying technology;
s2: three or more mask layers are plated on the base layer.
Specifically, in the step S1, the cleaning process is to sequentially perform alcohol cleaning, alkali cleaning and acid cleaning for 15-25min each, then ultrasonically clean in deionized water for 8-15min, and rinse with deionized water for 2-5min; the drying process is that spin-drying is firstly carried out, and then drying is carried out.
Specifically, the plating in step S2 may be physical deposition such as sputtering, evaporation, electron beam, laser, etc. (gas phase) chemical deposition, and printing, film pasting, etc., preferably plating using a sputter coater, performing an activation process before each plating, performing an annealing process after each plating, and performing a cleaning process and a drying process.
Further, the activation process is wet activation or dry activation, and the dry activation comprises laser assistance, plasma assistance and other modes; wet activation is typically chemically assisted, with weak acid cleaning being the dominant step in the conventional thin film activation procedure.
In the annealing process, the first annealing temperature of annealing after plating the first mask layer is 120-150 ℃, the first annealing time is more than or equal to 8 hours, the second annealing temperature of annealing after plating the last mask layer is 80-100 ℃, the second annealing time is more than or equal to 24 hours, the annealing temperature of annealing after plating the intermediate mask layer is less than or equal to the second annealing temperature, and the annealing time is less than or equal to the second annealing time.
Further, after each cleaning process and drying process, other processes such as etching, film deposition, electroplating, peeling, bonding, through-hole and the like can be continued.
The application also provides a multi-MEMS device which is manufactured by adopting the multi-layer mask layer structure and then using a multi-layer predefining technology. The multi-layer predefining technology is that the multi-layer mask layer structure is predefined on the surface of the base material, then the layers to be etched are released timely according to the needs in the subsequent base material etching process, and finally the MEMS device with multi-layer stereoscopic effect can be realized after complete etching.
The technical scheme of the application has the following advantages:
1. compared with the existing single and double mask layers, the MEMS device with the multi-layer mask layer structure provided by the application has the advantages that more layers can be defined, and the MEMS device with more abundant layers can be conveniently processed. The simple MEMS three-dimensional device can be realized by two layers in general; however, for complex MEMS devices as well as multi-functional integrated MEMS devices, more layers are required to meet the device requirements. The multi-layer requirement belongs to the development trend of future MEMS devices.
2. According to the MEMS device with the multi-layer mask layer structure, through designing the relative thickness of the film layers in each mask layer, serious mismatch of the side etching sizes of the pattern layers caused by repeated mask layer release steps is avoided, and the accuracy of subsequent pattern etching is ensured.
3. According to the preparation method of the MEMS device with the multi-layer mask layer structure, the strength of the annealing process parameters after the deposition of the annealing first layer film is maximum, and the annealing parameters of the first layer film are preferably 120-150 ℃ for more than 8 hours. The annealing process of the final film is preferably 80-100 ℃ for more than 24 hours. The important principle is that the first annealing temperature is not too high, so that the phenomenon of layer-crossing etching in the subsequent film layering etching process is prevented from being caused after the temperature exceeds 150 ℃, and the phenomenon is more likely to occur when the number of film layers is more; on the other hand, the annealing parameters of the intermediate film layer should not exceed the annealing temperature and the annealing time of the last film, because the main purpose of annealing the intermediate film layer is that the accumulated unevenness of the film layer surface is only required to be relaxed to a certain extent, the interlayer etching layer-crossing phenomenon possibly caused by structural bulges is reduced, and the stress release of the multi-layer mask layer is carried out simultaneously with the last annealing, so that the stress relief effect is better.
4. According to the preparation method of the MEMS device with the multi-layer mask layer structure, the activation step is carried out before each film plating, the surface oxidation passivation layer and the adsorption particles are removed, and meanwhile, a certain amount of suspension bonds are formed on the surface of the film layer, so that the bonding force of the next layer of film to be plated is guaranteed. Meanwhile, in the preparation process of three layers or more than three layers of films, unnecessary high-temperature annealing process is avoided, and the binding force and the integrity of the film layer can be improved through reasonable activation procedures.
5. According to the method, through the predefining technology of multiple layers, the definition of the layers in the mask layer is finished in advance before the substrate is etched, so that the problem that the subsequent structure of the substrate after deep etching cannot bear the structural damage risk of the substrate due to the fact that the structure of the substrate is damaged to a certain extent, such as the pattern definition technology of spraying (spin) photoresist, photoetching and the like, is avoided, and the risks of glue drying, glue damage and the like of the traditional photoresist mask in the long-time release-etching technology are avoided. On the other hand, the post-product after multi-layer predefining can be stored for a long time, and can be directly delivered to the first party for use or any layer in the multi-layer predefining can be selected and removed. Meanwhile, the first party can also randomly insert additional MEMS processes such as electroplating, new layer definition, etching, trimming, bonding and the like on corresponding arbitrary layers without substitution, thereby being beneficial to the full confidentiality requirements of the first party on self-process and design flow and having good commercial popularization characteristics.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a MEMS device having a multi-layer mask layer structure in embodiment 1 of the present application before performing a final step of continuous multi-step lithography-etching.
Reference numerals illustrate:
1-a quartz base layer; 2-a first Cr layer; 3-a first Au layer; 4-a second Cr layer; 5-a second Au layer; 6-a third Cr layer; 7-third Au layer.
Detailed Description
The following description of the embodiments of the present application will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Example 1
The embodiment provides a method for preparing a MEMS device with a multi-layer mask layer structure, which comprises the following steps:
(1) Taking a quartz substrate sample with a flat surface as a base layer, sequentially carrying out alcohol washing, alkali washing and acid washing for 20min according to a standard cleaning process flow, then carrying out ultrasonic cleaning in deionized water for 10min, washing with deionized water for 3min, spin-drying, and then activating for 3s by using 180W plasma;
(2) Adopting a sputtering coating machine to sequentially coat and deposit a first Cr layer with the thickness of 10nm and a first Au layer with the thickness of 100nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 120 ℃ for 12 hours;
(3) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a second Cr layer with the thickness of 20nm and a second Au layer with the thickness of 200nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 12 hours;
(4) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a third Cr layer with the thickness of 30nm and a third Au layer with the thickness of 250nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ and the structure is shown as figure 1 for 24 hours;
(5) And (3) repeating the cleaning process of the step (1), spin-drying, drying and activating, and then completing the definition and release of the corresponding Cr/Au pattern layer by a continuous multi-step photoetching-etching method according to the deep etching and pattern layer release requirements of the actual device, so as to finally obtain the MEMS device with the multi-layer mask layer structure.
Example 2
The embodiment provides a method for preparing a MEMS device with a multi-layer mask layer structure, which comprises the following steps:
(1) Taking a quartz substrate sample with a flat surface as a base layer, sequentially carrying out alcohol washing, alkali washing and acid washing for 20min according to a standard cleaning process flow, then carrying out ultrasonic cleaning in deionized water for 10min, washing with the deionized water for 3min, spin-drying, and then activating for 3s by using 180W plasma;
(2) Adopting a sputtering coating machine to sequentially coat and deposit a first Cr layer with the thickness of 5nm and a first Au layer with the thickness of 50nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 120 ℃ for 12 hours;
(3) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a second Cr layer with the thickness of 15nm and a second Au layer with the thickness of 150nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 12 hours;
(4) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a third Cr layer with the thickness of 25nm and a third Au layer with the thickness of 210nm on the quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 12 hours;
(5) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a fourth Cr layer with the thickness of 33nm and a fourth Au layer with the thickness of 260nm on the quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 24 hours;
(6) And (3) repeating the cleaning process of the step (1), spin-drying, drying and activating, and then completing the definition and release of the corresponding Cr/Au pattern layer by a continuous multi-step photoetching-etching method according to the deep etching and pattern layer release requirements of the actual device, so as to finally obtain the MEMS device with the multi-layer mask layer structure.
Example 3
The embodiment provides a method for preparing a MEMS device with a multi-layer mask layer structure, which comprises the following steps:
(1) Taking a quartz substrate sample with a flat surface as a base layer, sequentially carrying out alcohol washing, alkali washing and acid washing for 20min according to a standard cleaning process flow, then carrying out ultrasonic cleaning in deionized water for 10min, washing with the deionized water for 3min, spin-drying, and then activating for 3s by using 180W plasma;
(2) Adopting a sputtering coating machine to sequentially coat and deposit a first Cr layer with the thickness of 20nm and a first Au layer with the thickness of 200nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 120 ℃ for 12 hours;
(3) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a second Cr layer with the thickness of 35nm and a second Au layer with the thickness of 240nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 12 hours;
(4) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a third Cr layer with the thickness of 50nm and a third Au layer with the thickness of 300nm on the quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 24 hours;
(5) And (3) repeating the cleaning process of the step (1), spin-drying, drying and activating, and then completing the definition and release of the corresponding Cr/Au pattern layer by a continuous multi-step photoetching-etching method according to the deep etching and pattern layer release requirements of the actual device, so as to finally obtain the MEMS device with the multi-layer mask layer structure.
Example 4
The embodiment provides a method for preparing a MEMS device with a multi-layer mask layer structure, which comprises the following steps:
(1) Taking a quartz substrate sample with a flat surface as a base layer, sequentially carrying out alcohol washing, alkali washing and acid washing for 20min according to a standard cleaning process flow, then carrying out ultrasonic cleaning in deionized water for 10min, washing with the deionized water for 3min, spin-drying, and then activating for 3s by using 180W plasma;
(2) Adopting a sputtering coating machine to sequentially coat and deposit a first Ti layer with the thickness of 10nm and a first Au layer with the thickness of 150nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 150 ℃ for 12 hours;
(3) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a second Ti layer with the thickness of 15nm and a second Au layer with the thickness of 200nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 12 hours;
(4) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a third Ti layer with the thickness of 35nm and a third Au layer with the thickness of 300nm on the quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 12 hours;
(5) And (3) repeating the cleaning process of the step (1), spin-drying and drying, and then completing the definition and release of the corresponding Ti/Au pattern layer by a continuous multi-step photoetching-etching method according to the depth etching and pattern layer release requirements of the actual device, thereby finally obtaining the MEMS device with the multi-layer mask layer structure.
Comparative example 1
The present embodiment provides a method for manufacturing a MEMS device with a multi-layer mask layer structure, which is different from embodiment 1 only in the thickness of each chrome gold layer, and includes the following steps:
(1) Taking a quartz substrate sample with a flat surface as a base layer, sequentially carrying out alcohol washing, alkali washing and acid washing for 20min according to a standard cleaning process flow, then carrying out ultrasonic cleaning in deionized water for 10min, washing with the deionized water for 3min, spin-drying, and then activating for 3s by using 180W plasma;
(2) Adopting a sputtering coating machine to sequentially coat and deposit a first Cr layer with the thickness of 10nm and a first Au layer with the thickness of 200nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 120 ℃ for 12 hours;
(3) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a second Cr layer with the thickness of 10nm and a second Au layer with the thickness of 200nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 12 hours;
(4) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a third Cr layer with the thickness of 10nm and a third Au layer with the thickness of 200nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 24 hours;
(5) And (3) repeating the cleaning process of the step (1), spin-drying, drying and activating, and then completing the definition and release of the corresponding Cr/Au pattern layer by a continuous multi-step photoetching-etching method according to the deep etching and pattern layer release requirements of the actual device, so as to finally obtain the MEMS device with the multi-layer mask layer structure.
Comparative example 2
The present embodiment provides a method for manufacturing a MEMS device with a multi-layer mask layer structure, which is different from embodiment 1 only in the parameters of each annealing, and includes the following steps:
(1) Taking a quartz substrate sample with a flat surface as a base layer, sequentially carrying out alcohol washing, alkali washing and acid washing for 20min according to a standard cleaning process flow, then carrying out ultrasonic cleaning in deionized water for 10min, washing with the deionized water for 3min, spin-drying, and then activating for 3s by using 180W plasma;
(2) Adopting a sputtering coating machine to sequentially coat and deposit a first Cr layer with the thickness of 10nm and a first Au layer with the thickness of 100nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 120 ℃ for 12 hours;
(3) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a second Cr layer with the thickness of 20nm and a second Au layer with the thickness of 200nm on a quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 80 ℃ for 10 hours;
(4) Repeating the cleaning process of the step (1), spin-drying, drying and activating, adopting a sputtering coating machine to sequentially coat and deposit a third Cr layer with the thickness of 30nm and a third Au layer with the thickness of 250nm on the quartz wafer to be coated, and then carrying out an annealing process on the wafer subjected to the first chromium-gold coating process, wherein the annealing parameter is 150 ℃ for 12 hours;
(5) And (3) repeating the cleaning process of the step (1), spin-drying, drying and activating, and then completing the definition and release of the corresponding Cr/Au pattern layer by a continuous multi-step photoetching-etching method according to the deep etching and pattern layer release requirements of the actual device, so as to finally obtain the MEMS device with the multi-layer mask layer structure.
Test examples
The MEMS devices of the multilayer mask layer structures obtained in examples 1 to 4 and comparative examples 1 to 2 were subjected to corrosion resistance and the like, and the results are shown in the following table:
TABLE 1
As shown in the table, the MEMS device with the multi-layer mask layer structure prepared by the preparation method provided by the application has the minimum corrosion resistance time longer than 50h, the corrosion difference between each mask layer is smaller than 3 mu m, and the phenomenon of process serial layers does not exist. Compared with the comparative example 1 and the example 1, the Cr and Au films of each layer do not meet the requirements of the application, the corrosion resistance time is not influenced, but the interlayer side corrosion difference is greatly increased; compared with the embodiment 1, the annealing parameters of the comparative example 2 do not meet the requirements of the application, the corrosion resistance time is not influenced, but the phenomenon of uneven edges occurs between layers, and process serial layers occur, so that the value and the use effect of the MEMS device are greatly reduced.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.

Claims (8)

1. A multi-layer mask layer structure, comprising:
a base layer, and, in addition,
at least three mask layers are sequentially stacked on the base layer, wherein the thickness of the n+1th mask layer is 1.2-3 times of the thickness of the n mask layer, and n is a natural number except 0;
the mask layer is a double-layer metal film formed by an auxiliary layer formed by one of Cr and Ti and a gold layer formed by Au, and the auxiliary layer is arranged on one side of the mask layer, which is close to the base layer;
the thickness of the n+1th auxiliary layer is 1.3-3 times of that of the n auxiliary layer, and the thickness of the n+1th gold layer is 1.2-3 times of that of the n gold layer;
the thickness of the first auxiliary layer in the first mask layer is 5-50nm, and the thickness of the first gold layer is 50-500nm;
the preparation of the multi-layer mask layer structure comprises the steps of plating three or more mask layers on a base layer, and carrying out an annealing process after plating one layer each time;
in the annealing process, the first annealing temperature of annealing after plating the first mask layer is 120-150 ℃, the first annealing time is more than or equal to 8 hours, the second annealing temperature of annealing after plating the last mask layer is 80-100 ℃, the second annealing time is more than or equal to 24 hours, the annealing temperature of annealing after plating the intermediate mask layer is less than or equal to the second annealing temperature, and the annealing time is less than or equal to the second annealing time.
2. The multi-layer mask layer structure of claim 1, wherein the base layer is quartz, alN, znO, liNbO 3 、LiTaO 3 Any one of MEMS process functional materials, metal, ceramic, glass and organic materials.
3. The multi-layer mask layer structure of claim 2, wherein the base layer is any quartz cut quartz material.
4. A method for producing a multi-layer mask layer structure according to any one of claims 1-3, comprising the steps of:
s1: taking the functional material of the MEMS technology with a smooth surface as a base layer, and carrying out a cleaning technology and a drying technology;
s2: three or more mask layers are plated on the base layer.
5. The method according to claim 4, wherein the cleaning process in step S1 is sequentially alcohol washing, alkali washing, acid washing for 15-25min each, then ultrasonic cleaning in deionized water for 8-15min, and deionized water rinsing for 2-5min;
the drying process is that spin-drying is firstly carried out, and then drying is carried out.
6. The method according to claim 4 or 5, wherein the plating in step S2 is performed by using a sputter coater, an activation process is performed before each plating, an annealing process is performed after each plating, and a cleaning process and a drying process are performed.
7. The method of claim 6, wherein the activation process is wet or dry activation;
in the annealing process, the first annealing temperature of annealing after plating the first mask layer is 120-150 ℃, the first annealing time is more than or equal to 8 hours, the second annealing temperature of annealing after plating the last mask layer is 80-100 ℃, the second annealing time is more than or equal to 24 hours, the annealing temperature of annealing after plating the intermediate mask layer is less than or equal to the second annealing temperature, and the annealing time is less than or equal to the second annealing time.
8. A MEMS device employing the multi-layer mask layer structure of any of claims 1-3.
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