CN111224656A - Charge sharing resistant D latch with low power consumption function - Google Patents

Abstract

An anti-charge sharing D latch with a low power consumption function belongs to the field of anti-nuclear reinforcement in the reliability of an integrated circuit. The problems that a traditional D latch for resisting charge sharing needs more transistors, is large in area and large in power consumption overhead are solved. The invention comprises 30 transistors, specifically 20 PMOS transistors P1-P20 and 10 NMOS transistors N1-N10, and fault tolerance is carried out on the overturned nodes by mainly adopting a mode of parallel connection of the PMOS transistors, and the connection mode can effectively reduce the number of the nodes with threshold voltage loss, so that the latch has lower area and power consumption expenditure. The invention is mainly applied to low-power consumption circuits with medium and low frequencies.

Description

Charge sharing resistant D latch with low power consumption function

Technical Field

The invention belongs to the field of anti-nuclear reinforcement in the reliability of integrated circuits.

Background

The development of process size, the reduction of node spacing of integrated circuit devices and the improvement of integration level greatly increase the charge sharing probability when being bombarded by heavy ions. Meanwhile, the circuit is more susceptible to the single event effect due to the reduction of the thickness of the gate oxide and the reduction of the node capacitance. The reduction of the gate length also enhances the parasitic bipolar effect of the transistor, which will result in charge sharing being possible. The charge sharing effect refers to the phenomenon that a single high-energy particle bombards a circuit node to generate charges and is simultaneously collected by one or more nearby nodes: with the reduction of the process size, the number of nodes affected by the single event effect is increased from the previous one, and charges generated by particle bombardment are collected by the nodes to cause the node inversion, so that the problem of multi-node inversion of the integrated circuit is becoming an important problem affecting the reliability of the circuit. The existing anti-radiation reinforcing design related to single-node overturning cannot meet the requirement of circuit reinforcing, and a new anti-radiation reinforcing circuit is urgently needed to be designed for resisting multi-node overturning so as to improve the reliability of the circuit.

Most of the existing anti-charge sharing reinforced latches are constructed by using a multi-mode redundancy based C-cell interconnection technology, and although the flipped nodes can be recovered, too many transistors (up to 70) are needed to implement the latches, so that the problems of large number of transistors, large power consumption and large hardware overhead exist, and therefore, the problems need to be solved urgently.

Disclosure of Invention

The invention provides an anti-charge sharing D latch with a low power consumption function, aiming at solving the problems of more transistors, large area and high power consumption overhead required by the traditional anti-charge sharing D latch.

A charge sharing resistant D-latch with low power consumption function, including 20 PMOS transistors P1 to P20 and 10 NMOS transistors N1 to N10;

the drain of the transistor N10, the source of the transistor P9, the source of the transistor P10 and the source of the transistor P12 are connected to each other and then serve as input terminals of an input signal D of the latch;

the source of the transistor P11 is connected with the source of the transistor P13 to serve as the input end of an input signal DN of the latch, and the input signal D is opposite to the input signal DN;

the gate of the transistor P9, the gates of the transistors P10 to P13 and the gate of the transistor N7 are connected and then serve as the input end of the clock signal CLK of the latch;

after the gate of the transistor N10 is connected to the gate of the transistor P16, the gate serves as an input terminal of a clock signal CLKN of the latch, and the clock signal CLK is opposite to the clock signal CLKN;

the source of the transistor N10, the drain of the transistor P9, the drain of the transistor P16 and the drain of the transistor N7 are connected to each other and then serve as an output terminal of the latch output signal Q and also serve as a node Q;

the sources of the transistors P1-P8 are all connected with the positive pole of the power supply;

the gate of the transistor P7, the gate of the transistor P4, the drain of the transistor P5, the source of the transistor P20, the gate of the transistor N2, the gate of the transistor P14, the gate of the transistor N9, and the drain of the transistor P13 are connected to form a node X4;

the drain of the transistor P7, the drain of the transistor P1, the drain of the transistor N1, the gate of the transistor P17, the gate of the transistor P19, and the gate of the transistor N6 are connected to form a node X6;

the gate of the transistor P1, the gate of the transistor P2, the drain of the transistor P3, the source of the transistor P18, the gate of the transistor N4, the gate of the transistor P15, the gate of the transistor N8, and the drain of the transistor P11 are connected to form a node X2;

the gate of the transistor N1, the gate of the transistor P18, the gate of the transistor P20, the drain of the transistor N6, the drain of the transistor P6, and the drain of the transistor P8 are connected to form a node X5;

the sources of the transistors N1-N6 are all connected with the power ground;

the drain of the transistor P2, the gate of the transistor P5, the source of the transistor P17, the gate of the transistor N3, the gate of the transistor P6, and the drain of the transistor P10 are connected to form a node X1;

the drain of the transistor P17 is connected to the drain of the transistor N12;

the gate of the transistor P3, the drain of the transistor P4, the source of the transistor P19, the gate of the transistor N5, the gate of the transistor P8, and the drain of the transistor P12 are connected to form a node X3;

the drain of the transistor P18 is connected to the drain of the transistor N3;

the drain of the transistor P19 is connected to the drain of the transistor N4;

the drain of the transistor P20 is connected to the drain of the transistor N5;

the source of the transistor P14 is connected to the positive electrode of the power supply, the drain of the transistor P14 is connected to the source of the transistor P15, the drain of the transistor P15 is connected to the source of the transistor P16, the source of the transistor N7 is connected to the drain of the transistor N8, the source of the transistor N8 is connected to the drain of the transistor N9, and the source of the transistor N9 is connected to the ground of the power supply.

Preferably, when the clock signal CLK is at low level "0", the latch is turned on; when the clock signal CLK is at high level "1", the latch latches.

Preferably, when the clock signal CLK is at a high level "1" and the latch latches at a low level "0", the sensitive nodes of the latch are X1, X3, X5, X6, and Q;

when the clock signal CLK is high "1" and the latch latches a high "1", the sensitive nodes of the latch are X2, X4, X5, X6, and Q.

Preferably, the anti-charge sharing D latch with low power consumption function includes a normal operation state and a fault-tolerant operation state.

Preferably, the normal operating state includes the following cases:

the first condition is as follows: assuming that the input signal D is equal to 0, the input signal DN is equal to 1;

(1) when CLK is 0, and CLKN is 1, the latch is in the on state, at which time, PMOS transistors P10 to P13 are all on, PMOS transistors P3, P5, P6, and P8 are all on, PMOS transistors P1, P2, P4, and P7 are all off, NMOS transistors N1, N2, and N4 are all on, and NMOS transistors N3, N5, and N6 are off, which will result in node X5 being 1, and X6 being 0; then, the PMOS transistors P17 and P19 will be turned on, and the PMOS transistors P18 and P20 will be turned off, so that X1 ═ X3 ═ X6 ═ 0, and X2 ═ X4 ═ X5 ═ 1, at which time the PMOS transistor P9 and the NMOS transistor N10 are turned on, and the NMOS transistors N8 and N9 are also turned on, while the PMOS transistors P14 and P15 are turned off, but since the NMOS transistor N7 and the PMOS transistor P16 are also turned off, the output signal Q is equal to 0;

(2) when CLK is 1 and CLKN is 0, the latch enters a latch state, at this time, the PMOS transistors P9 to P13 are turned off, the NMOS transistor N7 is turned on, and at this time, the output terminal of the output terminal signal Q is directly connected to the power ground through the turned-on NMOS transistors N7 to N9, and because of the latch inside the latch, the output signal Q is 0 will be latched all the time and is not affected by the change of the input signal D;

case two: assuming that the input signal D is 1, the input signal DN is 0;

(1) when CLK is 0, and CLKN is 1, the latch is in a conducting state, at which time, PMOS transistors P10 to P13 are all turned on, PMOS transistors P1, P2, P4, and P7 are all turned on, PMOS transistors P3, P5, P6, and P8 are all turned off, NMOS transistors N3, N5, and N6 are all turned on, and NMOS transistors N1, N2, and N4 are all turned off, which will result in node X5 being 0, and X6 being 1; then, the PMOS transistors P18 and P20 will be turned on, and the PMOS transistors P17 and P19 will be turned off, so that X1 ═ X3 ═ X6 ═ 1, and X2 ═ X4 ═ X5 ═ 0, at which time the PMOS transistor P9 and the NMOS transistor N10 are turned on, and the PMOS transistors P14 and P15 are also turned on, while the NMOS transistors N18 and N9 are turned off, but since the NMOS transistor N7 and the PMOS transistor P16 are also turned off, the output signal Q is equal to 1;

(2) when CLK is equal to 1 and CLKN is equal to 0, the latch enters a latch state, at this time, the PMOS transistors P9 to P13 are all turned off, the PMOS transistor P16 is turned on, and the output terminal of the output signal Q is directly connected to the positive power supply terminal through the turned-on PMOS transistors P14 to P16, and the output signal Q is always latched and is not affected by the change of the input signal D due to the latch inside the latch.

Preferably, the fault tolerant operating condition occurs during latch latching, and includes the following:

the first condition is as follows: when the clock signal CLK is at a high level "1" and the latch latches a low level "0", the sensitive nodes of the latch are X1, X3, X5, X6 and Q; when any one or two of the sensitive nodes are inverted, the latch feedback mechanism of the latch is not completely destroyed, so that the nodes X2 and X4 can restore the inverted one or two sensitive nodes to the original states;

case two: when the clock signal CLK is at high level "1" and the latch latches at high level "1", the sensitive nodes of the latch are X2, X4, X5, X6 and Q; when any one or two of the sensitive nodes are flipped, the latch feedback mechanism of the latch is not completely destroyed, so the nodes X1 and X3 can restore the flipped sensitive node or sensitive nodes to their original states.

Principle analysis:

the fault-tolerant operating state is independent of a specific input value of an input signal D of the latch, the fault-tolerant operating state occurs in a latch latching state, and is related to data latched by each node inside the latch, and the fault-tolerant operating state of the charge sharing resistant D latch with the low power consumption function is analyzed as follows, when a clock signal CLK is 1, CLKN is 0, 6 internal nodes X1 is X3 is X6 is 1, X2 is X4 is X5 is 0, and an output node Q is 1, at this time, 5 internal sensitive nodes of the latch are X2, X4, X5, X6 and Q, and a specific situation when any one or two sensitive nodes of the 5 sensitive nodes are inverted is as follows:

1. when node X2 is flipped to 1, NMOS transistor N4 will turn on; the PMOS transistors P1 and P2 are turned off; however, since the PMOS transistor P19 is turned off, the other nodes will not be affected and will remain in the original state, and therefore, the PMOS transistor P18 and the NMOS transistor N3 will be turned on, so the node X2 will be pulled back to the original 0 state and the state of the output node Q will not change.

2. When the node X4 is bombarded and overturned, the PMOS transistors P4 and P7 are closed, the NMOS transistor N2 is opened, and the node X6 is kept unchanged, so the PMOS transistor P17 is always in a closed state, the node X1 is not influenced, and the node X4 can be pulled back to the original state because the PMOS transistor P20 and the NMOS transistor N5 are always in an open state, and the state of the output node Q is not changed.

3. When node X5 is bombarded to become 1, PMOS transistors P20 and P18 are turned off and NMOS transistor N1 will be turned on, resulting in node X6 being 0 and PMOS transistors P17 and P19 being turned on and NMOS transistor N6 being turned off, but this does not change the state of the other nodes, so the remaining transistors remain on and off. Thus, the PMOS transistors P1 and P7 will be turned on all the time, while the PMOS transistors P6 and P8 will be turned off all the time, thereby restoring node X6, and turning on NMOS transistor N6, thereby restoring node X5;

4. when the node X6 is bombarded to become 0, the PMOS transistors P17 and P19 will be caused to be temporarily turned on, and at the same time the NMOS transistor N6 will be temporarily turned off, and the state of the node X5 remains unchanged, so that the PMOS transistors P18 and P20 will be always turned on, but since the states of the nodes X1-X4 are not changed, the PMOS transistors P1 and P7 are always turned on, therefore, the node X6 will be pulled back to 1, and the state of the output node Q will not be changed;

5. when node Q is bombarded and changed, the flipped value of node Q can be recovered, resulting in only one recoverable glitch, since the states of internal nodes X1-X4 have not changed.

6. When the states of the nodes X2 and X4 change, the PMOS transistors P1 and P7 are turned off, and the NMOS transistors N4 and N2 are turned on, but since the states of the nodes X5 and X6 do not change, the states of the PMOS transistors P17 to P20 do not change, and as a result, the states of the nodes X1 and X3 do not change, which causes the NMOS transistors N3 and N5 to be turned on all the time, and therefore, the states of the nodes X2 and X4 are restored to the original 0 state, and the state of the output node Q is not changed.

7. When the state of the nodes X2 and X6 changes, the PMOS transistors P1 and P2 will be turned off, the NMOS transistor N4 will be turned on, the PMOS transistors P17 and P19 will be turned on temporarily, and the NMOS transistor N6 will be turned off temporarily, so that the state of the node X5 remains unchanged, so that the PMOS transistors P18 and P20 will be turned on all the time. However, since the state of the node X1 is not changed, the NMOS transistor N3 is always turned on, the node X2 is pulled back to 0, the PMOS transistor P1 is turned on, the node X6 is pulled back to 1 through the turned-on PMOS transistors P1 and P7, and finally the state of the output node Q is not changed.

8. When the states of the nodes X4 and X6 change, the PMOS transistors P4 and P7 will be turned off, the NMOS transistor N2 will be turned on, the PMOS transistors P17 and P19 will be turned on temporarily, and the NMOS transistor N6 will be turned off temporarily, so the state of the node X5 remains unchanged, so the PMOS transistors P18 and P20 will be turned on all the time, but since the state of the node X3 does not change, the NMOS transistor N5 will be turned on all the time, the node X4 will be pulled back to the original 0, the PMOS transistor P7 will be turned on, and the node X6 will be pulled back to 1 by the turned-on PMOS transistors P1 and P7, so the state of the final output node Q will not change.

9. When nodes X2 and Q change state, NMOS transistor N4 will turn on; the PMOS transistors P1 and P2 are turned off. However, since the PMOS transistor P19 is turned off, the other nodes will not be affected and will remain in the original state, and therefore, the PMOS transistor P18 and the NMOS transistor N3 will be turned on, so the node X2 will be pulled back to the original 0 state, and since the states of the internal nodes X1 to X4 are not changed, the inverted value of the node Q can be restored.

10. When the nodes X4 and Q are changed in state, the PMOS transistors P4 and P7 are turned off, the NMOS transistor N2 is turned on, and the node X6 is kept unchanged in state, so the PMOS transistor P17 is always turned off, and the node X1 is not affected, and since the PMOS transistor P20 and the NMOS transistor N5 are always turned on, the node X4 can be pulled back to the original state, and since the states of the internal nodes X1 to X4 are not changed, the inverted value of the node Q can be restored.

11. When the nodes X5 and Q change state, the PMOS transistors P20 and P18 are turned off and the NMOS transistor N1 is turned on, resulting in the node X6 being 0, and the PMOS transistors P17 and P19 are turned on and the NMOS transistor N6 is turned off, but this does not change the state of the other nodes, so the remaining transistors remain on and off, and therefore the PMOS transistors P1 and P7 are turned on all the time and the PMOS transistors P6 and P8 are turned off all the time, thereby restoring the node X6 and turning on the NMOS transistor N6, thereby restoring the node X5, and the value of the node Q flip can be restored because the states of the internal nodes X1 to X4 are not changed;

12. when the states of the nodes X6 and Q change, the PMOS transistors P17 and P19 are caused to be turned on temporarily, and the NMOS transistor N6 is turned off temporarily, and the state of the node X5 remains unchanged, so that the PMOS transistors P18 and P20 are always turned on, but since the states of the nodes X1 to X4 do not change, the PMOS transistors P1 and P7 and the NMOS transistor N7 are always turned on, the node X6 is pulled back to 1, and since the states of the internal nodes X1 to X4 do not change, the inverted value of the node Q can be restored.

The invention has the following beneficial effects: the invention comprises 30 transistors, needs few transistors, and mainly adopts a mode of parallel connection of PMOS tubes to carry out fault tolerance on overturned nodes, such as: the transistors P7 and P1 are connected in parallel and the transistors P6 and P8 are connected in parallel, and the connection mode can effectively reduce the number of nodes with threshold voltage loss, so that the latch has lower area and power consumption expenses, and can be used in systems with strict requirements on area and power consumption, such as portable instruments and the like;

on the other hand, the invention also starts from the polarity of the radiation pulse voltage generated by single event upset, and only can generate positive or negative radiation pulse voltage on certain nodes of the latch through reasonable circuit design, thereby reducing the number of sensitive nodes, effectively reducing the number of transistors used for reinforcement and simultaneously reducing the hardware cost.

The invention can restore all the inversions to the original state, so the output node is not suspended and is in a high-impedance state, and no maintaining single path is needed to maintain the value of the output node, so the designed reinforced latch not only has the advantages of small area and low power consumption, but also has the advantage of maintaining high resistance without adding an additional maintaining circuit.

The recovery function of the latch constructed by the invention mainly depends on the PMOS tubes connected in parallel, but the PMOS tubes have lower propagation speed; meanwhile, in the layout, the connecting lines of some nodes need to be connected with the farther transistors, so that the distance of connecting metal lines is increased, and the propagation delay is slightly increased, so that the invention is mainly applied to low-power-consumption circuits with medium and low frequencies.

Drawings

FIG. 1 is a schematic diagram of a charge sharing tolerant D-latch with low power consumption according to the present invention;

fig. 2 is a simulation diagram of the charge sharing resistant D latch with low power consumption function according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

Referring to fig. 1, illustrating the present embodiment, the charge sharing tolerant D-latch with low power consumption function according to the present embodiment includes 20 PMOS transistors P1 to P20 and 10 NMOS transistors N1 to N10;

the drain of the transistor N10, the source of the transistor P9, the source of the transistor P10 and the source of the transistor P12 are connected to each other and then serve as input terminals of an input signal D of the latch;

the source of the transistor P11 is connected with the source of the transistor P13 to serve as the input end of an input signal DN of the latch, and the input signal D is opposite to the input signal DN;

the gate of the transistor P9, the gates of the transistors P10 to P13 and the gate of the transistor N7 are connected and then serve as the input end of the clock signal CLK of the latch;

after the gate of the transistor N10 is connected to the gate of the transistor P16, the gate serves as an input terminal of a clock signal CLKN of the latch, and the clock signal CLK is opposite to the clock signal CLKN;

the source of the transistor N10, the drain of the transistor P9, the drain of the transistor P16 and the drain of the transistor N7 are connected to each other and then serve as an output terminal of the latch output signal Q and also serve as a node Q;

the sources of the transistors P1-P8 are all connected with the positive pole of the power supply;

the gate of the transistor P7, the gate of the transistor P4, the drain of the transistor P5, the source of the transistor P20, the gate of the transistor N2, the gate of the transistor P14, the gate of the transistor N9, and the drain of the transistor P13 are connected to form a node X4;

the drain of the transistor P7, the drain of the transistor P1, the drain of the transistor N1, the gate of the transistor P17, the gate of the transistor P19, and the gate of the transistor N6 are connected to form a node X6;

the gate of the transistor P1, the gate of the transistor P2, the drain of the transistor P3, the source of the transistor P18, the gate of the transistor N4, the gate of the transistor P15, the gate of the transistor N8, and the drain of the transistor P11 are connected to form a node X2;

the gate of the transistor N1, the gate of the transistor P18, the gate of the transistor P20, the drain of the transistor N6, the drain of the transistor P6, and the drain of the transistor P8 are connected to form a node X5;

the sources of the transistors N1-N6 are all connected with the power ground;

the drain of the transistor P2, the gate of the transistor P5, the source of the transistor P17, the gate of the transistor N3, the gate of the transistor P6, and the drain of the transistor P10 are connected to form a node X1;

the drain of the transistor P17 is connected to the drain of the transistor N12;

the gate of the transistor P3, the drain of the transistor P4, the source of the transistor P19, the gate of the transistor N5, the gate of the transistor P8, and the drain of the transistor P12 are connected to form a node X3;

the drain of the transistor P18 is connected to the drain of the transistor N3;

the drain of the transistor P19 is connected to the drain of the transistor N4;

the drain of the transistor P20 is connected to the drain of the transistor N5;

the source of the transistor P14 is connected to the positive electrode of the power supply, the drain of the transistor P14 is connected to the source of the transistor P15, the drain of the transistor P15 is connected to the source of the transistor P16, the source of the transistor N7 is connected to the drain of the transistor N8, the source of the transistor N8 is connected to the drain of the transistor N9, and the source of the transistor N9 is connected to the ground of the power supply.

The invention utilizes the connection of 30 transistors to resist the turnover of one or two nodes and realize the fault tolerance of the turnover node, the used devices are few, and the fault tolerance of the turnover node is realized by mainly adopting a mode of connecting PMOS tubes in parallel, the connection mode can effectively reduce the number of nodes with threshold voltage loss, therefore, the latch has lower area and power consumption expense, and can be used in systems with harsh requirements on area and power consumption, such as portable instruments and the like.

Furthermore, when the clock signal CLK is at low level '0', the latch is turned on; when the clock signal CLK is at high level "1", the latch latches.

Further, although there are 7 nodes in total, X1, X2, X3, X4, X5, X6 and Q, depending on the latched value, its sensitive node will be 5, namely:

when the clock signal CLK is at a high level "1" and the latch latches a low level "0", the sensitive nodes of the latch are X1, X3, X5, X6 and Q;

when the clock signal CLK is high "1" and the latch latches a high "1", the sensitive nodes of the latch are X2, X4, X5, X6, and Q.

In the preferred embodiment, the specific value latched by the latch is independent of the specific value of the input signal D.

Furthermore, the anti-charge sharing D latch with the low power consumption function comprises a normal working state and a fault-tolerant working state.

Further, the normal operation state includes the following cases:

the first condition is as follows: assuming that the input signal D is equal to 0, the input signal DN is equal to 1;

(1) when CLK is 0, and CLKN is 1, the latch is in the on state, at which time, PMOS transistors P10 to P13 are all on, PMOS transistors P3, P5, P6, and P8 are all on, PMOS transistors P1, P2, P4, and P7 are all off, NMOS transistors N1, N2, and N4 are all on, and NMOS transistors N3, N5, and N6 are off, which will result in node X5 being 1, and X6 being 0; then, the PMOS transistors P17 and P19 will be turned on, and the PMOS transistors P18 and P20 will be turned off, so that X1 ═ X3 ═ X6 ═ 0, and X2 ═ X4 ═ X5 ═ 1, at which time the PMOS transistor P9 and the NMOS transistor N10 are turned on, and the NMOS transistors N8 and N9 are also turned on, while the PMOS transistors P14 and P15 are turned off, but since the NMOS transistor N7 and the PMOS transistor P16 are also turned off, the output signal Q is equal to 0;

(2) when CLK is 1 and CLKN is 0, the latch enters a latch state, at this time, the PMOS transistors P9 to P13 are turned off, the NMOS transistor N7 is turned on, and at this time, the output terminal of the output terminal signal Q is directly connected to the power ground through the turned-on NMOS transistors N7 to N9, and because of the latch inside the latch, the output signal Q is 0 will be latched all the time and is not affected by the change of the input signal D;

case two: assuming that the input signal D is 1, the input signal DN is 0;

(1) when CLK is 0, and CLKN is 1, the latch is in a conducting state, at which time, PMOS transistors P10 to P13 are all turned on, PMOS transistors P1, P2, P4, and P7 are all turned on, PMOS transistors P3, P5, P6, and P8 are all turned off, NMOS transistors N3, N5, and N6 are all turned on, and NMOS transistors N1, N2, and N4 are all turned off, which will result in node X5 being 0, and X6 being 1; then, the PMOS transistors P18 and P20 will be turned on, and the PMOS transistors P17 and P19 will be turned off, so that X1 ═ X3 ═ X6 ═ 1, and X2 ═ X4 ═ X5 ═ 0, at which time the PMOS transistor P9 and the NMOS transistor N10 are turned on, and the PMOS transistors P14 and P15 are also turned on, while the NMOS transistors N18 and N9 are turned off, but since the NMOS transistor N7 and the PMOS transistor P16 are also turned off, the output signal Q is equal to 1;

(2) when CLK is equal to 1 and CLKN is equal to 0, the latch enters a latch state, at this time, the PMOS transistors P9 to P13 are all turned off, the PMOS transistor P16 is turned on, and the output terminal of the output signal Q is directly connected to the positive power supply terminal through the turned-on PMOS transistors P14 to P16, and the output signal Q is always latched and is not affected by the change of the input signal D due to the latch inside the latch.

Further, fault tolerant operating conditions occur during latch latching, including the following:

the first condition is as follows: when the clock signal CLK is at a high level "1" and the latch latches a low level "0", the sensitive nodes of the latch are X1, X3, X5, X6 and Q; when any one or two of the sensitive nodes are inverted, the latch feedback mechanism of the latch is not completely destroyed, so that the nodes X2 and X4 can restore the inverted one or two sensitive nodes to the original states;

case two: when the clock signal CLK is at high level "1" and the latch latches at high level "1", the sensitive nodes of the latch are X2, X4, X5, X6 and Q; when any one or two of the sensitive nodes are flipped, the latch feedback mechanism of the latch is not completely destroyed, so the nodes X1 and X3 can restore the flipped sensitive node or sensitive nodes to their original states.

Fig. 2 shows a simulation diagram of a charge sharing tolerant D-latch with low power consumption functionality. From the simulation of fig. 2, it can be seen that each time the clock signal CLK is equal to 0, if the input signal D changes, the output signal Q also changes immediately, and the function of latch transmission is realized; when the second, third and fourth clock signals CLK are 1, single-node and double-node fault injection is performed on the internal sensitive node, and it can be found that all the inversions can be recovered, that is, the output signal Q still keeps the original value and is not in a suspended high impedance state; thus, the timing function and fault tolerance function of the constructed latch are correct.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims (6)

1. An anti-charge sharing D latch with low power consumption function, characterized by comprising 20 PMOS transistors P1-P20 and 10 NMOS transistors N1-N10;

the drain of the transistor N10, the source of the transistor P9, the source of the transistor P10 and the source of the transistor P12 are connected to each other and then serve as input terminals of an input signal D of the latch;

the source of the transistor P11 is connected with the source of the transistor P13 to serve as the input end of an input signal DN of the latch, and the input signal D is opposite to the input signal DN;

the gate of the transistor P9, the gates of the transistors P10 to P13 and the gate of the transistor N7 are connected and then serve as the input end of the clock signal CLK of the latch;

after the gate of the transistor N10 is connected to the gate of the transistor P16, the gate serves as an input terminal of a clock signal CLKN of the latch, and the clock signal CLK is opposite to the clock signal CLKN;

the source of the transistor N10, the drain of the transistor P9, the drain of the transistor P16 and the drain of the transistor N7 are connected to each other and then serve as an output terminal of the latch output signal Q and also serve as a node Q;

the sources of the transistors P1-P8 are all connected with the positive pole of the power supply;

the gate of the transistor P7, the gate of the transistor P4, the drain of the transistor P5, the source of the transistor P20, the gate of the transistor N2, the gate of the transistor P14, the gate of the transistor N9, and the drain of the transistor P13 are connected to form a node X4;

the drain of the transistor P7, the drain of the transistor P1, the drain of the transistor N1, the gate of the transistor P17, the gate of the transistor P19, and the gate of the transistor N6 are connected to form a node X6;

the gate of the transistor P1, the gate of the transistor P2, the drain of the transistor P3, the source of the transistor P18, the gate of the transistor N4, the gate of the transistor P15, the gate of the transistor N8, and the drain of the transistor P11 are connected to form a node X2;

the gate of the transistor N1, the gate of the transistor P18, the gate of the transistor P20, the drain of the transistor N6, the drain of the transistor P6, and the drain of the transistor P8 are connected to form a node X5;

the sources of the transistors N1-N6 are all connected with the power ground;

the drain of the transistor P2, the gate of the transistor P5, the source of the transistor P17, the gate of the transistor N3, the gate of the transistor P6, and the drain of the transistor P10 are connected to form a node X1;

the drain of the transistor P17 is connected to the drain of the transistor N12;

the gate of the transistor P3, the drain of the transistor P4, the source of the transistor P19, the gate of the transistor N5, the gate of the transistor P8, and the drain of the transistor P12 are connected to form a node X3;

the drain of the transistor P18 is connected to the drain of the transistor N3;

the drain of the transistor P19 is connected to the drain of the transistor N4;

the drain of the transistor P20 is connected to the drain of the transistor N5;

the source of the transistor P14 is connected to the positive electrode of the power supply, the drain of the transistor P14 is connected to the source of the transistor P15, the drain of the transistor P15 is connected to the source of the transistor P16, the source of the transistor N7 is connected to the drain of the transistor N8, the source of the transistor N8 is connected to the drain of the transistor N9, and the source of the transistor N9 is connected to the ground of the power supply.

2. The D-latch with low power consumption of claim 1, wherein when the clock signal CLK is at low level "0", the latch is turned on; when the clock signal CLK is at high level "1", the latch latches.

3. The charge sharing tolerant D-latch with low power consumption function according to claim 1,

when the clock signal CLK is at a high level "1" and the latch latches a low level "0", the sensitive nodes of the latch are X1, X3, X5, X6 and Q;

when the clock signal CLK is high "1" and the latch latches a high "1", the sensitive nodes of the latch are X2, X4, X5, X6, and Q.

4. The charge sharing tolerant D-latch with low power consumption of claim 1 comprising a normal operating state and a fault tolerant operating state.

5. The charge sharing tolerant D-latch with low power consumption of claim 4, wherein the normal operation state comprises:

the first condition is as follows: assuming that the input signal D is equal to 0, the input signal DN is equal to 1;

(1) when CLK is 0, and CLKN is 1, the latch is in the on state, at which time, PMOS transistors P10 to P13 are all on, PMOS transistors P3, P5, P6, and P8 are all on, PMOS transistors P1, P2, P4, and P7 are all off, NMOS transistors N1, N2, and N4 are all on, and NMOS transistors N3, N5, and N6 are off, which will result in node X5 being 1, and X6 being 0; then, the PMOS transistors P17 and P19 will be turned on, and the PMOS transistors P18 and P20 will be turned off, so that X1 ═ X3 ═ X6 ═ 0, and X2 ═ X4 ═ X5 ═ 1, at which time the PMOS transistor P9 and the NMOS transistor N10 are turned on, and the NMOS transistors N8 and N9 are also turned on, while the PMOS transistors P14 and P15 are turned off, but since the NMOS transistor N7 and the PMOS transistor P16 are also turned off, the output signal Q is equal to 0;

(2) when CLK is 1 and CLKN is 0, the latch enters a latch state, at this time, the PMOS transistors P9 to P13 are turned off, the NMOS transistor N7 is turned on, and at this time, the output terminal of the output terminal signal Q is directly connected to the power ground through the turned-on NMOS transistors N7 to N9, and because of the latch inside the latch, the output signal Q is 0 will be latched all the time and is not affected by the change of the input signal D;

case two: assuming that the input signal D is 1, the input signal DN is 0;

(1) when CLK is 0, and CLKN is 1, the latch is in a conducting state, at which time, PMOS transistors P10 to P13 are all turned on, PMOS transistors P1, P2, P4, and P7 are all turned on, PMOS transistors P3, P5, P6, and P8 are all turned off, NMOS transistors N3, N5, and N6 are all turned on, and NMOS transistors N1, N2, and N4 are all turned off, which will result in node X5 being 0, and X6 being 1; then, the PMOS transistors P18 and P20 will be turned on, and the PMOS transistors P17 and P19 will be turned off, so that X1 ═ X3 ═ X6 ═ 1, and X2 ═ X4 ═ X5 ═ 0, at which time the PMOS transistor P9 and the NMOS transistor N10 are turned on, and the PMOS transistors P14 and P15 are also turned on, while the NMOS transistors N18 and N9 are turned off, but since the NMOS transistor N7 and the PMOS transistor P16 are also turned off, the output signal Q is equal to 1;

(2) when CLK is equal to 1 and CLKN is equal to 0, the latch enters a latch state, at this time, the PMOS transistors P9 to P13 are all turned off, the PMOS transistor P16 is turned on, and the output terminal of the output signal Q is directly connected to the positive power supply terminal through the turned-on PMOS transistors P14 to P16, and the output signal Q is always latched and is not affected by the change of the input signal D due to the latch inside the latch.

6. The charge sharing tolerant D latch with low power consumption of claim 4, wherein a fault tolerant operating state occurs during latching of the latch, the fault tolerant operating state comprising:

the first condition is as follows: when the clock signal CLK is at a high level "1" and the latch latches a low level "0", the sensitive nodes of the latch are X1, X3, X5, X6 and Q; when any one or two of the sensitive nodes are inverted, the latch feedback mechanism of the latch is not completely destroyed, so that the nodes X2 and X4 can restore the inverted one or two sensitive nodes to the original states;

case two: when the clock signal CLK is at high level "1" and the latch latches at high level "1", the sensitive nodes of the latch are X2, X4, X5, X6 and Q; when any one or two of the sensitive nodes are flipped, the latch feedback mechanism of the latch is not completely destroyed, so the nodes X1 and X3 can restore the flipped sensitive node or sensitive nodes to their original states.

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