CN111200429A

CN111200429A - Double-node-overturn-resistant D latch for high-frequency circuit application

Info

Publication number: CN111200429A
Application number: CN202010041914.8A
Authority: CN
Inventors: 郭靖; 杜芳芳
Original assignee: North University of China
Current assignee: North University of China
Priority date: 2020-01-15
Filing date: 2020-01-15
Publication date: 2020-05-26

Abstract

A double-node turnover resistant D latch for high-frequency circuit application belongs to the field of nuclear resistance and reinforcement in the reliability of integrated circuits. The problem that the traditional D latch for resisting charge sharing needs to consume more hardware, larger power consumption and area and seriously influences the reinforcement performance due to more sensitive nodes is solved. The invention comprises 20 NMOS transistors N1-N20 and 12 PMOS transistors P1-P12, only 32 transistors are needed to construct the D latch, thus reducing the area and power consumption expense of the D latch; and the input signal D can be directly transmitted to the output end of the output signal D through the transmission gate constructed by the transistors N20 and P12, so that the transmission delay is also reduced. The invention is suitable for being applied to high-frequency circuits, in particular to the application of the invention in nuclear radiation effect of aerospace, space flight, nuclear power stations and the like.

Description

Double-node-overturn-resistant D latch for high-frequency circuit application

Technical Field

The invention belongs to the field of anti-nuclear reinforcement in the reliability of integrated circuits.

Background

D-latches are widely used in various digital integrated circuits, such as decoders and timing control circuits. However, since the latch has a function of holding information, the radiation particle will change the information held by the latch, thereby causing an error in the electronic system. With the progress of integrated circuit technology, the flip phenomenon has been changed from the conventional one-node flip to the two-node flip due to the influence of charge sharing. The existing charge sharing resistant D-latch needs more than 70 transistors, needs more hardware, has larger area and power consumption overhead, has more than 10 sensitive nodes, has higher probability of being attacked as the more sensitive nodes are, has poorer reliability of the system, and seriously affects the reinforcement performance, and therefore, the above problems need to be solved urgently.

Disclosure of Invention

The invention provides a double-node-overturn-resistant D latch for high-frequency circuit application, which aims to solve the problems that the traditional charge sharing-resistant D latch needs to consume more hardware, has larger power consumption and area and seriously influences the reinforcement performance due to more sensitive nodes.

The D latch against double-node turnover for high-frequency circuit application comprises 20 NMOS transistors N1-N20 and 12 PMOS transistors P1-P12;

the source of the transistor P12, the drain of the transistor N20, the drain of the transistor N16 and the drain of the transistor N18 are connected to each other and then serve as input terminals of an input signal D of the latch;

the drain of the transistor N17 is connected with the drain of the transistor N19 to serve as the input end of an input signal DN of the latch, and the input signal D is opposite to the input signal DN;

the gates of the transistors N16 to N20 are connected with the gate of the transistor P11 and then are used as the input end of the clock signal CLK of the latch;

after the gate of the transistor P12 is connected to the gate of the transistor N13, the gate serves as an input terminal of a clock signal CLKN of the latch, and the clock signal CLK is opposite to the clock signal CLKN;

the drain of the transistor P12, the source of the transistor N20, the drain of the transistor P11 and the drain of the transistor N13 are connected to each other and then serve as an output terminal of the latch output signal Q and also serve as a node Q;

the source of the transistor P1, the source of the transistor P3, the source of the transistor P5, and the source of the transistor P7 are all connected to the positive terminal of the power supply;

the gate of the transistor P1, the drain of the transistor P3, the source of the transistor P4, the gate of the transistor N2, the gate of the transistor P5, the drain of the transistor P7, the source of the transistor P8, the gate of the transistor N4, the drain of the transistor N11 and the drain of the transistor N12 are connected to form a node X5;

a drain of the transistor P1, a source of the transistor P2, a gate of the transistor N1, drains of the transistors N5 to N6, a gate of the transistor P3, a drain of the transistor P5, a source of the transistor P6, a gate of the transistor N3, and a gate of the transistor P7 are connected to each other to form a node X6;

the drain of the transistor P2 is connected to the drain of the transistor N1; the gate of the transistor P2, the gate of the transistor N5, the source of the transistor N4, the gate of the transistor N9, the drain of the transistor N10, the source of the transistor N19, the gate of the transistor P9, and the gate of the transistor N15 are connected to each other to form a node X4;

the source of the transistor N1, the drain of the transistor N7, the gate of the transistor N10, the gate of the transistor P4, the gate of the transistor N11, and the source of the transistor N16 are connected to form a node X1;

the gate of the transistor N7, the source of the transistor N2, the drain of the transistor N8, the gate of the transistor N6, the gate of the transistor P6, the source of the transistor N17, the gate of the transistor P10, and the gate of the transistor N14 are connected to each other to form a node X2;

the sources of the transistors N5-N12 are all connected with the power ground;

the drain of the transistor P4 is connected to the drain of the transistor N2;

the gate of the transistor N8, the source of the transistor N3, the drain of the transistor N9, the gate of the transistor P8, the gate of the transistor N12, and the source of the transistor N18 are connected to form a node X3;

the drain of the transistor P6 is connected to the drain of the transistor N3;

the drain of the transistor P8 is connected to the drain of the transistor N4;

the source of the transistor P9 is connected to the positive electrode of the power supply, the drain of the transistor P9 is connected to the source of the transistor P10, the drain of the transistor P10 is connected to the source of the transistor P11, the source of the transistor N13 is connected to the drain of the transistor N14, the source of the transistor N14 is connected to the drain of the transistor N15, and the source of the transistor N15 is connected to the ground of the power supply.

Preferably, when the clock signal CLK is at low level "0", the latch latches; when the clock signal CLK is high "1", the latch is turned on.

Preferably, when the clock signal CLK is at a low level "0" and the latch latches at a low level "0", the sensitive nodes of the latch are X2, X4, X5, X6, and Q;

when the clock signal CLK is low "0" and the latch latches a high "1", the sensitive nodes of the latch are X1, X3, X5, X6, and Q.

Preferably, the D latch for high frequency circuit application, which is resistant to double node flipping, includes a normal operating state and a fault-tolerant operating state.

Preferably, the normal operating state includes the following cases:

the first condition is as follows: assuming that the input signal D is 1, the input signal DN is 0;

(1) when CLK is 1, CLKN is 0, the latch is in a conducting state, at which time NMOS transistors N16 to N19 are all turned on, NMOS transistors N1, N3, N8, N10, N11, and N12 are all turned on, NMOS transistors N2, N4, N5, N6, N7, and N9 are all turned off, PMOS transistors P1, P2, P5, and P6 are all turned on, and PMOS transistors P3, P4, P7, and P8 are all turned off, which will result in node X1-X3-X6-1, X2-X4-X5-0, at which time NMOS transistors N20 and P12 are turned on, and PMOS transistors P9 and P10 are also turned on, and NMOS transistors N14 and N15 are turned off, but NMOS transistors N67 13 and P368678 are also turned off, so are also turned off as NMOS transistors Q11 output signals;

(2) when CLK is 0 and CLKN is 1, the latch enters a latch state, at this time, NMOS transistors N16 to N20 and PMOS transistor P12 are all turned off, PMOS transistor P11 is turned on, and at this time, the output end of the output signal Q is directly connected to the positive power supply electrode through turned-on PMOS transistors P9 to P11, and because of the latch inside the latch, the output signal Q1 output by the latch will be latched all the time and is not affected by the change of the input signal D;

case two: assuming that the input signal D is equal to 0, the input signal DN is equal to 1;

(1) when CLK is 1 and CLKN is 0, the latch is in a conducting state, at this time, NMOS transistors N16 to N19 are all turned on, NMOS transistors N2, N4, N5, N6, N7, and N9 are all turned on, and NMOS transistors N1, N3, N8, N10, N11, and N12 are all turned off; PMOS transistors P3, P4, P7 and P8 are all turned on, and PMOS transistors P1, P2, P5 and P6 are turned off, which will result in node X1 ═ X3 ═ X6 ═ 0, X2 ═ X4 ═ X5 ═ 1, at which time NMOS transistor N20 and PMOS transistor P12 are turned on, and NMOS transistors N14 and N15 are also turned on, while PMOS transistors P9 and P10 are turned off, and since NMOS transistor N19 and PMOS transistor P15 are turned off, output signal Q ═ 0;

(2) when CLK is equal to 0 and CLKN is equal to 1, the latch enters a latch state, at this time, NMOS transistors N16 to N20 and PMOS transistor P12 are all turned off, NMOS transistor N13 is turned on, and at this time, the output terminal of the output signal Q is directly connected to the power ground through turned-on NMOS transistors N13 to N15, and the signal Q output by the latch is always latched at 0 due to the latch inside the latch and is not affected by the change of the input signal D.

Preferably, the fault tolerant operating condition occurs during latch latching, and includes the following:

the first condition is as follows: when the clock signal CLK is at a low level of "0" and the latch latches at a low level of "0", the sensitive nodes of the latch are X2, X4, X5, X6 and Q; when any one or two of the sensitive nodes are inverted, the latch feedback mechanism of the latch is not completely destroyed, so that the nodes X1 and X3 can restore the inverted one or two sensitive nodes to the original states;

case two: when the clock signal CLK is at a low level of '0' and the latch latches at a high level of '1', the sensitive nodes of the latch are X1, X3, X5, X6 and Q; when any one or two of the sensitive nodes are flipped, the latch feedback mechanism of the latch is not completely destroyed, so the nodes X2 and X4 can restore the flipped sensitive node or sensitive nodes to their original states.

Principle analysis:

the fault-tolerant working state is independent of the specific input value of an input signal D of the latch, the fault-tolerant working state occurs in the latch latching state of the latch and is related to data latched by each node in the latch, and the fault-tolerant working state of the double-node turnover resistant D latch applied to the high-frequency circuit is analyzed as follows: when the clock signal CLK is 0, CLKN is 1, 6 internal nodes X1, X3, X6, X2, X4, X5, and Q is 1, there are 5 internal sensitive nodes of the latch, X1, X3, X5, X6, and Q, where a specific situation when any one or two of the 5 sensitive nodes flip is as follows:

1. when the node X1 is flipped to 0, the NMOS transistors N10, N11 are turned off. However, the original state is maintained as other nodes will not be affected. Therefore, the NMOS transistor N1 and the PMOS transistors P1, P2 will be turned on all the time, so the node X1 will be pulled back to the original 1 state and the state of the output node Q will not change.

2. When node X3 flips due to bombardment, NMOS transistors N8, N12 are turned off, but remain in the original state as the other nodes will not be affected. Therefore, the NMOS transistor N3 and the PMOS transistors P5, P6 will be turned on all the time, so the node X3 will be pulled back to the original 1 state and the state of the output node Q will not change.

3. When node X5 is bombarded to become 1, which will cause NMOS transistors N2 and N4 to turn on temporarily, while PMOS transistors P1 and P5 will be turned off temporarily, the state of node X6 will remain unchanged, so that NMOS transistors N1 and N3 will always turn on. However, since the states of the nodes X1-X4 are not changed, the NMOS transistors N11 and N12 are always turned on. Therefore, node X5 will be pulled back down to 0 and the state of output node Q will not change.

4. When node X6 is bombarded to become 0, NMOS transistors N1 and N3 will be turned off and PMOS transistors P3 and P7 will be turned on. However, since the states of the X1-X4 nodes are unchanged, the NMOS transistors N11 and N12 will be turned on all the time and restore the X6 node.

5. When node Q is bombarded, this flip is easily recovered since all nodes X1 through X6 have not changed.

6. When the nodes X1 and X3 change state, the NMOS transistors N8, N10, N11, and N12 are turned off. However, since the states of the nodes X5 and X6 do not change, the states of the NMOS transistors N1 and N3 and the PMOS transistors P1, P2, P5 and P6 do not change and are always turned on. As a result, the states of the nodes X1 and X3 will be restored to the original 1 state, and the state of the output node Q will not change.

7. When the states of the nodes X1 and X5 change, the NMOS transistors N10 and N11 are turned off, the NMOS transistors N2 and N4 are turned on temporarily, and the PMOS transistors P1 and P5 are turned off temporarily, so that the state of the node X6 remains unchanged, so that the NMOS transistors N1 and N3 are turned on all the time, but since the state of the node X3 is not changed, the NMOS transistor N12 is turned on all the time, and the node X5 is pulled back to the original 0; the NMOS transistors N2 and N4 turn off again, and the PMOS transistors P1 and P5 turn on again, the node X1 is restored by the turned-on P1, P2 and N1, and thus the state of the final output node Q is not changed.

8. When the state of the nodes X1 and X6 changes, the NMOS transistors N10 and N11 are turned off, the NMOS transistors N1 and N3 are turned off, and the PMOS transistors P3 and P7 are turned on, but since the state of the node X3 does not change, the NMOS transistor N12 is turned on all the time and restores the node X6 to 1, and then the NMOS transistor N1 is turned on again, so that the node X1 can be restored by turning on the PMOS transistors P1, P2 and N1.

9. When the states of the nodes X3 and X5 change, the NMOS transistors N8 and N12 are turned off, the NMOS transistors N2 and N4 are turned on temporarily, and the PMOS transistors P1 and P5 are turned off temporarily, so that the state of the node X6 remains unchanged, so that the NMOS transistors N1 and N3 are turned on all the time, but since the state of the node X1 is not changed, the NMOS transistor N11 is turned on all the time, and the node X5 is pulled back to 0; the NMOS transistors N2 and N4 turn off again, and the PMOS transistors P1 and P5 turn on again, the node X3 is restored by the turned-on P5, P6 and N3, and thus the state of the final output node Q is not changed.

10. When the state of the nodes X3 and X6 changes, the NMOS transistors N8 and N12 are turned off, the NMOS transistors N1 and N3 are turned off, and the PMOS transistors P3 and P7 are turned on, but since the state of the node X1 does not change, the NMOS transistor N11 is turned on all the time and restores the node X6 to 1, and then the NMOS transistor N3 is turned on again, so that the node X3 can be restored by turning on the PMOS transistors P5, P6 and N3.

11. When nodes X1 and Q change state, NMOS transistors N10 and N11 are turned off. However, since the other nodes will not be affected and remain in the original state, the NMOS transistor N1 and the PMOS transistors P1 and P2 will be turned on all the time, so the node X1 will be pulled back to the original 1 state, and since the states of the nodes X2 and X4 are not changed, the node Q will be restored to the original 1 state through the turned-on P9, P10 and P11.

12. When the nodes X3 and Q change state, the NMOS transistors N8 and N12 are turned off, but remain as they are since the other nodes will not be affected. Therefore, the NMOS transistor N3 and the PMOS transistors P5 and P6 will be turned on all the time, so the node X3 will be pulled back to the original 1 state, and since the states of the nodes X2 and X4 are not changed, the node Q will be restored to the original 1 state through the turned-on P9, P10 and P11.

13. When the states of the nodes X5 and Q change, the NMOS transistors N2 and N4 are caused to be turned on temporarily, and the PMOS transistors P1 and P5 are turned off temporarily, and the state of the node X6 remains unchanged, so that the NMOS transistors N1 and N3 are turned on all the time, but since the states of the nodes X1 to X4 do not change, the NMOS transistors N11 and N12 are turned on all the time, the node X5 is pulled back to 0, and since the states of the nodes X2 and X4 do not change, the node Q is restored to 1 through the turned-on P9, P10, and P11.

14. When nodes X6 and Q change state, NMOS transistors N1 and N3 will be turned off and PMOS transistors P3 and P7 will be turned on. However, since the states of the nodes X1-X4 are unchanged, the NMOS transistors N11 and N12 will be turned on all the time and the node X6 will be restored. Since the states of the nodes X2 and X4 are unchanged, the node Q will be restored to 1 by turning on P9, P10 and P11.

Compared with the traditional anti-charge sharing D latch which needs more than 60 transistors, the anti-charge sharing D latch only needs 32 transistors, so that the area and power consumption overhead are reduced; the invention enables the input signal D to be directly transmitted to the output end of the output signal D through the transmission gate constructed by the transistors N20 and P12, so that the transmission delay is also reduced;

the invention constructs the anti-charge sharing D latch with less sensitive nodes, the number of the sensitive nodes of the invention is only 5, and compared with the traditional anti-charge sharing D latch, the number of the sensitive nodes can be reduced by at least 50%.

In the traditional D latch for resisting charge sharing, a plurality of C units are copied and then interconnected, so that the fault tolerance of two node overturning is realized at the cost of increasing the number of transistors and the number of sensitive nodes. The invention does not adopt the technology, and the invention utilizes the physical mechanism of radiation inversion to ensure that only one radiation induced voltage can be generated on certain nodes of the circuit, thereby reducing the number of sensitive nodes, reducing the number of used transistors and further reducing the hardware expense.

The invention is especially suitable for aerospace, aerospace flight, nuclear power station and other nuclear radiation effects.

Drawings

FIG. 1 is a schematic diagram of a dual-node flip-flop resistant D-latch for high frequency circuit applications according to the present invention;

fig. 2 is a simulation diagram of the dual-node flip-flop resistant D latch for high-frequency circuit application according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

Referring to fig. 1, illustrating the present embodiment, the D latch for high frequency circuit application, which is resistant to double node flipping, includes 20 NMOS transistors N1 to N20 and 12 PMOS transistors P1 to P12;

the sources of the transistors N5-N12 are all connected with the power ground;

the drain of the transistor P4 is connected to the drain of the transistor N2;

the drain of the transistor P6 is connected to the drain of the transistor N3;

the drain of the transistor P8 is connected to the drain of the transistor N4;

The latch constructed by the invention is realized based on a radiation-turning-resistant physical mechanism, the number of the sensitive nodes of the invention is only 5, and compared with the traditional charge-sharing-resistant D latch, the number of the sensitive nodes can be reduced by at least 50%. The invention has simple structure, can be realized by only 32 transistors, and effectively reduces the layout area and the power consumption overhead; meanwhile, information of the input signal D may be directly transmitted to the output latch node Q through the transistors P16 and N28, and thus, the transmission time is greatly reduced. The invention can realize fault tolerance to any one or two turned sensitive nodes to restore the sensitive nodes to the original state.

Further, when the clock signal CLK is low level '0', the latch latches; when the clock signal CLK is high "1", the latch is turned on.

Further, although there are 7 nodes in total, X1, X2, X3, X4, X5, X6 and Q, depending on the latched value, its sensitive node will be 5, namely:

when the clock signal CLK is at a low level of "0" and the latch latches at a low level of "0", the sensitive nodes of the latch are X2, X4, X5, X6 and Q;

In the preferred embodiment, the specific value latched by the latch is independent of the specific value of the input signal D.

Furthermore, the D latch for resisting double-node overturning applied to the high-frequency circuit comprises a normal working state and a fault-tolerant working state.

Further, the normal operation state includes the following cases:

Further, fault tolerant operating conditions occur during latch latching, including the following:

Fig. 2 shows a simulation diagram of a double-node flip-flop resistant D-latch for high frequency circuit applications. In the simulation of fig. 2, at each clock signal CLK equal to 1, after the input signal D changes, the output signal Q also changes, that is, the function of Q equal to D is realized, that is: the correctness of the time sequence function of the latch is ensured; when single-node and double-node fault injection is carried out when the second, third and fourth clocks CLK are equal to 0, it can be found that the inversions of the nodes can be recovered, therefore, the node Q will keep the original latch value continuously, and it can be seen that the fault-tolerant function of the constructed latch is also correct.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims

1. The D latch which is used for high-frequency circuit and resists double-node turnover is characterized by comprising 20 NMOS transistors N1-N20 and 12 PMOS transistors P1-P12;

the sources of the transistors N5-N12 are all connected with the power ground;

the drain of the transistor P4 is connected to the drain of the transistor N2;

the drain of the transistor P6 is connected to the drain of the transistor N3;

the drain of the transistor P8 is connected to the drain of the transistor N4;

2. The D latch with double node turnover resistance for high-frequency circuit application according to claim 1, wherein when the clock signal CLK is low level "0", the latch latches; when the clock signal CLK is high "1", the latch is turned on.

3. A D-latch resistant to double node flipping for high frequency circuit applications according to claim 1,

4. The high frequency circuit application-oriented double-node flip-flop resistant D-latch according to claim 1, comprising a normal operating state and a fault tolerant operating state.

5. The high frequency circuit application-oriented double-node flip-flop-resistant D latch according to claim 4, wherein the normal operating state comprises the following conditions:

6. A D latch against double node flipping for high frequency circuit applications as claimed in claim 4, wherein fault tolerant operation state occurs during latch latching, fault tolerant operation state comprises the following cases: the first condition is as follows: when the clock signal CLK is at a low level of "0" and the latch latches at a low level of "0", the sensitive nodes of the latch are X2, X4, X5, X6 and Q; when any one or two of the sensitive nodes are inverted, the latch feedback mechanism of the latch is not completely destroyed, so that the nodes X1 and X3 can restore the inverted one or two sensitive nodes to the original states;