CN111198464B

CN111198464B - Pixel array substrate

Info

Publication number: CN111198464B
Application number: CN202010017176.3A
Authority: CN
Inventors: 张翔睿; 丘兆仟
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-05-10
Filing date: 2020-01-08
Publication date: 2022-08-09
Anticipated expiration: 2040-01-08
Also published as: TWI695367B; TW202042206A; CN111198464A

Abstract

A pixel array substrate comprises a substrate, a plurality of scanning lines arranged on the substrate, a plurality of data lines arranged on the substrate, a plurality of touch signal lines arranged on the substrate, a plurality of pixel groups arranged on the substrate to form an array and a plurality of first connecting structures. The data line extends the interlaced scanning line and comprises a first data line. The data lines and the touch signal lines are alternately arranged. Each of the pixel groups includes a plurality of sub-pixels. Each sub-pixel comprises a thin film transistor and a pixel electrode connected with the thin film transistor. The orthographic projection part of the first connecting structure on the substrate correspondingly overlaps the orthographic projection of the touch signal line on the substrate. The first connecting structure crosses the touch signal line to be electrically connected between the thin film transistor and the pixel electrode. The first sub-pixel or the second sub-pixel is electrically connected to the first data line through the first connection structure.

Description

Pixel array substrate

Technical Field

The present invention relates to a pixel array substrate, and more particularly, to a pixel array substrate having a connection structure crossing a touch signal line.

Background

Displays are increasingly used, and their tracks are visible in home audio-visual entertainment, information display boards in public places, displays for electronic competitions and portable electronic products. In order to facilitate the use, the display has a touch function. An electronic device with touch and display functions is called a touch display device. Generally, touch display devices can be classified into an out cell (out cell), an on cell (on cell), and an In-cell (In-cell). In-cell touch display devices have the advantage of being easily made thinner, and thus have become the mainstream of touch display devices in recent years.

The embedded touch display device comprises a pixel array substrate with pixels, data lines and scanning lines and touch wires integrated in the pixel array substrate. In order to integrate the touch traces into the touch traces in the pixel array substrate, another process is mostly used to fabricate the touch traces, which results in a great number of processes for the pixel array substrate.

In addition, the commonly adopted HSD (half source driving) architecture can reduce the number of data lines by half by doubling the number of scan lines, but the driving method thereof adopts column inversion (column inversion), resulting in different polarities of pixels on adjacent rows. Therefore, when the viewer and the display move relatively, vertical stripes (also called shaking stripes) are observed, and the display quality is reduced.

Disclosure of Invention

The invention provides a pixel array substrate, which can reduce the manufacturing cost and achieve the display effect of single-point inversion, thereby improving the display quality.

The pixel array substrate comprises a substrate, a plurality of scanning lines arranged on the substrate, a plurality of data lines arranged on the substrate, a plurality of touch signal lines arranged on the substrate, a plurality of pixel groups arranged on the substrate to form an array and a plurality of first connecting structures. The data line extends the interlaced scanning line and comprises a first data line. The touch signal lines extend to the interlaced scanning lines, and the data lines and the touch signal lines are alternately arranged. Each of the pixel groups includes a plurality of sub-pixels. Each sub-pixel comprises a thin film transistor and a pixel electrode connected with the thin film transistor. The orthographic projection part of the first connecting structure on the substrate correspondingly overlaps the orthographic projection of the touch signal line on the substrate. One of the first connecting structures crosses over one of the touch signal lines to be electrically connected between the thin film transistor and the pixel electrode. The pixel group comprises a first pixel group, the first pixel group comprises a first sub-pixel and a second sub-pixel which are electrically connected to the first data line, and one of the first sub-pixel or the second sub-pixel is electrically connected to the first data line through one of the first connection structures. The first sub-pixel and the second sub-pixel are respectively and electrically connected to two of the scanning lines.

In view of the above, the pixel array substrate according to an embodiment of the invention can complete the arrangement of the pixel electrode and the first connection structure simultaneously in the same step of manufacturing the pixel electrode, so that the electrical connection between the pixel electrode and the corresponding data line can be directly completed without winding, thereby solving the problem of crossing the touch signal line. Therefore, the manufacturing process of the pixel array substrate can be simplified and the manufacturing cost can be reduced. In addition, the arrangement of the first connection structure can enable the sub-pixels on two sides of the data line to have opposite polarities. Therefore, the pixel array substrate of the embodiment can achieve a display effect of single-point inversion by using a driving mode of row inversion. Therefore, the pixel array substrate can avoid the generation of vertical lines/head shaking lines, and the display effect is improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic view of a pixel array substrate according to an embodiment of the invention.

Fig. 2A is a partially enlarged top view of a scan line, a data line and a touch signal line of a pixel array substrate according to an embodiment of the invention.

Fig. 2B is a partially enlarged top view of a common electrode of the pixel array substrate according to an embodiment of the invention.

Fig. 2C is a partially enlarged top view of the pixel array substrate according to an embodiment of the invention.

Fig. 3A is a schematic cross-sectional view of fig. 2C along section line a-a'.

FIG. 3B is a schematic cross-sectional view of FIG. 2C along section line B-B'.

Fig. 4A is a partially enlarged top view of a scan line, a data line and a touch signal line of a pixel array substrate according to another embodiment of the invention.

Fig. 4B is a partially enlarged top view of the common electrode of the pixel array substrate according to an embodiment of the invention.

Fig. 4C is a partially enlarged top view of a pixel array substrate according to another embodiment of the invention.

Fig. 5 shows a cross-sectional view of fig. 4C along section line C-C'.

Fig. 6 is a schematic cross-sectional view illustrating a pixel array substrate according to another embodiment of the invention.

Fig. 7 is a schematic view of a pixel array substrate according to yet another embodiment of the invention.

Fig. 8 is a schematic view of a pixel array substrate according to still another embodiment of the invention.

Description of reference numerals:

10. 10A, 10B, 10C, 10D: pixel array substrate

100: substrate

110: gate insulating layer

120: first protective layer

130: touch signal line

140: second protective layer

160. 160A: common electrode

162: electrode part

164: connecting part

166. 166A: contact part

181: first connecting structure

182: second connecting structure

190: slit

A. B: region(s)

A-A ', B-B ', C-C ': section line

CH. CH2, CH3, CH 4: semiconductor layer

D. D2, D3, D4: drain electrode

DL、DL _n+3 、DL _n+4 、DL _n+5 : data line

DL _n : first data line

DL _n+1 : second data line

DL _n+2 : third data line

G. G2, G3, G4: grid electrode

O1: opening of the container

P1: first pixel group

P2: second pixel group

P3: third pixel group

PA: pixel array

PE, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE 8: pixel electrode

PX 1: first sub-pixel

PX 2: second sub-pixel

PX 3: third sub-pixel

PX 4: the fourth sub-pixel

PX 5: the fifth sub-pixel

PX 6: the sixth sub-pixel

S, S2, S3, S4: source electrode

SL、SL _m+1 、SL _m+2 、SL _m+3 : scanning line

T, T1, T2, T3, T4, T5, T6: thin film transistor

V1: first contact hole

V2, V2': second contact hole

V3: third contact hole

+: positive polarity

-: negative polarity

Detailed Description

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present invention.

In the drawings, the thickness of various elements and the like are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" or "overlapping" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physically and/or electrically connected.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings herein.

As used herein, "about," "substantially," or "approximately" includes the stated value and the average value within an acceptable range of deviation of the stated value, taking into account the particular number of measurements in question and the errors associated with the measurements (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Fig. 1 is a schematic view of a pixel array substrate according to an embodiment of the invention, and fig. 1 schematically illustrates only some components for convenience of illustration and observation. Fig. 2A is a partially enlarged top view of a scan line, a data line and a touch signal line of a pixel array substrate according to an embodiment of the invention. Fig. 2B is a partially enlarged top view of a common electrode of the pixel array substrate according to an embodiment of the invention. Fig. 2C is a partially enlarged top view of the pixel array substrate according to an embodiment of the invention, and fig. 2C shows a part of the covered element as a solid line for convenience of illustration and observation. Referring to fig. 1 and fig. 2C, in the present embodiment, the pixel array substrate 10 includes a substrate 100, a plurality of scan lines SL disposed on the substrate 100, a plurality of data lines DL disposed on the substrate 100, a plurality of touch signal lines 130 (shown in fig. 2A) disposed on the substrate 100, a pixel array PA formed by a plurality of pixel groups (including a first pixel group P1 and a second pixel group P2, which will be described later) disposed on the substrate 100 to form an array, and a plurality of first connection structures 181. The data lines DL extend and cross the scan lines SL, and the extending direction of the data lines DL is perpendicular to the extending direction of the scan lines SL. The touch signal lines 130 extend the interlaced scan lines SL, and the data lines DL and the touch signal lines 130 are alternately arranged. In the present embodiment, the pixel array PA having a plurality of pixel groups can provide a display area electric field under the control of the signals of the scan lines SL and the data lines DL to realize the display operation. In the present embodiment, the pixel array substrate 10 further includes a common electrode 160 disposed on the substrate 100 and a plurality of second connection structures 182 electrically connected between the common electrode 160 and the touch signal line 130. Thus, the common electrode 160 can perform touch sensing operation under the control and transmission of the signals of the touch signal line 130. Therefore, the pixel array substrate 10 can be applied to a touch display device to achieve dual functions of touch and display. It is noted that, for clarity, the touch signal line 130, the common electrode 160, the first passivation layer 120, and the second passivation layer 140 are omitted from fig. 1.

Referring to fig. 1 and fig. 2A, in the present embodiment, the material of the substrate 100 may be glass, quartz, organic polymer or other applicable materials, but the invention is not limited thereto.

As shown in fig. 1, the pixel array PA is disposed on the substrate 100, and a plurality of pixel groups in the pixel array PA are arranged in an array and electrically connected to the scan lines SL and the data lines DL. Each of the pixel groupsThe pixel structure comprises a plurality of sub-pixels, and each sub-pixel comprises a thin film transistor and a pixel electrode connected with the thin film transistor. For example, as shown in fig. 1, the pixel groups include a first pixel group P1 and a second pixel group P2. The first pixel group P1 is electrically connected to a first data line DL of the plurality of data lines DL _n And n is a positive integer greater than or equal to 0. In detail, the first pixel group P1 may include a first sub-pixel PX1 and a second sub-pixel PX2, and the first sub-pixel PX1 and the second sub-pixel PX2 are electrically connected to the first data line DL _n . The second pixel group P2 may include a third subpixel PX3 and a fourth subpixel PX4, and the third subpixel PX3 and the fourth subpixel PX4 are electrically connected to a second data line DL of the plurality of data lines DL _n+1 . By analogy, each pixel group includes a plurality of sub-pixels connected to the same data line DL. Each pixel group may include two, three or more sub-pixels, and the number of the sub-pixels is not limited to that shown in fig. 1 and may be set according to the user's requirement. In the present embodiment, each pixel group array is arranged in a plurality of columns to form the pixel array PA, but the invention is not limited thereto.

Referring to fig. 1 and fig. 2A, in the present embodiment, a plurality of scan lines SL may be disposed in pairs. For example, the scan lines SL include scan lines SL _m 、SL _m+1 、SL _m+2 And m is a positive integer greater than or equal to 0, but the invention is not limited thereto. As shown in FIG. 1, the scan lines SL _m+1 And the scanning line SL _m+2 Are adjacently disposed and located between two adjacent rows of pixel groups (for example, in fig. 1, the first pixel group P1 and the pixel group therebelow). Referring to fig. 1 and fig. 2A, the data lines DL and the touch signal lines 130 are crossed with the scan lines SL, and the data lines DL and the touch signal lines 130 are alternately arranged. As shown in FIG. 2A, two adjacent data lines DL (e.g., the first data line DL) _n And a second data line DL _n+1 ) A touch signal line 130 is disposed therebetween, and a data line DL (e.g. the second data line DL shown in fig. 2A) is disposed between two adjacent touch signal lines 130 _n+1 ). In the present embodiment, the scan lines SL, the data lines DL and the touch signal lines 130 are generally made of metal materials for electrical conductivity. However, the device is not suitable for use in a kitchenHowever, the present invention is not limited thereto. According to other embodiments, other conductive materials such as an alloy, an oxide of a metal material, a nitride of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials may be used for the scan lines SL, the data lines DL and the touch signal lines 130. It should be noted that the numbers of the scan lines SL, the data lines DL and the pixel groups in the pixel array PA shown in fig. 1 are only illustrative, and the actual numbers can be set according to the needs of the user, and are not limited thereto.

As shown in fig. 1, the rows of the pixel groups are located between the scan lines SL. For example, the row of the first pixel group P1 and the second pixel group P2 can be located on the scan line SL _m And a scanning line SL _m+1 In the meantime. In fig. 1, the row of the pixel groups under the first pixel group P1 and the second pixel group P2 can be located on the scan line SL _m+2 And a scanning line SL _m+3 However, the invention is not limited thereto. In the present embodiment, the first sub-pixel PX1 in the first pixel group P1 is electrically connected to the scan line SL _m+1 The second sub-pixel PX2 is electrically connected to the scan line SL _m . The third sub-pixel PX3 in the second pixel group P2 is electrically connected to the scan line SL _m+1 And the fourth sub-pixel PX4 is electrically connected to the scan line SL _m . In other words, under the above arrangement, the first sub-pixel PX1 and the second sub-pixel PX2 in the first pixel group P1 are electrically connected to the first data line DL _n And are respectively electrically connected to two of the scan lines SL, such as the scan line SL _m+1 And a scan line SL _m . As such, the pixel array substrate 10 is a technology applying a half-source driving (HSD) architecture. The half-source driving architecture can reduce the number of source lines by increasing the number of scan lines, so as to achieve the purpose of reducing the number of source drivers. Therefore, the cost of the panel module can be greatly reduced.

In the present embodiment, each of the sub-pixels includes a thin film transistor T including a gate G, a semiconductor layer CH, and a source S and a drain D electrically connected to the semiconductor layer CH (as shown in fig. 6). As shown in fig. 1, the first sub-unitThe thin film transistor T1 of the pixel PX1 is electrically connected to the pixel electrode PE1 and the first data line DL _n . The thin film transistor T2 of the second subpixel PX2 is electrically connected to the pixel electrode PE2 and the first data line DL _n . In the embodiment, as shown in fig. 1, the pixel electrode PE1 of the first sub-pixel PX1 may be directly electrically connected to the drain (not labeled) of the thin film transistor T1 to be electrically connected to the first data line DL _n The pixel electrode PE2 of the second sub-pixel PX2 is electrically connected to the drain electrode D2 (shown in fig. 2C) of the thin film transistor T2 through the first connection structure 181 to be electrically connected to the first data line DL _n However, the present invention is not limited thereto. According to the user's requirement, the pixel electrode PE2 of the second sub-pixel PX2 can be directly electrically connected to the thin film transistor T2 to be electrically connected to the first data line DL _n The pixel electrode PE1 of the first subpixel PX1 is electrically connected to the thin film transistor T1 through the first connection structure 181 to be electrically connected to the first data line DL _n 。

As shown in fig. 1, the first sub-pixel PX1 and the second sub-pixel PX2 are respectively located on the first data line DL _n And the third sub-pixel PX3 and the fourth sub-pixel PX4 are respectively located at the second data line DL _n+1 On both sides of the base. The pixel electrode PE3 of the third subpixel PX3 is electrically connected to the drain electrode D3 of the thin film transistor T3 through the first connection structure 181 to be electrically connected to the second data line DLn ₊₁ The pixel electrode PE4 of the fourth sub-pixel PX4 may be directly electrically connected to the drain electrode D4 of the thin film transistor T4 to be electrically connected to the second data line DL _n+1 。

As can be seen from fig. 1, the polarities of the two adjacent data lines DL may be different. Specifically, the data line DL is driven _n- May make the first data line DL possible _n- Having a first polarity and a second data line DL _n+1 Has a second polarity, and the first polarity is opposite to the second polarity. For example, the first data line DL _n For example, a positive polarity (indicated by + sign in fig. 1), and the second data line DL _n+1 For example negative (indicated by a-sign in fig. 1). By analogy, the third data line DL _n+2 May be positive while the data line DL _n+3 ～DL _n+5 Is sequentially set in a negative, positive, negative, etc. manner. In the present embodiment, the polarity of the data lines DL may be switched once in one frame period (frame period) of the pixel array substrate 10. For example, as shown in FIG. 1, during one frame period, the first data line DL _n Is positive polarity and the second data line DL _n+1 Is negative in polarity; during the next frame period, the first data line DL _n And a second data line DL _n+1 The polarity of (c) is changed to negative polarity and positive polarity, respectively. In other words, the pixel array substrate 10 of the present embodiment can drive the pixel array PA by using a column inversion (column inversion) driving method. However, the conventional column inversion driving method causes the pixel electrodes on the adjacent columns to have opposite polarities, so that the vertical stripes are easily generated, and the display quality is reduced.

It should be noted that in the present embodiment, the pixel electrode PE3 of the third sub-pixel PX3 is located between the pixel electrode PE1 of the first sub-pixel PX1 and the pixel electrode PE2 of the second sub-pixel PX2, and the pixel electrode PE2 of the second sub-pixel PX2 is located between the pixel electrode PE3 of the third sub-pixel PX3 and the pixel electrode PE4 of the fourth sub-pixel PX 4. In detail, as shown in fig. 1, the first pixel group P1 is connected to the first data line DL _n The pixel electrode PE1 of the first subpixel PX1 has a first polarity (positive polarity) and is connected to the first data line DL _n The pixel electrode PE2 of the second sub-pixel PX2 has a first polarity (positive polarity). And the second pixel group P2 is connected to the second data line DL _n+1 The pixel electrode PE3 of the third sub-pixel PX3 has the second polarity (negative polarity). Under the above configuration, the first data line DL is located _n The polarities of the first sub-pixel PX1 and the third sub-pixel PX3 at both sides may be opposite. Further, connected to the second data line DL _n+1 The pixel electrode PE4 of the fourth sub-pixel PX4 has the second polarity (negative polarity). Thus, it is located on the second data line DL _n+1 The polarities of the second sub-pixel PX2 and the fourth sub-pixel PX4 at both sides may be opposite. In other words, the sub-pixels on both sides of any data line DL have opposite polarities, so the pixel array substrate 10 of the present embodiment can realize a single pixel by using a row inversion driving methodDot inversion (dot inversion) display effect. Therefore, the pixel array substrate 10 can avoid the generation of vertical stripes, and improve the display effect.

However, the method for implementing the single-dot inversion display method is affected by the touch signal line 130 and other signal traces integrated in the pixel array PA. The manner and structure of setting the pixel groups will be briefly described below.

First, as shown in fig. 2A, a plurality of scan lines SL, a plurality of data lines DL, and a plurality of touch signal lines 130 are formed on a substrate 100. Next, as shown in fig. 2B, a plurality of thin film transistors (e.g., thin film transistors T2, T3, and T4) are formed and electrically connected to the scan line SL and the data line DL, respectively. Then, the common electrode 160 is disposed on the scan line SL and the data line DL, and the orthographic projection of the common electrode 160 on the substrate 100 does not overlap the orthographic projection of the tft on the substrate 100. Next, as shown in fig. 2C, the pixel electrodes (e.g., the pixel electrodes PE2, PE3, PE4) are disposed on the common electrode 160 in an overlapping manner, and are electrically connected to the thin film transistors through contact holes (e.g., the first contact hole V1).

For example, as shown in fig. 1, the pixel electrode PE1 of the first sub-pixel PX1 and the pixel electrode PE4 of the fourth sub-pixel PX4 may be directly electrically connected to the thin film transistor T1 and the thin film transistor T4, respectively. Taking the fourth sub-pixel PX4 as an example, as shown in fig. 2B and 2C, the thin film transistor T4 of the fourth sub-pixel PX4 includes a gate G4, a semiconductor layer CH4, and a source S4 and a drain D4 electrically connected to the semiconductor layer CH 4. The source S4 is electrically connected to the second data line DL _n+1 The pixel electrode PE4 is electrically connected to the drain electrode D4. Therefore, the pixel electrode of the sub-pixel close to the connected data line DL can be directly electrically connected to the thin film transistor.

Next, the method and structure for disposing the tft and the pixel electrode in the sub-pixel on two opposite sides of the touch signal line will be described.

Fig. 3A is a schematic cross-sectional view of fig. 2C along section line a-a'. FIG. 3B is a schematic cross-sectional view of FIG. 2C along section line B-B'. The following will briefly describe the process and structure of the sub-pixel by taking the second sub-pixel PX2 as an example. As shown in FIGS. 2C and 3As shown in a, the thin film transistor T2 of the second sub-pixel PX2 is disposed on the substrate 100. A gate G2 of the TFT T2 disposed on the substrate 100 and connected to the scan line SL _m And (6) electrically connecting. The substrate 100 and the gate electrode G2 are entirely covered with a gate insulating layer 110. The gate insulating layer 110 is provided with a semiconductor layer CH2, and an orthographic projection of the semiconductor layer CH2 on the substrate 100 overlaps the gate electrode G2. The source S2 of the TFT T2 is electrically connected to the first data line DL _n And a semiconductor layer CH 2. The drain D2 is electrically connected to the semiconductor layer CH 2. As shown in fig. 3B, the touch signal line 130 may be disposed on the gate insulating layer 110 and the first data line DL _n The source S2 and the drain D2 belong to the same film. That is, the touch signal line 130 is integrated in the pixel array PA (shown in fig. 1). In the present embodiment, the gate G2 and the scan line SL _m May be made of the same material in the same process, but the invention is not limited thereto. A source S2, a drain D2 and a first data line DL _n May be made of the same material in the same process, but the invention is not limited thereto.

Similarly, referring to fig. 2B and 2C, the thin film transistor T3 includes a gate G3, a semiconductor layer CH3, and a source S3 and a drain D3 electrically connected to the semiconductor layer CH 3. The source S3 is electrically connected to the second data line DL _n+1 Therefore, the description is omitted.

As shown in fig. 3A and 3B, a first protective film 120 is then covered on the tft T2 and the touch signal line 130. In this embodiment, the material of the first protection layer 120 includes inorganic insulating materials, such as (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the foregoing materials. In the present embodiment, the first protection film 120 is formed on the gate insulating layer 110 in a front surface and thus covers the tfts T3, T4 and other tfts, which is not limited to the embodiment shown in fig. 3A.

In the present embodiment, the common electrode 160 is formed on the first protective layer 120. As shown in fig. 2B and 2C, the electrode portion 162, the contact portion 166, and the connection portion 164 connecting the electrode portion 162 and the contact portion 166 may be formed by patterning the common electrode 160. In the present embodiment, the orthographic projection of the electrode portion 162 of the common electrode 160 on the substrate 100The orthogonal projection of the pixel electrodes (e.g., the pixel electrodes PE2, PE3, PE4) of the overlapping sub-pixels on the substrate 100. For example, as shown in fig. 3A, the orthographic projection of the electrode portion 162 on the substrate 100 overlaps the orthographic projection of the pixel electrode PE3 on the substrate 100. As shown in fig. 2B and 2C, the electrode portion 162 may overlap with pixel electrodes of other sub-pixels, for example: the pixel electrode PE2 and the pixel electrode PE4, but the invention is not limited thereto. As shown in fig. 2B and 2C, the orthographic projection of the contact portion 166 on the substrate 100 is located between the orthographic projections of the two adjacent scan lines SL on the substrate 100. Such as the scanning line SL _m And the scanning line or scanning line SL above it _m+1 And the scanning line SL ₊₂ However, the invention is not limited thereto. The connecting portion 164 may cross the scan line SL (e.g., the scan line SL) _m ) To connect the electrode portion 162 and the contact portion 166. In the present embodiment, the material of the common electrode 160 may be a transparent conductive material, such as a metal oxide, for example, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Tin Oxide (ATO), Aluminum Zinc Oxide (AZO), or Indium Germanium Zinc Oxide (IGZO), but the invention is not limited thereto.

As shown in fig. 2C, 3A and 3B, the second passivation layer 140 is disposed on the first passivation layer 120 over the entire surface and covers the common electrode 160. In this embodiment, the material of the second protection layer 140 includes an inorganic insulating material, such as (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the foregoing materials. Next, a first contact hole V1 penetrating the first protective layer 120 and the second protective layer 140 is formed in the first protective layer 120 and the second protective layer 140. The orthographic projection of the first contact hole V1 on the substrate 100 overlaps the orthographic projection of the drain electrode D2 on the substrate 100 to expose the drain electrode D2. In the embodiment, the method for forming the first contact hole V1 includes photolithography etching or laser drilling, but the invention is not limited thereto.

As shown in fig. 2C, 3A and 3B, the pixel electrodes (e.g., the pixel electrodes PE2, PE3 and PE4) are formed on the second protective layer 140. In the present embodiment, the common electrode 160 is located between the pixel electrode (e.g., the pixel electrode PE3 shown in fig. 3A) and the substrate 100. That is, the pixel array substrate 10 of the present embodiment is a top pixel electrode (top pixel electrode) structure. In the embodiment, the pixel electrodes PE2, PE3, and PE4 further include a plurality of slits 190, but the invention is not limited thereto.

In the embodiment, compared to the pixel electrodes PE2 and PE3, the pixel electrode PE4 can be directly electrically connected to the drain electrode D4 of the thin film transistor T4 through the contact holes on the first protective layer 120 and the second protective layer 140. The pixel electrodes PE2, PE3, and PE4 may be made of transparent conductive materials, such as metal oxides, for example, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Tin Oxide (ATO), Aluminum Zinc Oxide (AZO), or Indium Germanium Zinc Oxide (IGZO), but the invention is not limited thereto.

It is noted that, as shown in fig. 1 and 2C, the second data line DL is closer to the first data line DL than to the neighboring second data line DL _n+1 The touch signal line 130 does not exist between the thin film transistor T4 and the pixel electrode PE4 of the fourth subpixel PX 4. A touch signal line 130 exists between the thin film transistor T2 of the second sub-pixel PX2 located between the third sub-pixel PX3 and the fourth sub-pixel PX4 and the pixel electrode PE 4. In addition, as shown in fig. 1 and fig. 2C, a touch signal line 130 is also present between the thin film transistor T3 of the third subpixel PX3 and the pixel electrode PE3, which are located between the first subpixel PX1 and the second subpixel PX2 (fig. 1 omits the touch signal line 130 for clarity of the drawing, and actually the touch signal line 130 is located between the pixel electrode PE2 and the pixel electrode PE 3). In other words, the drains D2 and D3 belonging to the same layer as the touch signal line 130 cannot cross over to overlap with the corresponding pixel electrodes PE2 and PE 3.

In the present embodiment, the first connection structure 181 and the pixel electrodes PE2 and PE3 may be formed by the same material in the same process. In other words, the first connection structure 181 may belong to the same film layer as the pixel electrodes PE2 and PE 3. Under the above configuration, the first connection structure 181, the pixel electrodes PE2 and PE3 are disposed on the second passivation layer 140, so that the pixel electrode PE2 of the second sub-pixel PX2 crosses the touch signal line 130 to be electrically connected to the thin film transistor T2. Specifically, as shown in fig. 2C and fig. 3A, the orthographic projection of the first connecting structure 181 on the substrate 100 corresponds to the orthographic projection of the touch signal line 130 on the substrate 100. In this way, the first connection structure 181 crosses the touch signal line 130 to electrically connect the pixel electrode PE2, and conformally fills the first contact hole V1 to electrically connect the exposed drain D2 of the thin film transistor T2. Therefore, the first connection structure 181 can be electrically connected between the thin film transistor T2 and the pixel electrode PE2 as a bridge crossing the touch signal line 130. Similarly, the pixel electrode PE3 of the third sub-pixel PX3 may also be electrically connected to the thin film transistor T3 through the first connection structure 181 crossing the touch signal line 130. Therefore, the first connection structure 181 can be electrically connected between the thin film transistor T3 and the pixel electrode PE3 as a bridge crossing the touch signal line 130.

In short, under the above configuration, the pixel electrodes PE2, PE3, PE4 and the first connection structure 181 can be simultaneously disposed through the same mask in the same steps as the steps of fabricating the pixel electrodes PE2, PE3 and PE4, and the problem of crossing the touch signal line 130 can be solved, and the pixel electrodes PE2 and PE3 and the corresponding first data line DL can be directly disposed without routing wires _n And a second data line DL _n+1 The electrical connection of (2). Therefore, the manufacturing process of the pixel array substrate 10 can be simplified and the manufacturing cost can be reduced. Furthermore, by the arrangement of the first connection structure 181, it is also possible to arrange the pixel electrode PE3 of the third sub-pixel PX3 between the pixel electrode PE1 of the first sub-pixel PX1 and the pixel electrode PE2 of the second sub-pixel PX2, and to arrange the pixel electrode PE2 of the second sub-pixel PX2 between the pixel electrode PE3 of the third sub-pixel PX3 and the pixel electrode PE4 of the fourth sub-pixel PX 4. Thus, it is located on the first data line DL _n The pixel electrodes PE1 of the first sub-pixel PX1 and the pixel electrode PE3 of the third sub-pixel PX3 at both sides may have opposite polarities. Therefore, the pixel array substrate 10 of the present embodiment can achieve a display effect of single-dot inversion by using a driving method of row inversion. Therefore, the pixel array substrate 10 can avoid the generation of vertical stripes, and improve the display effect.

Referring to fig. 2C and fig. 3B, in the present embodiment, the pixel array substrate 10 can further electrically connect the common electrode 160 to the touch signal line 130 through the second connection structure 182. In detail, as shown in fig. 3A and 3B, the first contact hole V1 may be formed simultaneously with the second contact hole V2 penetrating through the first protective layer 120 and the second protective layer 140. The orthographic projection of the second contact hole V2 on the substrate 100 overlaps the orthographic projection of the touch signal line 130 on the substrate 100 to expose the touch signal line 130. In the present embodiment, the method for forming the second contact hole V2 includes photolithography etching or laser drilling, but the invention is not limited thereto.

Next, a third contact hole V3 penetrating the second protective layer 140 is formed. The orthographic projection of the third contact hole V3 on the substrate 100 overlaps the orthographic projection of the contact portion 166 of the common electrode 160 on the substrate 100. Specifically, the orthographic projection of the third contact hole V3 on the substrate 100 is located within the orthographic projection of the contact portion 166 on the substrate 100, so as to expose the contact portion 166. In the embodiment, the method for forming the third contact hole V3 includes photolithography etching or laser drilling, but the invention is not limited thereto.

Then, the second connection structure 182 is formed on the second protection layer 140 while forming the pixel electrode (e.g., the pixel electrode PE2) and the first connection structure 181. That is, the second connection structure 182 and the pixel electrode are the same layer. In this embodiment, the orthographic projection of the second connecting structure 182 on the substrate 100 may overlap the orthographic projection of the touch signal line 130 and the contact portion 166 of the common electrode 160 on the substrate 100. As shown in fig. 3B, the second connection structure 182 can be conformally filled in the second contact hole V2 to electrically connect the touch signal line 130, and the second connection structure 182 can be conformally filled in the third contact hole V3 to electrically connect the contact portion 166. Under the above configuration, the common electrode 160 can be electrically connected to the touch signal line 130 through the second connection structure 182, so as to implement the in-cell touch technology. Therefore, the touch signal line 130 is not required to be manufactured by another process so as to simplify the manufacturing process, and the use of masks can be saved, thereby further reducing the manufacturing cost.

The following embodiments follow the reference numerals and part of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and for the part of the description where the same technical contents are omitted, reference may be made to the foregoing embodiments, and the description in the following embodiments is not repeated.

Fig. 4A is a partially enlarged top view of a scan line, a data line and a touch signal line of a pixel array substrate according to another embodiment of the invention. Fig. 4B is a partially enlarged top view of the common electrode of the pixel array substrate according to an embodiment of the invention. Fig. 4C is a partially enlarged top view of a pixel array substrate according to another embodiment of the invention. Fig. 5 is a schematic cross-sectional view of fig. 4C along section line C-C'. The method for manufacturing the pixel array substrate 10A will be briefly described below. Referring to fig. 2A and 4A, fig. 4A is similar to the scan lines SL, the data lines DL and the touch signal lines 130 shown in fig. 2A, and therefore, the description thereof is omitted. Next, referring to fig. 4B, the common electrode 160A is disposed on the substrate 100 to cover a portion of the scan line SL, the data line DL and the touch signal line 130. Then, pixel electrodes (e.g., the pixel electrodes PE2, PE3, and PE4) are overlapped on the common electrode 160A and electrically connected to the scan line SL and the data line DL via thin film transistors (e.g., the thin film transistors T2, T3, and T4).

Referring to fig. 2C and fig. 4C, the pixel array substrate 10A of the present embodiment is similar to the pixel array substrate 10 of fig. 2C, and the main differences are: the orthographic projection of the contact portion 166A of the common electrode 160A on the substrate 100 overlaps the orthographic projection of the touch signal line 130 on the substrate 100. As shown in fig. 4C and fig. 5, the first protection layer 120 has a second through hole V2' penetrating through the first protection layer 120. The orthographic projection of the second through hole V2' on the substrate 100 overlaps the orthographic projection of the touch signal line 130 on the substrate 100 to expose the touch signal line 130. The common electrode 160A is disposed on the first passivation layer 120 and the contact portion 166A conformally fills the second contact hole V2' to electrically connect the touch signal line 130. In the present embodiment, the second passivation layer 140 may be disposed on the first passivation layer 120 entirely to cover the common electrode 160A and be conformally filled in the second contact hole V2', but the invention is not limited thereto. Under the above configuration, compared to the pixel array substrate 10, the common electrode 160A can be directly electrically connected to the touch signal line 130 without the second connection structure 182, so as to implement the in-cell touch technology. Thus, the pixel array substrate 10A can further simplify the manufacturing process and further reduce the manufacturing cost. In addition, the pixel array substrate 10A can also achieve technical effects similar to those of the above embodiments.

Fig. 6 is a schematic cross-sectional view illustrating a pixel array substrate according to another embodiment of the invention. Referring to fig. 3A, 3B and 6, a pixel array substrate 10B of the present embodiment is similar to the pixel array substrate 10 of fig. 3A and 3B, and the main difference is: the pixel array substrate 10B further includes a planarization layer 170. The planarization layer 170 is disposed on the first passivation layer 120 in the region a and the region B, and the second passivation layer 140 is disposed on the planarization layer 170. That is, the planarization layer 170 is located between the first protection layer 120 and the second protection layer 140. In the present embodiment, the area a is exemplified as a relative position diagram of the tft T2 and the first contact hole V1 shown in fig. 3A, and the area B is exemplified as a relative position diagram of the touch signal line 130 and the second contact hole V2 shown in fig. 3B.

As shown in fig. 6, the common electrode 160 is disposed between the planarization layer 170 and the second passivation layer 140. The planar layer 170 has an opening O1. The second protection layer 140 may fill the opening O1. The first passivation layer 120 and the second passivation layer 140 further have a first contact hole V1 passing through the first passivation layer 120 and the second passivation layer 140. The first contact hole V1 overlaps the drain electrode D of the thin film transistor T to expose the drain electrode D. In addition, the orthographic projection of the first contact hole V1 on the substrate 100 is located within the orthographic projection of the opening O1 on the substrate 100. In the present embodiment, the pixel electrode PE and the first connection structure 181 are disposed on the second passivation layer 140, and the first connection structure 181 is conformally filled in the first contact hole V1 to electrically connect the drain D. In this embodiment, the pixel electrode PE may overlap the common electrode 160 to generate an electric field, whereby liquid crystal molecules (not shown) in the display device may be rotated. In the present embodiment, the material of the planarization layer 170 includes an organic insulating material, such as (but not limited to): a polymer material such as a polyimide resin, an epoxy resin or an acryl resin.

As shown in fig. 6, the first passivation layer 120 and the second passivation layer 140 further include a second contact hole V2 penetrating through the first passivation layer 120 and the second passivation layer 140. In the present embodiment, the planarization layer 170 does not overlap the second contact hole V2. The second protective layer 140 further includes a third contact hole V3 penetrating the second protective layer 140. The second contact hole V2 exposes the touch signal line 130, and the third contact hole V3 exposes the common electrode 160. Thus, the second connecting structure 182 is electrically connected to the touch signal line 130 through the second contact hole V2 and electrically connected to the common electrode 160 through the third contact hole V3, so as to electrically connect the common electrode 160 to the touch signal line 130. Under the above configuration, the planarization layer 170 can provide a more planar surface for the pixel array substrate 10B, thereby improving the display quality and performance. The pixel array substrate 10B can also achieve technical effects similar to those of the above embodiments.

Fig. 7 is a schematic view of a pixel array substrate according to yet another embodiment of the invention. Referring to fig. 1 and 7, a pixel array substrate 10C of the present embodiment is similar to the pixel array substrate 10 of fig. 1, and the main difference is: the first sub-pixel PX1 and the second sub-pixel PX2 of the first pixel group P1 are located on the first data line DL _n And a second data line DL _n+1 In the meantime. The third sub-pixel PX3 and the fourth sub-pixel PX4 of the second pixel group P2 are located on the second data line DL _n+1 And the third data line DL _n+2 In the meantime. From another perspective, the first pixel group P1 and the second pixel group P2 are respectively located on the second data line DL _n+1 To opposite sides of the panel. In the present embodiment, the first sub-pixel PX1 and the second sub-pixel PX2 are electrically connected to the first data line DL _n The third sub-pixel PX3 and the fourth sub-pixel PX4 are electrically connected to the second data line DL _n+1 . As shown in fig. 7, the second sub-pixel PX2 may cross a touch signal line (not shown) between the pixel electrode PE1 and the pixel electrode PE2 through the first connection structure 181. Under the above arrangement, the sub-pixels connected to the same data line DL may be located between two adjacent data lines DL.

In the present embodiment, the first data line DL _n Has a first polarity (positive polarity) and a second data line DL _n+1 Having a second polarity (negative polarity). Since the first pixel group P1 is electrically connected to the first data line DL _n Therefore, the first sub-pixel PX1 and the second sub-pixel PX2 have positive polarity. The second pixel group P2 is electrically connected to the second data line DL _n+1 Therefore, the third sub-pixel PX3 and the fourth sub-pixel PX4 have negative polarity. Thus, the poles of two adjacent pixel groupsThe polarity may correspond to the polarity of the connected data line DL. That is, under the row inversion driving, the pixel groups on both sides of any one data line DL may have opposite polarities. Therefore, the pixel array substrate 10C can realize a two-dot inversion (two dots inversion) display effect by using a row inversion driving method. Therefore, the pixel array substrate 10C can avoid the generation of vertical stripes, improve the display effect, and achieve the technical effects similar to those of the above embodiments.

Fig. 8 is a schematic view of a pixel array substrate according to still another embodiment of the invention. Referring to fig. 1 and 8, a pixel array substrate 10D of the present embodiment is similar to the pixel array substrate 10 of fig. 1, and the main difference is: the pixel array substrate 10D further includes a third pixel group P3. The third pixel group P3 includes a fifth sub-pixel PX5 and a sixth sub-pixel PX 6. The fifth sub-pixel PX5 and the sixth sub-pixel PX6 are electrically connected to the third data line DL _n+2 And are respectively located on the third data lines DL _n+2 To opposite sides of the panel. Compared with the first pixel group P1 and the second pixel group P2, the fifth sub-pixel PX5 and the sixth sub-pixel PX6 of the third pixel group P3 are directly and electrically connected to the adjacent third data line DL _n+2 . That is, the polarities of the fifth sub-pixel PX5 and the sixth sub-pixel PX6 and the third data line DL _n+2 The same is true. Therefore, when the third data line DL _n+2 When the first polarity (positive polarity) is provided, the fifth sub-pixel PX5 and the sixth sub-pixel PX6 also have positive polarities.

In the embodiment, the pixel electrode PE7 under the pixel electrode PE5 is electrically connected to the adjacent second data line DL _n+1 Thus, the polarity of PE7 (negative polarity) may be opposite to the polarity of PE5 (positive polarity). In addition, the pixel electrode PE8 under the pixel electrode PE6 is electrically connected to the adjacent data line DL _n+3 Thus, the polarity of PE8 (negative polarity) may be opposite to the polarity of PE6 (positive polarity). Therefore, the third data line DL is electrically connected _n+2 The pixel electrodes PE5, PE6, PE7, and PE8 can still achieve the dot inversion display effect in the direction of the column. Therefore, the pixel array substrate 10D can avoid the generation of vertical stripes, improve the display effect, and achieve the technical effect similar to the above embodimentsAnd (5) fruit.

In summary, the pixel array substrate according to an embodiment of the invention can complete the pixel electrode and the first connection structure simultaneously in the same step of fabricating the pixel electrode, so that the pixel electrode can be directly electrically connected to the corresponding data line without winding, thereby solving the problem of crossing the touch signal line. Therefore, the manufacturing process of the pixel array substrate can be simplified and the manufacturing cost can be reduced.

In addition, through the arrangement of the first connection structure, the pixel electrode of the third sub-pixel may be arranged between the pixel electrode of the first sub-pixel and the pixel electrode of the second sub-pixel, and the pixel electrode of the second sub-pixel may be arranged between the pixel electrode of the third sub-pixel and the pixel electrode of the fourth sub-pixel. Therefore, the pixel electrode of the first sub-pixel and the pixel electrode of the third sub-pixel which are positioned at two sides of the first data line can be respectively and electrically connected to the two data lines with opposite polarities, so that the pixel electrode of the first sub-pixel and the pixel electrode of the third sub-pixel have opposite polarities. Therefore, the pixel array substrate of the embodiment can achieve a display effect of single-point inversion by using a driving mode of row inversion. Therefore, the pixel array substrate can avoid the generation of vertical lines/head shaking lines, and the display effect is improved.

In addition, the second connection structure can be manufactured simultaneously when the pixel electrode is manufactured, and the common electrode can be electrically connected with the touch signal line through the second connection structure to realize the embedded touch technology. Therefore, the touch signal line is not required to be manufactured by using another process so as to simplify the manufacturing process, the use of a mask can be saved, and the manufacturing cost is further reduced.

In addition, the pixel array substrate can also directly electrically connect the common electrode to the touch signal line so as to realize the embedded touch technology. Therefore, the pixel array substrate can simplify the manufacturing process and further reduce the manufacturing cost.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A pixel array substrate, comprising:

a substrate;

a plurality of scanning lines arranged on the substrate;

a plurality of data lines arranged on the substrate, wherein the data lines extend to cross the scanning lines and comprise a first data line;

a plurality of touch signal lines are arranged on the substrate, each touch signal line extends to cross the scanning lines, and the data lines and the touch signal lines are alternately arranged;

a plurality of pixel groups arranged on the substrate and arranged in an array, wherein each of the pixel groups comprises a plurality of sub-pixels, and each sub-pixel comprises a thin film transistor and a pixel electrode connected with the thin film transistor; and

a plurality of first connecting structures, wherein orthographic projection parts of the first connecting structures on the substrate correspondingly overlap orthographic projection of the touch signal lines on the substrate,

wherein one of the first connecting structures crosses over one of the touch signal lines to be electrically connected between the thin film transistor and the pixel electrode,

wherein the pixel groups include a first pixel group, the first pixel group includes a first sub-pixel and a second sub-pixel electrically connected to the first data line, and one of the first sub-pixel or the second sub-pixel is electrically connected to the first data line through one of the first connection structures,

wherein the first sub-pixel and the second sub-pixel are electrically connected to two of the scan lines respectively,

further comprising:

a common electrode disposed on the substrate, wherein part of the common electrode overlaps the pixel groups; and

and the orthographic projection of the second connecting structures on the substrate correspondingly overlaps the orthographic projection of the common electrode on the substrate and the orthographic projection of one of the touch signal lines on the substrate, and one of the second connecting structures is electrically connected between the common electrode and one of the touch signal lines.

2. The pixel array substrate of claim 1, wherein the first connecting structures, the second connecting structures and the pixel electrode are the same layer.

3. The pixel array substrate of claim 1, wherein the common electrode is disposed between the pixel electrode and the substrate, and the pixel electrode has a plurality of slits.

4. The pixel array substrate of claim 1, further comprising:

the first protective layer covers the touch signal lines and the thin film transistor, and the common electrode is configured on the first protective layer; and

a second passivation layer covering the common electrode, the pixel electrode, the first connection structures and the second connection structures being disposed on the second passivation layer,

wherein one of the first connection structures contacts the thin film transistor of one of the sub-pixels through a first contact hole penetrating the first protection layer and the second protection layer,

one of the second connection structures contacts the one of the touch signal lines through a second contact hole penetrating the first protection layer and the second protection layer, and the second connection structure contacts the common electrode through a third contact hole penetrating the second protection layer.

5. The pixel array substrate of claim 4, wherein the first and second passivation layers comprise inorganic insulating materials.

6. The pixel array substrate of claim 4, further comprising:

the common electrode is arranged between the flat layer and the second protective layer, the flat layer is provided with an opening, and the orthographic projection of the first contact hole on the substrate is positioned in the orthographic projection of the opening on the substrate.

7. The pixel array substrate of claim 6, wherein the planarization layer comprises an organic insulating material.

8. The pixel array substrate of claim 1, further comprising:

a second passivation layer covering the common electrode, the pixel electrode and the first connecting structures being disposed on the second passivation layer,

the common electrode contacts one of the touch signal lines through a second contact hole penetrating through the first protective layer, and the second protective layer conformally fills the second contact hole.

9. The pixel array substrate of claim 1, further comprising:

a second pixel group including a third sub-pixel electrically connected to a second data line of the data lines and located between the first sub-pixel and the second sub-pixel,

wherein the third sub-pixel is electrically connected to the second data line through another one of the first connection structures,

wherein the first data line has a first polarity, the second data line has a second polarity, and the first polarity is opposite to the second polarity,

the polarity of the first sub-pixel and the polarity of the second sub-pixel are the same as the polarity of the first data line, and the polarity of the third sub-pixel is the same as the polarity of the second data line.

10. The pixel array substrate of claim 1, further comprising:

a second pixel group including a third sub-pixel and a fourth sub-pixel electrically connected to a second data line of the data lines, respectively, and one of the third sub-pixel or the fourth sub-pixel is electrically connected to the second data line through the other of the first connection structures,

wherein the first pixel group and the second pixel group are respectively located at two opposite sides of the second data line,

the polarity of the first sub-pixel and the second sub-pixel is the same as that of the first data line, and the polarity of the third sub-pixel and the fourth sub-pixel is the same as that of the second data line.

11. The pixel array substrate of claim 1, further comprising:

a second pixel group including a third sub-pixel and a fourth sub-pixel electrically connected to a second data line of the data lines, respectively, the third sub-pixel being electrically connected to the second data line through another one of the first connection structures, the third sub-pixel being located between the first sub-pixel and the second sub-pixel, the second sub-pixel being located between the third sub-pixel and the fourth sub-pixel,

12. The pixel array substrate of claim 11, further comprising:

a third pixel group including a fifth sub-pixel and a sixth sub-pixel electrically connected to a third data line of the data lines, respectively, and the fifth sub-pixel or the sixth sub-pixel is directly electrically connected to the third data line,

wherein the fifth sub-pixel and the sixth sub-pixel are respectively located at two opposite sides of the third data line,

the third data line has the first polarity, and the polarities of the fifth sub-pixel and the sixth sub-pixel are the same as the third data line.