CN111192621A - Word line control method, word line control circuit device, and semiconductor memory - Google Patents
Word line control method, word line control circuit device, and semiconductor memory Download PDFInfo
- Publication number
- CN111192621A CN111192621A CN201811351053.2A CN201811351053A CN111192621A CN 111192621 A CN111192621 A CN 111192621A CN 201811351053 A CN201811351053 A CN 201811351053A CN 111192621 A CN111192621 A CN 111192621A
- Authority
- CN
- China
- Prior art keywords
- row address
- signal
- signals
- output
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000012360 testing method Methods 0.000 claims abstract description 108
- 239000003990 capacitor Substances 0.000 description 14
- 101150014328 RAN2 gene Proteins 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 101150069124 RAN1 gene Proteins 0.000 description 4
- 101100355633 Salmo salar ran gene Proteins 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 101100411667 Arabidopsis thaliana RAN4 gene Proteins 0.000 description 3
- 101150074586 RAN3 gene Proteins 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention provides a word line control method and a word line control circuit device, wherein the method comprises the following steps: the method comprises the steps of obtaining a row address input signal, obtaining a test mode signal, carrying out logic and decoding processing on the row address input signal and the test mode signal, generating a row address control signal, wherein the row address control signal comprises at least two effective starting signals, and controlling at least two non-adjacent word lines to be opened simultaneously according to the at least two effective starting signals. In the test mode, the obtained row address control signal can simultaneously open two non-adjacent word lines by logic operation and decoding processing of the row address input signal and the test mode signal. Because the two non-adjacent word lines do not share the same contact area, the influence on the test caused by the disconnection of the contact area or the too large impedance is eliminated, and the test accuracy is improved.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit technology, and in particular, to a word line control method, a word line control circuit device, and a semiconductor memory.
Background
The finished memory chip typically has some drawbacks: the storage capacitors are small, the capacity of each storage capacitor can be half of that of the standard storage capacitor, or the contact area between the storage capacitors is disconnected or the impedance is too large. Those skilled in the art typically go through testing to find these defects. For example, to test whether the storage capacitors become small, a common test method is to open two adjacent word lines to control two storage capacitors to be opened simultaneously, and the obtained test result is equal to that of the standard storage capacitor, which indicates that the two storage capacitors in the memory chip have a defect that the capacity is too small. The reason why the test is performed by opening the adjacent two word lines is that the test can be continued even if one of the word lines is broken. At this time, the test result obtained is smaller than that of the standard storage capacitor, which indicates that the storage capacitor in the memory chip has a defect of too small capacity.
However, the foregoing testing method is not accurate for testing defects with small storage capacitors. Since two adjacent storage capacitors share one contact region, once the contact region also fails, whether two word lines are simultaneously turned on or only one of the word lines is turned on cannot determine whether the memory chip is a defect with a small storage capacitor.
The above information disclosed in the background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is known to a person of ordinary skill in the art.
Disclosure of Invention
The present invention provides a word line control method, a word line control circuit device and a semiconductor memory, which overcome or alleviate one or more of the problems in the background art and at least provide a useful choice.
As an aspect of the present invention, there is provided a word line control method including:
acquiring a row address input signal;
acquiring a test mode signal;
performing logic and decoding processing on the row address input signal and the test mode signal to generate a row address control signal, wherein the row address control signal comprises at least two effective opening signals;
and controlling at least two non-adjacent word lines to be opened at the same time according to at least two bits of the effective opening signals.
In one embodiment, the row address input signal includes a plurality of row address signals, and the step of performing logic and decoding processing on the row address input signal and the test mode signal to generate the row address control signal includes:
carrying out inverse operation on the test mode signal to generate an inverse test signal;
optionally selecting one of the plurality of row address signals, and carrying out NAND logic operation on the inverted test signal and the selected row address signal to generate an inverted output row address;
performing inverse logic operation on all the row address signals to generate a plurality of corresponding inverse row address signals;
performing AND logic operation on an inverted row address signal corresponding to the selected row address signal and the inverted test signal to generate a normal phase output row address;
and decoding the inverted output row address, the normal phase output row address, the plurality of row address signals and the corresponding plurality of inverted row address signals to obtain the row address control signal.
In one embodiment, the decoding the inverted output row address, the non-inverted output row address, the plurality of row address signals, and the corresponding plurality of inverted row address signals to obtain the row address control signal includes:
performing primary decoding processing on the reverse phase output row address, the normal phase output row address, unselected row address signals and unselected reverse phase row address signals to obtain a first row address control signal, wherein the first row address control signal comprises at least two effective opening signals, and the effective opening signals are used for controlling at least two non-adjacent word lines to be opened simultaneously;
and performing secondary decoding processing on the first row address control signal to obtain a second row address control signal, wherein the second row address control signal is used for controlling at least two non-adjacent word lines to be opened simultaneously.
The invention also provides a word line control circuit device, which comprises a test mode input module, a row address input module and a logic decoding processor, wherein the signal input end of the logic decoding processor is connected to the test mode input module, and the signal output end of the logic decoding processor is correspondingly connected with a plurality of word lines of the storage array;
the test mode input module is used for receiving a test mode signal, and the row address input module is used for receiving a plurality of row address signals; the logic decoding processor is used for carrying out logic and decoding processing on the plurality of row address signals and the test mode signal to generate row address control signals, and the row address control signals comprise at least two effective opening signals and are used for controlling at least two non-adjacent word lines to be opened simultaneously.
In one embodiment, the test mode input module includes a test mode input terminal, a first inverter, and a test mode output terminal, the test mode input terminal is configured to receive the test mode signal, the first inverter is configured to perform an inversion operation on the test mode signal to generate an inverted test signal, and the test mode output terminal is configured to output the inverted test signal.
In an embodiment, the row address input module includes a plurality of row address signal lines and a plurality of second inverters respectively connected to the row address signal lines, where the row address signal lines are respectively configured to receive corresponding row address signals in the row address input signals, and the second inverters are configured to perform an inversion logic operation on the row address signals to obtain a plurality of inverted row address signals.
In one embodiment, the logic decoding processor comprises a first AND gate, a second AND gate and a decoding device;
the first and gate is used for performing and logic operation on the selected row address signal and the inverted test signal to generate an inverted output row address, and comprises a first input end, a second input end and a first output end, wherein the first input end is connected to a row address signal line corresponding to the selected row address signal, and the second input end is connected to the test mode output end and used for receiving the inverted test signal;
the second and gate is used for performing and logic operation on an inverted row address signal corresponding to the selected row address signal and the inverted test signal to generate a normal phase output row address, and comprises a third input end, a fourth input end and a second output end, wherein the third input end is connected to the output end of the second inverter corresponding to the selected row address signal, and the fourth input end is connected to the test mode output end;
the decoding device is used for decoding the inverted output row address, the normal phase output row address, the unselected row address signals and the corresponding inverted row address signals to obtain row address control signals, and the row address control signals comprise at least two effective opening signals which can enable at least two non-adjacent word lines to be opened simultaneously.
In one embodiment, the decoding apparatus includes a first decoder including a set of non-inverting inputs and a set of inverting inputs, and the first output terminal and the second output terminal are respectively connected to the corresponding inverting input and the corresponding non-inverting input.
In one embodiment, the decoding apparatus further comprises a second decoder and a third decoder, the inputs of the second decoder comprising a set of non-inverting inputs for receiving the non-selected row address signals and a set of inverting inputs for receiving the non-selected inverting row address signals;
the inputs of the third decoder include a set of non-inverting inputs for receiving non-selected row address signals and a set of inverting inputs for receiving non-selected inverting row address signals.
In an embodiment, the decoding apparatus further includes a fourth decoder, an input terminal of the fourth decoder is connected to the output terminal of the first decoder, the output terminal of the second decoder, and the output terminal of the third decoder, and an output terminal of the fourth decoder is connected to each of the word lines.
The invention also provides a semiconductor memory comprising the word line control circuit device.
By adopting the technical scheme, the invention has the following advantages: in the test mode, the obtained row address control signal can simultaneously open two non-adjacent word lines by logic operation and decoding processing of the row address input signal and the test mode signal. Because the two non-adjacent word lines do not share the same contact area, the influence on the test caused by the disconnection of the contact area or the too large impedance is eliminated, and the test accuracy is improved.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
Fig. 1 is a schematic flow chart illustrating a word line control method according to an embodiment of the invention.
FIG. 2 is a schematic diagram of a word line structure according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a word line structure according to an embodiment of the invention.
FIG. 4 is a flow chart illustrating another word line control method according to an embodiment of the invention.
Fig. 5 is a schematic structural diagram of a word line control circuit device according to an embodiment of the invention.
FIG. 6 is a schematic diagram of another word line control circuit device according to an embodiment of the present invention.
Description of the drawings:
10-a test mode input module; 11-test mode input; 12-a test mode output;
20-row address input module; 22-output of row address input module;
30-a logical decoding processor; 40-word lines;
32-signal input of logic decoding processor; 33-signal output of logic decoding processor;
201-row address signal lines; 100-a first inverter; 200-a second inverter;
310-a first and gate; 320-a second and gate; 330-decoding means;
311-a first input terminal; 312 — a second input; 313 — a first output;
321-a third input terminal; 322-a fourth input terminal; 323-second output terminal;
331-a first decoder; 332-a second decoder; 333-a third decoder;
334-a fourth decoder;
335 — output of first decoder;
336-output of the second decoder;
337-output of the third decoder.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "square," and "over" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Example one
In a specific embodiment, there is provided a word line control method, as shown in fig. 1, including:
step S10: a row address input signal is acquired.
Step S20: a test mode signal is acquired.
Step S30: and performing logic and decoding processing on the row address input signal and the test mode signal to generate a row address control signal, wherein the row address control signal comprises at least two effective starting signals.
Step S40: and controlling at least two non-adjacent word lines to be opened simultaneously according to at least two effective opening signals.
In the test mode, the row address control signal obtained by the logic operation and decoding processing of the row address input signal and the test mode signal can simultaneously open at least two non-adjacent word lines. As shown in fig. 2, two storage capacitors 400 electrically connected to the sources of the access transistors share one active region 300, two adjacent word lines share one contact region 500, and the contact region 500 serves as a drain. As shown in FIG. 3, since two non-adjacent word lines such as WL1 and WL3 do not share the same contact region, the influence on the test due to the disconnection of the contact region or too large impedance is eliminated, and the test accuracy is improved.
In one embodiment, as shown in fig. 4, the step of generating the row address control signal includes the steps of:
step S101: and carrying out inverse operation on the test mode signal to generate an inverse test signal.
Step S102: and optionally selecting one of the plurality of row address signals, and carrying out NAND logic operation on the inverted test signal and the selected row address signal to generate an inverted output row address.
Step S103: all the row address signals are subjected to inversion logic operation to generate a plurality of corresponding inversion row address signals.
Step S104: and performing NAND logic operation on the inverted row address signal corresponding to the selected row address signal and the inverted test signal to generate a normal phase output row address.
Step S105: and decoding the inverted output row address, the non-inverted output row address, the unselected row address signals and the unselected inverted row address signals to obtain row address control signals.
In one example, as shown in FIG. 6, to enter the test mode, the test mode signal may be set to logic state 1, and the test mode signal may be inverted to generate the logic state of the inverted test signal. The row address input signals RA <8:0> include nine row address signals, which are respectively represented by RA0 to RA8, and all the row address signals are inverted by logical operation to generate corresponding inverted row address signals, which are respectively represented by RAN0 to RAN 8. Any one of RA 0-RA 8, for example RA1, performs NAND operation on the inverted test signal and the selected row address signal to generate an inverted output row address RANint 1. The inverted row address signal RAN1 corresponding to the selected row address signal RA1 is nand-operated with the inverted test signal to generate the non-inverted output row address RAint 1. The decoder receives as input the RANint1, the rainint 1, the RA0, the RA2 to the RA8, the RAN0, and the RAN2 to the RAN8, and generates row address control signals including signals of the same number as the number of word lines to be controlled, for example, 512 word lines. The row address control signal comprises at least two effective starting signals, and can control at least two non-adjacent random word lines in 512 word lines to be simultaneously opened.
In one embodiment, as shown in fig. 4, the decoding the inverted output row address, the non-output row address, the unselected row address signal, and the unselected inverted row address signal to obtain the row address control signal includes:
step S201: performing primary decoding processing on the inverted output row address, the normal output row address, unselected row address signals and unselected inverted row address signals to obtain a first row address control signal, wherein the first row address control signal comprises at least two effective starting signals, and the effective starting signals are used for controlling at least two non-adjacent word lines to be opened simultaneously;
step S202: and carrying out secondary decoding processing on the first row address control signal to obtain a second row address control signal, wherein the second row address control signal is used for controlling at least two non-adjacent word lines to be opened simultaneously.
In an example, as shown in fig. 6, during the first-stage decoding process, three-eight decoders may be selected, wherein one of the three-eight decoders inputs rantin 1 and rait 1 to generate a first control signal, where the first control signal includes a two-bit active-on signal for controlling two non-adjacent word lines to be simultaneously turned on. The remaining two three-eight decoders respectively output and input RA0, RA2 to RA8, RAN0, RAN2 to RAN8, and output a second control signal and a third control signal. The first control signal, the second control signal, and the third control signal constitute a first row address control signal.
Of course, the mode of the first-level decoding process includes, but is not limited to, the above example, and other modes may be selected, and the protection scope of the present embodiment is all within the scope of the present embodiment as long as the purpose of the present example is achieved.
Example two
In another embodiment, as shown in FIG. 5, a word line control circuit apparatus is provided, which includes a test mode input module 10, a row address input module 20, and a logic decoding processor 30.
The output 12 of the test mode input block and the output 22 of the row address input block are connected to the signal input 32 of the logic decoding processor, and the signal output 33 of the logic decoding processor 30 is connected to a plurality of word lines 40 of the memory array.
The test mode input module 10 is configured to receive a test mode signal, the row address input module 20 is configured to receive a plurality of row address signals, the logic decoding processor 30 is configured to perform logic and decoding processing on the plurality of row address signals and the test mode signal to generate a row address control signal, and the row address control signal includes at least two valid enable signals and is configured to control at least two non-adjacent word lines 40 to be simultaneously turned on according to the at least two valid enable signals.
In one embodiment, as shown in fig. 6, the test mode input module 10 includes a test mode input terminal 11, a first inverter 100, and a test mode output terminal 12, wherein the test mode input terminal 11 is configured to receive a test mode signal, the first inverter 100 is configured to invert the test mode signal to generate an inverted test signal, and the test mode output terminal 12 is configured to output the inverted test signal.
In one embodiment, the row address input module 20 includes a plurality of row address signal lines 201 and a plurality of second inverters 200 respectively connected to the row address signal lines, where the row address signal lines 201 are respectively configured to receive corresponding row address signals in the row address input signal, and the second inverters 200 are configured to perform an inversion logic operation on the row address signals to obtain inverted row address signals.
As shown in fig. 6, in an example, the row address input module 20 includes nine row address signal lines 201 for inputting corresponding row address signals RA0 through RA8, the nine row address signal lines 201 are connected to the nine second inverters 200 in a one-to-one correspondence, and output terminals 202 of the nine corresponding second inverters output inverted row address signals RAN0 through RAN 8. Of course, the number of row address signal lines included in the row address input module 20 is not limited to the above embodiments, and the number of signal lines is determined according to the number of row addresses required to be input, and is within the protection scope of the present embodiment.
In one embodiment, the logic decoding processor 30 comprises a first and gate 310, a second and gate 320, and a decoding device 330.
The first and gate 310 is used for performing a nand logic operation on the selected row address signal and the inverted test signal to generate an inverted output row address. The first and gate 310 includes a first input terminal 311, a second input terminal 312, and a first output terminal 313. The first input terminal 311 is connected to the selected row address signal line, the second input terminal 312 is connected to the test mode output terminal 12 for receiving the inverted test signal, and the first output terminal 313 is connected to the decoding device 330.
The second and gate 320 is configured to perform a nand operation on an inverted row address signal corresponding to the selected row address signal and an inverted test signal to generate a non-inverted output row address, the second and gate 320 includes a third input end 321, a fourth input end 322, and a second output end 323, the third input end 321 is connected to the output end 202 of the second inverter corresponding to the selected row address signal line, the fourth input end 322 is connected to the test mode output end 12, and the second output end 323 is connected to the decoding device 330.
The decoding device 330 decodes the inverted output row address, the non-inverted output row address, the unselected row address signal, and the unselected inverted row address signal to obtain a row address control signal, which includes a two-bit effective turn-on signal that can turn on two non-adjacent word lines at the same time. The decoding input terminal of the decoding device 30 is connected to the first output terminal 313, the second output terminal 323, the unselected row address signal line 201 and the unselected output terminal 202 of the second inverter, respectively, and the decoding output terminal is connected to each word line 40.
The first and gate 310 performs a nand operation on the inverted test signal and the selected row address signal RA1 to output an inverted output row address RANint 1. The second and gate 320 performs nand operation on the inverted row address signal RAN1 corresponding to the selected row address signal RA1 and the inverted test signal to generate the non-inverted output row address RAint 1.
In one embodiment, the decoding apparatus 30 includes a first decoder 331, the first decoder 331 includes a set of non-inverting inputs and a set of inverting inputs, and the first output 313 and the second output 323 are respectively connected to the corresponding inverting inputs and non-inverting inputs of the first decoder 331. The decoding means 330 further comprises a second decoder 332 and a third decoder 333, the inputs of the second decoder 332 comprising a set of non-inverting inputs for receiving a plurality of row address signals and a set of inverting inputs for receiving an inverted row address signal. The inputs of the third decoder 333 include a set of non-inverting inputs for receiving a plurality of row address signals and a set of inverting inputs for receiving an inverted row address signal.
Specifically, the first decoder 331 includes three non-inverting inputs, namely RA0, RA1, and RA2 inputs, and three inverting inputs, namely RAN0, RAN1, and RAN2 inputs. The RA0 input terminal and the RA2 input terminal are respectively connected to the row address signal line 201 of the row address input module 20 for receiving the row address signal RA0 and the row address signal line 201 of the row address signal RA 2. The RAN0 input and the RAN2 input are connected to a second inverter output 202 for the output RAN0 and a second inverter output RAN2 for the output RAN2, respectively, in the row address input module 20. The input terminals of RA1 of the first decoder 331 are connected to the second output terminals 323 of the output inverted output row address rantin 1 of the second and gate 320 in a one-to-one correspondence, and the input terminals of RAN1 of the first decoder 331 are connected to the second output terminals 323 of the output non-inverted output row address RAint1 of the first and gate 310 in a one-to-one correspondence.
The second decoder 332 includes three non-inverting inputs, namely RA3, RA4, RA5 inputs, and three inverting inputs, namely RAN3, RAN4, RAN5 inputs. The RA3 input terminal, the RA4 input terminal, and the RA5 input terminal are respectively connected to three row address signal lines 201 of the row address input block 20 for receiving row address signals RA3, RA4, and RA5 in a one-to-one correspondence. The RAN3 input, the RAN4 input, and the RAN5 input are respectively connected to three second inverter outputs 202 for outputting RAN3, RAN4, and RAN5 in the row address input module 20 in a one-to-one correspondence.
The third decoder 333 includes three non-inverting inputs, namely RA6, RA7, RA8 inputs, and three inverting inputs, namely RAN6, RAN7, RAN8 inputs. The RA6 input terminal, the RA7 input terminal, and the RA8 input terminal are respectively connected to three row address signal lines 201 of the row address input block 20 for receiving row address signals RA6, RA7, and RA8 in a one-to-one correspondence. The RAN6 input, the RAN7 input, and the RAN8 input are respectively connected to three second inverter outputs 202 for outputting RAN6, RAN7, and RAN8 in the row address input module 20 in a one-to-one correspondence.
The decoding device 30 further comprises a fourth decoder 334, an input of the fourth decoder 334 being connected to the output 335 of the first decoder, the output 336 of the second decoder and the output 337 of the third decoder, an input of the first decoder, an input of the second decoder and an input of said third decoder forming the signal input 32 of the logical decoding processor, an output of the fourth decoder forming the signal output 33 of the logical decoding processor being connected to each word line 40. The second row address control signal output by the fourth decoder 334 controls the on and off of each of the word lines, and controls the simultaneous on of two non-adjacent word lines 40 according to the two-bit valid on signal.
As shown in FIG. 6, 516 word lines 40, WL0-WL512 respectively, are included in the memory array. The number of the word lines 40 connected finally is adjusted within a suitable range according to actual needs, and is within the protection range of the embodiment.
EXAMPLE III
The invention also provides a semiconductor memory comprising the word line control circuit device.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present invention, and these should be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
1. A word line control method, comprising:
acquiring a row address input signal;
acquiring a test mode signal;
performing logic and decoding processing on the row address input signal and the test mode signal to generate a row address control signal, wherein the row address control signal comprises at least two effective opening signals;
and controlling at least two non-adjacent word lines to be opened at the same time according to at least two bits of the effective opening signals.
2. The method of claim 1, wherein the row address input signal comprises a plurality of row address signals, and wherein the step of performing logic and decoding processing on the row address input signal and the test mode signal to generate row address control signals comprises:
carrying out inverse operation on the test mode signal to generate an inverse test signal;
optionally selecting one of the plurality of row address signals, and carrying out NAND logic operation on the inverted test signal and the selected row address signal to generate an inverted output row address;
performing inverse logic operation on all the row address signals to generate a plurality of corresponding inverse row address signals;
performing AND logic operation on an inverted row address signal corresponding to the selected row address signal and the inverted test signal to generate a normal phase output row address;
and decoding the reverse phase output row address, the normal phase output row address, the unselected row address signals and the unselected reverse phase row address signals to obtain the row address control signal.
3. The method of claim 2, wherein decoding the inverted output row address, the non-inverted output row address, the unselected row address signals, and the unselected inverted row address signals to obtain the row address control signal comprises:
performing primary decoding processing on the reverse phase output row address, the normal phase output row address, unselected row address signals and unselected reverse phase row address signals to obtain a first row address control signal, wherein the first row address control signal comprises at least two effective opening signals, and the effective opening signals are used for controlling at least two non-adjacent word lines to be opened simultaneously;
and performing secondary decoding processing on the first row address control signal to obtain a second row address control signal, wherein the second row address control signal is used for controlling at least two non-adjacent word lines to be opened simultaneously.
4. A word line control circuit device is characterized by comprising a test mode input module, a row address input module and a logic decoding processor, wherein the output end of the test mode input module and the output end of the row address input module are connected to the signal input end of the logic decoding processor, and the signal output end of the logic decoding processor is correspondingly connected with a plurality of word lines of a storage array;
the test mode input module is used for receiving a test mode signal, the row address input module is used for receiving a plurality of row address signals, the logic decoding processor is used for carrying out logic and decoding processing on the plurality of row address signals and the test mode signal to generate a row address control signal, and the row address control signal comprises at least two-bit effective opening signals and is used for controlling at least two non-adjacent word lines to be opened simultaneously.
5. The apparatus of claim 4, wherein the test mode input module comprises a test mode input to receive the test mode signal, a first inverter to invert the test mode signal to generate an inverted test signal, and the test mode output to output the inverted test signal.
6. The apparatus of claim 5, wherein the row address input module comprises a plurality of row address signal lines and a plurality of second inverters respectively connected to the row address signal lines, the row address signal lines respectively receiving corresponding row address signals of the row address input signals, the second inverters performing an inversion logic operation on the row address signals to obtain a plurality of inverted row address signals.
7. The apparatus of claim 6, wherein the logical decode processor comprises a first AND gate, a second AND gate, and a decode means;
the first and gate is used for performing and logic operation on the selected row address signal and the inverted test signal to generate an inverted output row address, and comprises a first input end, a second input end and a first output end, wherein the first input end is connected to a row address signal line corresponding to the selected row address signal, and the second input end is connected to the test mode output end and used for receiving the inverted test signal;
the second and gate is used for performing and logic operation on an inverted row address signal corresponding to the selected row address signal and the inverted test signal to generate a normal phase output row address, and comprises a third input end, a fourth input end and a second output end, wherein the third input end is connected to the output end of the second inverter corresponding to the selected row address signal, and the fourth input end is connected to the test mode output end;
the decoding device is used for decoding the reverse phase output row address, the normal phase output row address, the unselected row address signals and the unselected reverse phase row address signals to obtain row address control signals, and the row address control signals comprise at least two effective opening signals which can enable at least two non-adjacent word lines to be opened simultaneously.
8. The apparatus of claim 7 wherein said decoding means comprises a first decoder including a set of non-inverting inputs and a set of inverting inputs, said first output and said second output being coupled to a corresponding inverting input and a corresponding non-inverting input, respectively.
9. The apparatus of claim 8 wherein said decoding means further comprises a second decoder and a third decoder, the inputs of said second decoder comprising a set of non-inverting inputs for receiving non-selected row address signals and a set of inverting inputs for receiving non-selected inverting row address signals;
the inputs of the third decoder include a set of non-inverting inputs for receiving non-selected row address signals and a set of inverting inputs for receiving non-selected inverting row address signals.
10. The apparatus of claim 9 wherein said decoding means further comprises a fourth decoder having an input coupled to an output of said first decoder, an output of said second decoder, and an output of said third decoder;
an input of the first decoder, an input of the second decoder, and an input of the third decoder form a signal input of the logic decoding processor, and an output of the fourth decoder forms a signal output of the logic decoding processor, and is connected to each of the word lines.
11. A semiconductor memory comprising the word line control circuit arrangement as claimed in any one of claims 4 to 10.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811351053.2A CN111192621B (en) | 2018-11-14 | 2018-11-14 | Word line control method, word line control circuit device, and semiconductor memory |
| PCT/CN2019/116063 WO2020098549A1 (en) | 2018-11-14 | 2019-11-06 | Word line control method, word line control circuit device and semiconductor memory |
| US17/171,307 US11693584B2 (en) | 2018-11-14 | 2021-02-09 | Word line control method, word line control circuit device and semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811351053.2A CN111192621B (en) | 2018-11-14 | 2018-11-14 | Word line control method, word line control circuit device, and semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111192621A true CN111192621A (en) | 2020-05-22 |
| CN111192621B CN111192621B (en) | 2024-08-23 |
Family
ID=70708956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811351053.2A Active CN111192621B (en) | 2018-11-14 | 2018-11-14 | Word line control method, word line control circuit device, and semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111192621B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5831925A (en) * | 1996-12-03 | 1998-11-03 | Texas Instruments Incorporated | Memory configuration circuit and method |
| KR20010059018A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Redundant word line disturbance test device and method thereof |
| US20010014043A1 (en) * | 2000-02-11 | 2001-08-16 | Samsung Electronics Co., Ltd. | MRAD test circuit, semiconductor memory device having the same and MRAD test method |
| US20020067644A1 (en) * | 2000-12-06 | 2002-06-06 | Seo Young-Soon | Wordline driver for ensuring equal stress to wordlines in multi row address disturb test and method of driving the wordline driver |
| US6658609B1 (en) * | 1998-11-20 | 2003-12-02 | Fujitsu Limited | Semiconductor memory device with a test mode |
| CN1892903A (en) * | 2005-06-30 | 2007-01-10 | 富士通株式会社 | Semiconductor memory |
| US20080279021A1 (en) * | 2007-05-11 | 2008-11-13 | Hynix Seminconductor, Inc. | Multi-wordline test control circuit and controlling method thereof |
| CN102024498A (en) * | 2009-09-21 | 2011-04-20 | 旺宏电子股份有限公司 | Integrated circuit device for storage and operation method thereof |
| CN102831927A (en) * | 2011-06-14 | 2012-12-19 | 芯成半导体（上海）有限公司 | Circuit capable of entering into internal test mode of ASRAM chip |
| CN108564982A (en) * | 2018-03-28 | 2018-09-21 | 睿力集成电路有限公司 | Memory device and test circuit for it |
| CN208834750U (en) * | 2018-11-14 | 2019-05-07 | 长鑫存储技术有限公司 | Word line control circuit device and semiconductor memory |
-
2018
- 2018-11-14 CN CN201811351053.2A patent/CN111192621B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5831925A (en) * | 1996-12-03 | 1998-11-03 | Texas Instruments Incorporated | Memory configuration circuit and method |
| US6658609B1 (en) * | 1998-11-20 | 2003-12-02 | Fujitsu Limited | Semiconductor memory device with a test mode |
| KR20010059018A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Redundant word line disturbance test device and method thereof |
| US20010014043A1 (en) * | 2000-02-11 | 2001-08-16 | Samsung Electronics Co., Ltd. | MRAD test circuit, semiconductor memory device having the same and MRAD test method |
| US20020067644A1 (en) * | 2000-12-06 | 2002-06-06 | Seo Young-Soon | Wordline driver for ensuring equal stress to wordlines in multi row address disturb test and method of driving the wordline driver |
| CN1892903A (en) * | 2005-06-30 | 2007-01-10 | 富士通株式会社 | Semiconductor memory |
| US20080279021A1 (en) * | 2007-05-11 | 2008-11-13 | Hynix Seminconductor, Inc. | Multi-wordline test control circuit and controlling method thereof |
| CN102024498A (en) * | 2009-09-21 | 2011-04-20 | 旺宏电子股份有限公司 | Integrated circuit device for storage and operation method thereof |
| CN102831927A (en) * | 2011-06-14 | 2012-12-19 | 芯成半导体（上海）有限公司 | Circuit capable of entering into internal test mode of ASRAM chip |
| CN108564982A (en) * | 2018-03-28 | 2018-09-21 | 睿力集成电路有限公司 | Memory device and test circuit for it |
| CN208834750U (en) * | 2018-11-14 | 2019-05-07 | 长鑫存储技术有限公司 | Word line control circuit device and semiconductor memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111192621B (en) | 2024-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7990788B2 (en) | Refresh characteristic testing circuit and method for testing refresh using the same | |
| JPS5928560Y2 (en) | Storage device with redundant bits | |
| US9922726B2 (en) | Semiconductor memory device and method for detecting weak cells | |
| US6551846B1 (en) | Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration | |
| US10497431B2 (en) | Static random-access memory device, redundant circuit thereof, and semiconductor device | |
| US10665316B2 (en) | Memory device | |
| JP2006268971A (en) | Semiconductor memory device and its test method | |
| EP3896693B1 (en) | Memory and addressing method therefor | |
| US7605434B2 (en) | Semiconductor memory device to which test data is written | |
| US8248874B2 (en) | Semiconductor memory apparatus and probe test control circuit therefor | |
| US6741510B2 (en) | Semiconductor memory device capable of performing burn-in test at high speed | |
| US10535418B2 (en) | Memory device including repair circuit and operation method thereof | |
| US11693584B2 (en) | Word line control method, word line control circuit device and semiconductor memory | |
| US5710737A (en) | Semiconductor memory device | |
| US10643731B2 (en) | Semiconductor memory apparatus | |
| CN111192621B (en) | Word line control method, word line control circuit device, and semiconductor memory | |
| US8416638B2 (en) | Semiconductor memory device removing parasitic coupling capacitance between word lines | |
| JP4068241B2 (en) | Burn-in control circuit for semiconductor memory device | |
| US7548479B2 (en) | Semiconductor memory device and manufacturing method thereof | |
| CN114388048A (en) | Repair circuit and memory | |
| US8687454B2 (en) | Semiconductor storage apparatus and semiconductor integrated circuit | |
| US6256257B1 (en) | Memory device including a burn-in controller for enabling multiple wordiness during wafer burn-in | |
| CN212516572U (en) | Repair circuit and memory | |
| KR102221417B1 (en) | Biuilt-in test circuit of semiconductor apparatus | |
| US11189342B2 (en) | Memory macro and method of operating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |