US20010014043A1 - MRAD test circuit, semiconductor memory device having the same and MRAD test method - Google Patents
MRAD test circuit, semiconductor memory device having the same and MRAD test method Download PDFInfo
- Publication number
- US20010014043A1 US20010014043A1 US09/766,733 US76673301A US2001014043A1 US 20010014043 A1 US20010014043 A1 US 20010014043A1 US 76673301 A US76673301 A US 76673301A US 2001014043 A1 US2001014043 A1 US 2001014043A1
- Authority
- US
- United States
- Prior art keywords
- signal
- test
- control signal
- word lines
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/32—Serial access; Scan testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C2029/2602—Concurrent test
Definitions
- the present invention relates to a semiconductor memory device, and more particularly, to a test circuit that shortens the time required to test semiconductor memory devices and a semiconductor memory device having the same.
- semiconductor memory devices have progressed significantly, with continual increases in performance and integration. As memory sizes increases, the time required to test the memories also increases. The increased test time delays the production cycle. Thus, efforts to shorten test times are ever on-going. Circuits have been designed and added to semiconductor devices to reduce test time. Meanwhile, in order to improve the input and output speed of semiconductor memory devices, semiconductor memory devices include a plurality of banks. A plurality of bits can be simultaneously inputted to/outputted from semiconductor memory devices including a plurality of banks.
- RCR refresh cycle reduction
- a plurality of banks are selected by a row active command. Therefore, a plurality of word lines are simultaneously activated by a one-time row active command, which allows a reduction in the test time.
- word lines within a plurality of banks are selected at the same time, more bit line sense amplifiers are operated at the same time, and more current is consumed accordingly. Since there is a limit to the amount of consumable current in a semiconductor memory device, the number of word lines which can be activated at the same time in a RCR mode is limited. Accordingly, a need exists for a device and method for conducting tests of a semiconductor memory device in a speeding fashion while minimizing current consumption.
- the present invention provides a semiconductor memory device that shortens testing time while minimizing the increase of current consumption.
- the present invention further provides a test control circuit for controlling a predetermined test mode operation in such a way as to shorten the testing time in a semiconductor memory device.
- the present invention further provides a test method of shortening the test time in a semiconductor memory device.
- a semiconductor memory device including at least one memory array including a plurality of word lines sharing a bit line sense amplifier.
- the semiconductor device at least two word lines among the plurality of word lines including the bit line sense amplifier are activated at the same time in a test mode.
- test circuit in a semiconductor memory device including at least one memory array which has a plurality of word lines sharing a bit line sense amplifier.
- the test circuit includes a control signal generating circuit which generates a plurality of control signals at least one of which is activated in a test mode, and a row decoder which activates at least two word lines in response to the activated control signal and a predetermined row address signal comprised of a plurality of bits.
- test method in a semiconductor memory device including at least one memory array which has a plurality of word lines sharing a bit line sense amplifier.
- the test method includes the steps of: a) inputting a predetermined MRAD test signal through address pins; b) activating at least one control signal according to the predetermined MRAD test signal; and c) selecting at least two word lines at the same time according to the control signal and a predetermined row address signal.
- the above test circuit and test method can shorten the testing time of a semiconductor memory device to be shortened without increasing current consumption.
- FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention
- FIG. 2 is a block diagram showing a test circuit according to an embodiment of the present invention.
- FIG. 3 is a detailed diagram showing a predecoder in the test circuit of FIG. 2;
- FIG. 4 is a flowchart showing a test method according to an embodiment of the present invention.
- the semiconductor memory device includes at least one memory array 122 and bit line sense amplifier 128 .
- the memory array 122 is a portion of a semiconductor memory 12 in which memory cells for storing information are in the memory array 122 arranged in columns and rows.
- a word line is a line connected in a row direction within the memory array, and the word line selects memory cells where data is inputted and outputted.
- a bit line is a line connected in a column direction within the memory array 122 to which data is inputted and outputted.
- One memory array 122 includes a plurality of word lines which shares one bit line sense amplifier 128 .
- Memory cells within the memory array are selected in units of a word line. Data of the memory cells selected by a word line is outputted to the bit line to be sensed and amplified in the bit line sense amplifier 128 . Among the thus-sensed and amplified data, only the data of a column selected by a column decoder 126 is finally outputted from the semiconductor memory device through an input/output circuit 18 .
- the memory array 122 can include one or more sub-arrays, and a bit line sense amplifier can be provided for each sub-array.
- the semiconductor memory device includes a multi-row active disturb (MRAD) test circuit 14 .
- the MRAD test circuit 14 includes a control signal generating circuit 142 and a row decoder 124 .
- the MRAD test circuit according to the present invention will be described in detail with reference to FIG. 2 later.
- the control signal generating circuit 142 generates a plurality of control signals, which are denoted by PMRAD. At least one control signal PMRAD is activated in an MRAD test mode. In other modes, a control signal PMRAD is not activated.
- the MRAD test mode is a test mode in which a semiconductor memory device is tested in such a way that at least two of a plurality of word lines within the memory array 122 sharing the bit line sense amplifier 128 are activated at the same time to shorten the test time.
- a row decoder 124 selects and activates one or more word lines in response to a control signal PMRAD and a row address signal.
- the row decoder 124 simultaneously activates at least two of a plurality of word lines sharing the bit line sense amplifier, in response to an activated control signal PMRAD and a row address signal.
- the memory array 122 , bit line sense amplifier 128 , row decoder 124 , and column decoder 126 may form a bank.
- the semiconductor memory device according to a preferred embodiment of the present invention may include a plurality of banks having such a structure.
- FIG. 2 is a block diagram showing a test circuit according to an embodiment of the present invention.
- the test circuit according to the present invention is called an MRAD test circuit.
- an MRAD test circuit 14 according to a preferred embodiment of the present invention includes a control signal generating circuit 142 and a row decoder 124 .
- the MRAD test circuit 14 may include a row address latch signal generating circuit 24 which generates a row address latch signal denoted by PDRAE.
- the row address latch signal PDRAE causes the row decoder 124 to latch a row address signal.
- the row address signal includes a plurality of bits and they are inputted through address pins.
- control signal generating circuit 142 does not activate control signal PMRAD, and then the row decoder 124 receives for decoding a row address signal.
- control signal generating circuit 142 In an MRAD test mode, the control signal generating circuit 142 generates at least one activated control signal PMRAD, and then the row decoder 124 decodes bits of a row address designated by the activated control signal PMRAD at a predetermined level. In this case, it is assumed that the predetermined level is a logic high level.
- the row decoder 124 includes a plurality of predecoders for predecoding row address signals.
- the row address signals are divided in units of n bits.
- control signals PMRADij selectively control each predecoder.
- each predecoder receives for predecoding two bits of a row address signal. It would be apparent to one ordinarily skilled in the art that a different number of bits of a row address signal can be predecoded, and that a row address signal can be decoded without the predecoding process.
- the MRAD test circuit 14 is a test circuit for semiconductor memory device including a plurality of banks and sub-arrays.
- a row address signal is classified into a bank address BRA 0 -BRAj for selecting the banks, a sub-array address SRA 0 -SRAj, or a word line address RA 0 -RAj for selecting word lines within the sub-arrays.
- the row decoder 124 is mainly comprised of a bank decoder 27 , a sub-array decoder 26 , a word line decoder 25 , a sub-array select circuit 28 and a word line driving circuit 29 .
- the bank decoder 27 predecodes the bank address BRA 0 -BRAj
- the sub-array decoder 26 predecodes the sub-array address SRA 0 -SRAj.
- the word line decoder 25 predecodes the word line address RA 0 -RAj.
- the sub-array select circuit 28 receives output signals of the bank decoder 27 and the sub-array decoder 26 to generate a final sub-array select signal SSUB.
- the word line driving circuit 29 activates a word line finally selected by an output signal of the word line predecoder 25 and the sub-array select signal SSUB.
- the control signal generating circuit 142 generates a plurality of control signals PMRAD 01 , PMRAD 23 , . . . , PMRADij by dividing a row address signal in units of two bits.
- each one of the banks and sub-arrays is selected, and that two or more word lines within the sub-array are selected at the same time. Therefore, the generated control signals PMRAD 01 , PMRAD 23 , . . . , PMRADij controls the respective predecoders DRA 01 -DRAij within the word line decoder 25 .
- control signal is inputted to the sub-array decoder 26 and the bank decoder 27 .
- a control signal for simultaneously selecting a plurality of banks and sub-arrays may be further generated. This means that a plurality of word lines are selected at the same time within a plurality of banks or a plurality of sub-arrays.
- the word line address is comprised of bits ranging from RA 0 bit to RAj bit.
- the control signals generated by control signal generating circuit 142 include a signal PMRAD 01 for controlling predecoder DRA 01 which decodes RA 0 and RA 1 bits of the word line address.
- Control signals PMRADij are generated for controlling RAi and RAj bits of the word line address.
- control signal PMRAD 23 controls predecoder DRA 23 .
- the control signal generating circuit 142 activates a control signal PMRADij and inputs the control signal PMRADij to a predecoder DRAij within the row decoder 124 .
- the corresponding predecoder DRAij renders the received input bits RAi and RAj as ‘don't care,’ with circuitry under control of PMRADij to output bits corresponding to RAi and RAj at a logic high level.
- the predecoding operation will be described in detail with reference to FIG. 3.
- the semiconductor memory device can enter into an MRAD test mode by inputting an MRAD test signal through address pins. This means that the MRAD test signal contains information denoting whether or not it is an MRAD test mode.
- FIG. 3 is a detailed diagram showing a predecoder in the test circuit of FIG. 2.
- a predecoder DRAij in the test circuit of FIG. 2 includes a predecoding unit 34 , a gating signal unit 32 , 2 n (the nth power of 2) of switches TG 1 -TG 4 , and 2 n (the nth power of 2) latching units 36 a - 36 d .
- n is the number of bits of a row address signal received by the predecoder DRAij.
- the predecoder receives two row address bits, there should be four (2 2 ) switches TG 1 -TG 4 and four (2 2 ) latching units 36 a - 36 d .
- the predecoding unit 34 receives two bits RAi and RAj of row address signal to activate and output, depending on the value of two bits, only one of four output signals P 01 -P 04 to the corresponding one of the four switches TG 1 -TG 4 .
- the gating signal unit 32 generates a gating signal SG in response to a row address latch signal PDRAE and a control signal PMRADij.
- the switches TG 1 -TG 4 are turned on or turned off according to the gating signal SG. In this embodiment, the switches TG 1 -TG 4 acts as a transmission gate which are turned on when the gating signal SG is at logic high and turned off at logic low.
- the latching units 36 a - 36 d receives the respective output signals P 01 -P 04 and latches them. Conversely, if the switches TG 1 -TG 4 are turned off, the latching units 36 a - 36 d latch a predetermined level of signal (here, high level signal).
- the latching units 36 a - 36 d have respective MOS transistors NM 1 -NM 4 which are formed between the respective latching units and a ground voltage (GND).
- the respective MOS transistors NM 1 -NM 4 are gated by control signal PMRADij.
- control signal PMRADij is in an activated state, i.e., at logic high, the switches TG 1 -TG 4 are turned off, and the respective MOS transistors NM 1 -NM 4 are turned on, so output signals DRAij[ 0 ]-DRAij[ 3 ] of the respective four latching units 36 a - 36 d are all at the predetermined logic high level. Accordingly, four word lines are selected at the same time because all the four latching units 36 a - 36 d are simultaneously at logic high level.
- control signal PMRADij is in a deactivated state, i.e., at logic low, the switches TG 1 -TG 4 are turned on and only one of the output signals DRAij[ 0 ]-DRAij[ 3 ] of the respective latching units 36 a - 36 d becomes high depending on the received value of two bits of a row address signal RAi and RAj.
- the embodiment describes only one control signal PMRADij being activated, a plurality of control signals can be activated to select more word lines at the same time. The number of word lines which are simultaneously activated can be adjusted by controlling an activated control signal.
- FIG. 4 is a flowchart showing a test method according to an embodiment of the present invention.
- the test method according to the present invention mainly includes three steps. First, an MRAD test signal is inputted through address pins so that a semiconductor memory device may go into an MRAD test mode (step 43 ). Then, according to the input MRAD test signal, at least one control signal is activated (step 45 ). Finally, according to the activated control signal and the input address signal, at least two word lines are selected at the same time (step 47 ).
- test circuit and test method according to the present invention shortens the test time of a semiconductor memory device without increasing current consumption.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor memory device, and more particularly, to a test circuit that shortens the time required to test semiconductor memory devices and a semiconductor memory device having the same.
- 2. Description of the Related Art
- Since the beginning of their development, semiconductor memory devices have progressed significantly, with continual increases in performance and integration. As memory sizes increases, the time required to test the memories also increases. The increased test time delays the production cycle. Thus, efforts to shorten test times are ever on-going. Circuits have been designed and added to semiconductor devices to reduce test time. Meanwhile, in order to improve the input and output speed of semiconductor memory devices, semiconductor memory devices include a plurality of banks. A plurality of bits can be simultaneously inputted to/outputted from semiconductor memory devices including a plurality of banks.
- Generally, when one-time row active and data input and output commands are applied in a normal operation mode of semiconductor memory devices, only one word line is selected in one bank corresponding to an address input from the outside. Information stored in a memory cell outputted onto a selected word line is amplified by a bit line sense amplifier and then outputted to the outside. For all word lines to be selected by a row active command, a one-time row active command must be applied at times which are equivalent to the number of banks multiplied by the number of word lines within a bank. All of the components involved in inputting/outputting data to/from a semiconductor memory device must be tested in order to ensure that the device functions properly. One can readily appreciates that as memory size becomes more dense, the time required for testing the increased memory locations and support circuits must also increase.
- One way to shorten test time in a semiconductor memory device is the use of a refresh cycle reduction (RCR) mode. In the RCR mode, a plurality of banks are selected by a row active command. Therefore, a plurality of word lines are simultaneously activated by a one-time row active command, which allows a reduction in the test time. However, in this mode, since word lines within a plurality of banks are selected at the same time, more bit line sense amplifiers are operated at the same time, and more current is consumed accordingly. Since there is a limit to the amount of consumable current in a semiconductor memory device, the number of word lines which can be activated at the same time in a RCR mode is limited. Accordingly, a need exists for a device and method for conducting tests of a semiconductor memory device in a speeding fashion while minimizing current consumption.
- The present invention provides a semiconductor memory device that shortens testing time while minimizing the increase of current consumption.
- The present invention further provides a test control circuit for controlling a predetermined test mode operation in such a way as to shorten the testing time in a semiconductor memory device.
- The present invention further provides a test method of shortening the test time in a semiconductor memory device.
- In one aspect of the present invention, there is provided a semiconductor memory device including at least one memory array including a plurality of word lines sharing a bit line sense amplifier. In the semiconductor device, at least two word lines among the plurality of word lines including the bit line sense amplifier are activated at the same time in a test mode.
- In another aspect of the present invention, there is provided a test circuit in a semiconductor memory device including at least one memory array which has a plurality of word lines sharing a bit line sense amplifier. The test circuit according to a preferred embodiment of the invention includes a control signal generating circuit which generates a plurality of control signals at least one of which is activated in a test mode, and a row decoder which activates at least two word lines in response to the activated control signal and a predetermined row address signal comprised of a plurality of bits.
- In yet anther aspect of the present invention, there is provided a test method in a semiconductor memory device including at least one memory array which has a plurality of word lines sharing a bit line sense amplifier. The test method according to a preferred embodiment of the invention includes the steps of: a) inputting a predetermined MRAD test signal through address pins; b) activating at least one control signal according to the predetermined MRAD test signal; and c) selecting at least two word lines at the same time according to the control signal and a predetermined row address signal.
- The above test circuit and test method can shorten the testing time of a semiconductor memory device to be shortened without increasing current consumption.
- The above objectives and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
- FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention;
- FIG. 2 is a block diagram showing a test circuit according to an embodiment of the present invention;
- FIG. 3 is a detailed diagram showing a predecoder in the test circuit of FIG. 2; and
- FIG. 4 is a flowchart showing a test method according to an embodiment of the present invention.
- For convenience sake, signals and elements which perform the same function in different drawings are denoted by the same reference characters and the same reference numerals.
- Referring to FIG. 1, which is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, the semiconductor memory device includes at least one
memory array 122 and bitline sense amplifier 128. Thememory array 122 is a portion of asemiconductor memory 12 in which memory cells for storing information are in thememory array 122 arranged in columns and rows. A word line is a line connected in a row direction within the memory array, and the word line selects memory cells where data is inputted and outputted. A bit line is a line connected in a column direction within thememory array 122 to which data is inputted and outputted. Onememory array 122 includes a plurality of word lines which shares one bitline sense amplifier 128. Memory cells within the memory array are selected in units of a word line. Data of the memory cells selected by a word line is outputted to the bit line to be sensed and amplified in the bitline sense amplifier 128. Among the thus-sensed and amplified data, only the data of a column selected by acolumn decoder 126 is finally outputted from the semiconductor memory device through an input/output circuit 18. In this case, thememory array 122 can include one or more sub-arrays, and a bit line sense amplifier can be provided for each sub-array. - The semiconductor memory device according to a preferred embodiment of the present invention includes a multi-row active disturb (MRAD)
test circuit 14. The MRADtest circuit 14 includes a controlsignal generating circuit 142 and arow decoder 124. The MRAD test circuit according to the present invention will be described in detail with reference to FIG. 2 later. - Turning to FIG. 1, the control
signal generating circuit 142 generates a plurality of control signals, which are denoted by PMRAD. At least one control signal PMRAD is activated in an MRAD test mode. In other modes, a control signal PMRAD is not activated. The MRAD test mode is a test mode in which a semiconductor memory device is tested in such a way that at least two of a plurality of word lines within thememory array 122 sharing the bitline sense amplifier 128 are activated at the same time to shorten the test time. Arow decoder 124 selects and activates one or more word lines in response to a control signal PMRAD and a row address signal. In the MRAD test mode, therow decoder 124 simultaneously activates at least two of a plurality of word lines sharing the bit line sense amplifier, in response to an activated control signal PMRAD and a row address signal. In this case, thememory array 122, bitline sense amplifier 128,row decoder 124, andcolumn decoder 126 may form a bank. Furthermore, the semiconductor memory device according to a preferred embodiment of the present invention may include a plurality of banks having such a structure. - FIG. 2 is a block diagram showing a test circuit according to an embodiment of the present invention. The test circuit according to the present invention is called an MRAD test circuit. Referring to FIG. 2, an
MRAD test circuit 14 according to a preferred embodiment of the present invention includes a controlsignal generating circuit 142 and arow decoder 124. Furthermore, theMRAD test circuit 14 may include a row address latchsignal generating circuit 24 which generates a row address latch signal denoted by PDRAE. The row address latch signal PDRAE causes therow decoder 124 to latch a row address signal. The row address signal includes a plurality of bits and they are inputted through address pins. - In a mode other than an MRAD test mode, the control
signal generating circuit 142 does not activate control signal PMRAD, and then therow decoder 124 receives for decoding a row address signal. In an MRAD test mode, the controlsignal generating circuit 142 generates at least one activated control signal PMRAD, and then therow decoder 124 decodes bits of a row address designated by the activated control signal PMRAD at a predetermined level. In this case, it is assumed that the predetermined level is a logic high level. - Preferably, the
row decoder 124 includes a plurality of predecoders for predecoding row address signals. The row address signals are divided in units of n bits. In describing the embodiment, for convenience sake, it is assumed that row address signals in units of two bits are provided to the predecoders. Thus, control signals PMRADij selectively control each predecoder. In other words, each predecoder receives for predecoding two bits of a row address signal. It would be apparent to one ordinarily skilled in the art that a different number of bits of a row address signal can be predecoded, and that a row address signal can be decoded without the predecoding process. - The
MRAD test circuit 14 is a test circuit for semiconductor memory device including a plurality of banks and sub-arrays. Thus, a row address signal is classified into a bank address BRA0-BRAj for selecting the banks, a sub-array address SRA0-SRAj, or a word line address RA0-RAj for selecting word lines within the sub-arrays. Therow decoder 124 is mainly comprised of abank decoder 27, asub-array decoder 26, aword line decoder 25, a sub-arrayselect circuit 28 and a wordline driving circuit 29. Thebank decoder 27 predecodes the bank address BRA0-BRAj, and thesub-array decoder 26 predecodes the sub-array address SRA0-SRAj. Theword line decoder 25 predecodes the word line address RA0-RAj. The sub-arrayselect circuit 28 receives output signals of thebank decoder 27 and thesub-array decoder 26 to generate a final sub-array select signal SSUB. The wordline driving circuit 29 activates a word line finally selected by an output signal of theword line predecoder 25 and the sub-array select signal SSUB. - The control
signal generating circuit 142 generates a plurality of control signals PMRAD01, PMRAD23, . . . , PMRADij by dividing a row address signal in units of two bits. In the illustrative embodiment according to the present invention, it is preferred that each one of the banks and sub-arrays is selected, and that two or more word lines within the sub-array are selected at the same time. Therefore, the generated control signals PMRAD01, PMRAD23, . . . , PMRADij controls the respective predecoders DRA01-DRAij within theword line decoder 25. Furthermore, it is assumed that no control signal is inputted to thesub-array decoder 26 and thebank decoder 27. However, a control signal for simultaneously selecting a plurality of banks and sub-arrays may be further generated. This means that a plurality of word lines are selected at the same time within a plurality of banks or a plurality of sub-arrays. - The word line address is comprised of bits ranging from RA0 bit to RAj bit. The control signals generated by control
signal generating circuit 142 include a signal PMRAD01 for controlling predecoder DRA01 which decodes RA0 and RA1 bits of the word line address. Control signals PMRADij are generated for controlling RAi and RAj bits of the word line address. For example, control signal PMRAD23 controls predecoder DRA23. - If the semiconductor memory device goes into an MRAD test mode, the control
signal generating circuit 142 activates a control signal PMRADij and inputs the control signal PMRADij to a predecoder DRAij within therow decoder 124. When the control signal PMRADij is in an activated state, the corresponding predecoder DRAij renders the received input bits RAi and RAj as ‘don't care,’ with circuitry under control of PMRADij to output bits corresponding to RAi and RAj at a logic high level. The predecoding operation will be described in detail with reference to FIG. 3. - The semiconductor memory device can enter into an MRAD test mode by inputting an MRAD test signal through address pins. This means that the MRAD test signal contains information denoting whether or not it is an MRAD test mode.
- Referring to FIG. 3, which is a detailed diagram showing a predecoder in the test circuit of FIG. 2. A predecoder DRAij in the test circuit of FIG. 2 includes a
predecoding unit 34, a gating signal unit 32, 2 n (the nth power of 2) of switches TG1-TG4, and 2 n (the nth power of 2) latching units 36 a-36 d. In this case, n is the number of bits of a row address signal received by the predecoder DRAij. When the predecoder receives two row address bits, there should be four (22) switches TG1-TG4 and four (22) latching units 36 a-36 d. Thepredecoding unit 34 receives two bits RAi and RAj of row address signal to activate and output, depending on the value of two bits, only one of four output signals P01-P04 to the corresponding one of the four switches TG1-TG4. The gating signal unit 32 generates a gating signal SG in response to a row address latch signal PDRAE and a control signal PMRADij. The switches TG1-TG4 are turned on or turned off according to the gating signal SG. In this embodiment, the switches TG1-TG4 acts as a transmission gate which are turned on when the gating signal SG is at logic high and turned off at logic low. - If the switches TG1-TG4 are turned on, the latching units 36 a-36 d receives the respective output signals P01-P04 and latches them. Conversely, if the switches TG1-TG4 are turned off, the latching units 36 a-36 d latch a predetermined level of signal (here, high level signal). The latching units 36 a-36 d have respective MOS transistors NM1-NM4 which are formed between the respective latching units and a ground voltage (GND). The respective MOS transistors NM1-NM4 are gated by control signal PMRADij. If the control signal PMRADij is in an activated state, i.e., at logic high, the switches TG1-TG4 are turned off, and the respective MOS transistors NM1-NM4 are turned on, so output signals DRAij[0]-DRAij[3] of the respective four latching units 36 a-36 d are all at the predetermined logic high level. Accordingly, four word lines are selected at the same time because all the four latching units 36 a-36 d are simultaneously at logic high level.
- If the control signal PMRADij is in a deactivated state, i.e., at logic low, the switches TG1-TG4 are turned on and only one of the output signals DRAij[0]-DRAij[3] of the respective latching units 36 a-36 d becomes high depending on the received value of two bits of a row address signal RAi and RAj. Although the embodiment describes only one control signal PMRADij being activated, a plurality of control signals can be activated to select more word lines at the same time. The number of word lines which are simultaneously activated can be adjusted by controlling an activated control signal.
- FIG. 4 is a flowchart showing a test method according to an embodiment of the present invention. Referring to FIG. 4, the test method according to the present invention mainly includes three steps. First, an MRAD test signal is inputted through address pins so that a semiconductor memory device may go into an MRAD test mode (step43). Then, according to the input MRAD test signal, at least one control signal is activated (step 45). Finally, according to the activated control signal and the input address signal, at least two word lines are selected at the same time (step 47).
- Advantageously, the test circuit and test method according to the present invention shortens the test time of a semiconductor memory device without increasing current consumption.
- While this invention has been particularly shown and described with reference to a preferred embodiment thereof, it should be understood that various alternatives and modifications can be devised by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2000-6551 | 2000-02-11 | ||
KR1020000006551A KR100355230B1 (en) | 2000-02-11 | 2000-02-11 | MRAD Test Circuit, Semiconductor Memory Device having the same and MRAD Test Method |
KR00-6551 | 2000-02-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010014043A1 true US20010014043A1 (en) | 2001-08-16 |
US6301170B2 US6301170B2 (en) | 2001-10-09 |
Family
ID=19645793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/766,733 Expired - Lifetime US6301170B2 (en) | 2000-02-11 | 2001-01-22 | MRAD test circuit, semiconductor memory device having the same and MRAD test method |
Country Status (3)
Country | Link |
---|---|
US (1) | US6301170B2 (en) |
JP (1) | JP2001229695A (en) |
KR (1) | KR100355230B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060034139A1 (en) * | 2004-08-11 | 2006-02-16 | Hynix Semiconductor Inc. | Semiconductor memory device |
CN103035300A (en) * | 2012-12-20 | 2013-04-10 | 北京航天测控技术有限公司 | Modeling method and boundary scan test method for DDR2 memory |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100604890B1 (en) * | 2004-07-22 | 2006-07-28 | 삼성전자주식회사 | Semiconductor device for initialization by the unit SRAMs |
KR100920845B1 (en) | 2008-06-04 | 2009-10-08 | 주식회사 하이닉스반도체 | Row address decoder and semiconductor memory apparatus with the same |
KR102468710B1 (en) | 2018-03-26 | 2022-11-21 | 에스케이하이닉스 주식회사 | Memory system including memory device and memory controller, and operation method thereof |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07312100A (en) * | 1994-05-17 | 1995-11-28 | Seiko Instr Inc | Semiconductor memory integrated circuit |
JPH0887887A (en) * | 1994-09-17 | 1996-04-02 | Toshiba Corp | Semiconductor memory |
-
2000
- 2000-02-11 KR KR1020000006551A patent/KR100355230B1/en not_active IP Right Cessation
-
2001
- 2001-01-22 US US09/766,733 patent/US6301170B2/en not_active Expired - Lifetime
- 2001-01-30 JP JP2001021610A patent/JP2001229695A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060034139A1 (en) * | 2004-08-11 | 2006-02-16 | Hynix Semiconductor Inc. | Semiconductor memory device |
US7154808B2 (en) | 2004-08-11 | 2006-12-26 | Hynix Semiconductor Inc. | Semiconductor memory device for simultaneously testing blocks of cells |
CN103035300A (en) * | 2012-12-20 | 2013-04-10 | 北京航天测控技术有限公司 | Modeling method and boundary scan test method for DDR2 memory |
Also Published As
Publication number | Publication date |
---|---|
KR20010083353A (en) | 2001-09-01 |
KR100355230B1 (en) | 2002-10-11 |
JP2001229695A (en) | 2001-08-24 |
US6301170B2 (en) | 2001-10-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7372768B2 (en) | Memory with address management | |
US6272056B1 (en) | Semiconductor memory device capable of implementing redundancy-based repair efficiently in relation to layout and operating speed and semiconductor integrated circuit device having such semiconductor memory device | |
KR100937600B1 (en) | Semiconductor memory device with high-speed operation and Memory system comprising the same | |
KR920009059B1 (en) | Method for testing parallel semiconductor memory device | |
US5544101A (en) | Memory device having a latching multiplexer and a multiplexer block therefor | |
JPH09120698A (en) | Test method for semiconductor memory device | |
US6727532B2 (en) | Semiconductor integrated circuit device | |
EP2082399B1 (en) | Memory bus output driver of a multi-bank memory device and method therefor | |
US7187615B2 (en) | Methods of selectively activating word line segments enabled by row addresses and semiconductor memory devices having partial activation commands of word line | |
US6122207A (en) | Semiconductor memory device and method for relieving defective memory cells | |
US7038957B2 (en) | Semiconductor memory device for testifying over-driving quantity depending on position | |
US6301170B2 (en) | MRAD test circuit, semiconductor memory device having the same and MRAD test method | |
JP3279787B2 (en) | Semiconductor storage device | |
US6243291B1 (en) | Two-stage pipeline sensing for page mode flash memory | |
US6819623B2 (en) | Integrated circuit memory devices having efficient column select signal generation during normal and refresh modes of operation and methods of operating same | |
JP2000251471A (en) | Activating method for hierarchical row for banking control in multi-bank dram | |
US6331963B1 (en) | Semiconductor memory device and layout method thereof | |
US8400846B2 (en) | Semiconductor integrated circuit with multi test | |
KR100422422B1 (en) | Semiconductor device | |
US20020001895A1 (en) | Semiconductor memory device with reduced current consumption | |
US6473347B2 (en) | Semiconductor device having memory with effective precharging scheme | |
US5956276A (en) | Semiconductor memory having predecoder control of spare column select lines | |
KR960008280B1 (en) | Row decoder circuit consuming low power | |
US20040223398A1 (en) | Method and device for a scalable memory building block | |
US7743291B2 (en) | Semiconductor memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JANG, TAE-SEONG;REEL/FRAME:011494/0266 Effective date: 20010110 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |