CN208834750U - Word line control circuit device and semiconductor memory - Google Patents
Word line control circuit device and semiconductor memory Download PDFInfo
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- CN208834750U CN208834750U CN201821876360.8U CN201821876360U CN208834750U CN 208834750 U CN208834750 U CN 208834750U CN 201821876360 U CN201821876360 U CN 201821876360U CN 208834750 U CN208834750 U CN 208834750U
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Abstract
The utility model provides a kind of Word line control circuit device, including test pattern input module, row address input module and logic decoding processor, the output end of test pattern input module output end and row address input module is connected to the signal input part of logic decoding processor, and the signal output end of logic decoding processor and a plurality of wordline of storage array are correspondingly connected with；Test pattern input module is for receiving test mode signal, row address input module is for receiving multiple row address signals, logic decoding processor is used to carry out logic to multiple row address signals and test mode signal and decoding is handled, it generates row address and controls signal, it includes at least two effective open signals that row address, which controls signal, and at least two wordline for controlling non-adjacent open simultaneously.It eliminates since contact zone disconnects or impedance is too greatly to the influence of test, improves the accuracy of test.
Description
Technical field
The utility model relates to semiconductor integrated circuit technology fields, and in particular to a kind of Word line control circuit device and
Semiconductor memory.
Background technique
The finished product of memory chip usually has some defects: storage capacitance is smaller, and the capacity of each storage capacitance may
The problems such as being contact zone disconnection or the too big impedance between the half or storage capacitance of the capacity of standard storage capacitor.This
Field technical staff generally goes through test to find out these defects.For example, to test whether storage capacitance becomes smaller, common test
Method is to be opened simultaneously by opening adjacent two wordline to control two storage capacitances, and obtained test result is deposited equal to standard
The test result that storage is held illustrates the defect that the two storage capacitances in memory chip have capacity too small.Pass through opening
The reason of adjacent two wordline are tested is, even if wherein a wordline breaks down, can also continue to complete test.At this point,
The test result arrived is less than the test result of standard storage capacitor, illustrates that this storage capacitance in memory chip has capacity
Too small defect.
However, this test mode above-mentioned defect test small to storage capacitance is inaccurate.It is deposited due to two neighboring
Storage holds a shared contact zone and either opens simultaneously two wordline, or only beat once contact zone also breaks down
A wherein wordline is opened, can not determine that storage chip is the small defect of storage capacitance.
Disclosed above- mentioned information are only used for reinforcing the understanding to the background of the utility model in the background technology, therefore it can
It can include the information for not being formed as the prior art that those of ordinary skill in the art are known.
Utility model content
The utility model provides a kind of Word line control circuit device and semiconductor memory, to overcome or alleviated by background skill
One or more problem present in art at least provides a kind of beneficial selection.
As the one aspect of the utility model, the utility model provides a kind of Word line control circuit device, including surveys
Die trial formula input module, row address input module and logic decoding processor, the signal input of the logic decoding processor
End is connected to the test pattern input module, the signal output end of the logic decoding processor and a plurality of word of storage array
Line is correspondingly connected with；
For the test pattern input module for receiving test mode signal, the row address input module is more for receiving
A row address signal；The logic decoding processor is used to carry out the multiple row address signal and the test mode signal
Logic and decoding processing generate row address and control signal, and the row address control signal includes at least two effective open signals,
At least two wordline for controlling non-adjacent open simultaneously.
In one embodiment, the test pattern input module include test pattern input terminal, the first phase inverter and
Test pattern output end, for receiving the test mode signal, first phase inverter is used for the test pattern input terminal
The test mode signal is subjected to reverse phase operation, reverse phase is generated and tests signal, the test pattern output end is for exporting institute
State reverse phase test signal.
In one embodiment, the row address input module includes a plurality of row address signal line and with each row
Multiple second phase inverters that location signal wire is separately connected, each row address signal line are respectively used to receive the row address input
Corresponding row address signal in signal, second phase inverter are used to carry out inverted logic operation to each row address signal,
Obtain multiple reverse phase row address signals.
In one embodiment, the logic decoding processor includes first and door, second and door and code translator；
Described first row address signal for being used to have chosen with door and reverse phase test signal progress and logical operation,
Anti-phase output row address is generated, described first and door include first input end, the second input terminal and the first output end, and described the
One input terminal is connected to the corresponding row address signal line of row address signal chosen, and second input terminal is connected to institute
Test pattern output end is stated, for receiving the reverse phase test signal；
Described second reverse phase row address signal corresponding with the row address signal that door is used to have chosen and the reverse phase are surveyed
Trial signal carries out and logical operation, generates positive and exports row address, described second and door include third input terminal, the 4th input terminal
And second output terminal, the third input terminal are connected to the defeated of corresponding second phase inverter of row address signal chosen
Outlet, the 4th input terminal are connected to the test pattern output end；
The code translator is used for the anti-phase output row address, positive output row address, the row ground that do not choose
Location signal and the corresponding reverse phase row address signal carry out decoding processing, obtain row address control signal, the row address
Controlling signal includes at least two effective open signals that non-adjacent at least two wordline can be made to open simultaneously.
In one embodiment, the code translator includes the first decoder, and first decoder includes one group of positive
Input terminal and one group of inverting input terminal, first output end and the second output terminal are respectively connected to corresponding anti-phase input
End and corresponding normal phase input end.
In one embodiment, the code translator further includes the second decoder and third decoder, second decoding
The input terminal of device include for receive the one of the row address signal that do not choose group of normal phase input end and for receive do not choose it is anti-
One group of inverting input terminal of phase row address signal；
The input terminal of the third decoder includes for receiving the one of the row address signal that do not choose group of normal phase input end
With one group of inverting input terminal for receiving the reverse phase row address signal that do not choose.
In one embodiment, the code translator further includes the 4th decoder, the input terminal of the 4th decoder with
The output end of the output end of first decoder, the output end of second decoder and the third decoder connects,
The output end of 4th decoder is connected to each wordline.
The utility model additionally provides a kind of semiconductor memory, including Word line control circuit described in any of the above embodiments dress
It sets.
The utility model by adopting the above technical scheme, has the advantages that in test mode, by inputting to row address
The logical operation and decoding of signal and test mode signal are handled, and obtained row address control signal can open simultaneously non-adjacent
Two wordline.Due to not sharing the same contact zone between two non-adjacent wordline, so, it eliminates since contact zone is disconnected
It opens or impedance is too greatly to the influence of test, improve the accuracy of test.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the utility model is into one
Aspect, embodiment and the feature of step, which will be, to be readily apparent that.
Detailed description of the invention
In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to originally practical
Novel disclosed some embodiments, and should not be taken as the limitation to the scope of the utility model.
Fig. 1 is painted a kind of wordline control method flow diagram provided by the embodiment of the utility model.
Fig. 2 is painted word line structure schematic diagram provided by the embodiment of the utility model.
Fig. 3 is painted word line structure schematic diagram provided by the embodiment of the utility model.
Fig. 4 is painted another wordline control method flow diagram provided by the embodiment of the utility model.
Fig. 5 is painted a kind of Word line control circuit apparatus structure schematic diagram provided by the embodiment of the utility model.
Fig. 6 is painted another Word line control circuit apparatus structure schematic diagram provided by the embodiment of the utility model.
Detailed description of the invention:
10- test pattern input module；11- test pattern input terminal；12- test pattern output end；
20- row address input module；The output end of 22- row address input module；
30- logic decoding processor；40- wordline；
The signal input part of 32- logic decoding processor；The signal output end of 33- logic decoding processor；
201- row address signal line；The first phase inverter of 100-；The second phase inverter of 200-；
310- first and door；320- second and door；330- code translator；
311- first input end；The second input terminal of 312-；The first output end of 313-；
321- third input terminal；The 4th input terminal of 322-；323- second output terminal；
The first decoder of 331-；The second decoder of 332-；333- third decoder；
The 4th decoder of 334-；
The output end of the first decoder of 335-；
The output end of the second decoder of 336-；
The output end of 337- third decoder.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present utility model, it can be modified by various different modes described real
Apply example.Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it should be understood that term " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside",
The orientation or positional relationship of the instructions such as " clockwise ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " is based on the figure
Orientation or positional relationship is merely for convenience of describing the present invention and simplifying the description, rather than the dress of indication or suggestion meaning
It sets or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as to the utility model
Limitation.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.The meaning of " plurality " is two or two in the description of the present invention,
More than, unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " Gu
It is fixed " etc. terms shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be
Mechanical connection, is also possible to be electrically connected, can also be communication；It can be directly connected, the indirect phase of intermediary can also be passed through
Even, the connection inside two elements or the interaction relationship of two elements be can be.For those of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it
"lower" may include that the first and second features directly contact, and also may include that the first and second features are not direct contacts but lead to
Cross the other characterisation contact between them.Moreover, fisrt feature second feature " on ", " side " and " above " include first
Feature is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.Fisrt feature
It under the second feature " below ", " below " and " below " include fisrt feature right above second feature and oblique upper, or only table
Show that first feature horizontal height is less than second feature.
Following disclosure provides many different embodiments or example is used to realize the different structure of the utility model.
In order to simplify the disclosure of the utility model, hereinafter the component of specific examples and setting are described.Certainly, they are only
Example, and purpose does not lie in limitation the utility model.In addition, the utility model can in different examples repeat reference numerals
And/or reference letter, this repetition are for purposes of simplicity and clarity, itself not indicate discussed various embodiments
And/or the relationship between setting.In addition, the example of various specific techniques and material that the utility model provides, but this
Field those of ordinary skill can be appreciated that the application of other techniques and/or the use of other materials.
Embodiment one
In a kind of specific embodiment, a kind of wordline control method is provided, as shown in Figure 1, comprising:
Step S10: row address input signal is obtained.
Step S20: test mode signal is obtained.
Step S30: logic is carried out to row address input signal and test mode signal and decoding is handled, generates row address control
Signal processed, it includes at least two effective open signals that row address, which controls signal,.
Step S40: non-adjacent at least two wordline are controlled according at least two effective open signals and are opened simultaneously.
In test mode, it is handled by logical operation to row address input signal and test mode signal and decoding,
Obtained row address control signal can open simultaneously non-adjacent at least two wordline.As shown in Fig. 2, with access transistor source
Two storage capacitances 400 of pole electrical connection share an active area 300, and two adjacent wordline have shared a contact zone 500,
Contact zone 500 is as drain electrode.As shown in figure 3, due between two non-adjacent wordline as WL1 and WL3 will not share it is same
Contact zone, so, it eliminates since contact zone disconnects or impedance is too greatly to the influence of test, improves the accuracy of test.
In one embodiment, as shown in figure 4, row address input signal includes multiple row address signals, to row address
Input signal and test mode signal carry out logic and decoding processing, generate the step of row address controls signal and include:
Step S101: carrying out reverse phase operation for test mode signal, generates reverse phase and tests signal.
Step S102: optional one from multiple row address signals, reverse phase test signal is believed with the row address chosen
Number carry out NAND Logic operation, generate anti-phase output row address.
Step S103: inverted logic operation is carried out to all row address signals, generates corresponding multiple reverse phase row addresses
Signal.
Step S104: the corresponding reverse phase row address signal of the row address signal chosen and reverse phase test signal carry out with it is non-
Logical operation generates positive and exports row address.
Step S105: it does not choose anti-phase output row address, positive output row address, the row address signal that do not choose and
Reverse phase row address signal carry out decoding processing, obtain row address control signal.
In a kind of example, as shown in fig. 6, to enter test pattern, test mode signal can be set to logic state
1, test mode signal carries out reverse phase operation, generates the logic state of reverse phase test signal.Row address input signal RA<8:0>packet
Nine row address signals are included, are indicated respectively with RA0~RA8, inverted logic operation is carried out to all row address signals, is generated
Corresponding reverse phase row address signal is respectively used to RAN0~RAN8 to indicate.Optional one from RA0~RA8, such as RA1, it will
Reverse phase test signal carries out NAND Logic operation with the row address signal chosen, and generates anti-phase output row address RANint1.?
The corresponding reverse phase row address signal RAN1 of the row address signal RA1 of selection and reverse phase test signal carry out NAND Logic operation, raw
Row address RAint1 is exported at positive.RANint1, RAint1 and RA0, RA2~RA8, RAN0, RAN2~RAN8 are input to
In decoder, the signal for the wordline number same number that the row address control signal of generation includes and needs control, such as 512
Wordline.Wherein, there are at least two effective open signals in row address control signal, the non-phase in 512 wordline can be controlled
Adjacent at least two any two wordline open simultaneously.
In one embodiment, as shown in figure 4, the row that anti-phase output row address, positive are exported row address, do not chosen
Address signal and the reverse phase row address signal that do not choose carry out decoding processing, obtain the step of row address controls signal and include:
Step S201: it does not choose anti-phase output row address, positive output row address, the row address signal that do not choose and
Reverse phase row address signal carry out level-one decoding processing, obtain the first row address control signal, the first row address control signal packet
At least two effective open signals are included, effective open signal is opened simultaneously for controlling non-adjacent at least two wordline；
Step S202: carrying out second level decoding processing for the first row address control signal, obtains the second row address control signal,
Second row address control signal is opened simultaneously for controlling non-adjacent at least two wordline.
In a kind of example, as shown in fig. 6, three three or eight decoders can be selected when level-one decoding processing, one of them
Three or eight decoders input RANint1, RAint1, generate first control signal, include that control is non-adjacent in first control signal
Two effective open signals that two wordline open simultaneously.Remaining two three or eight decoders export respectively input RA0, RA2~
RA8, RAN0, RAN2~RAN8, export second control signal and third controls signal.First control signal, second control signal
The first row address control signal is formed with third control signal.
Certainly, mode when level-one decoding processing includes but is not limited to above-mentioned example, can also select other way, as long as
This exemplary purpose is realized, in the protection scope of present embodiment.
Embodiment two
In another embodiment specific implementation mode, as shown in figure 5, providing a kind of Word line control circuit device, including test
Mode input module 10, row address input module 20 and logic decoding processor 30.
The output end 12 of test pattern input module and the output end 22 of row address input module are connected at logic decoding
Manage the signal input part 32 of device, the corresponding company of the signal output end 33 of logic decoding processor 30 and a plurality of wordline 40 of storage array
It connects.
Test pattern input module 10 is for receiving test mode signal, and row address input module 20 is for receiving multiple rows
Address signal, logic decoding processor 30 are used to carry out at logic and decoding multiple row address signals and test mode signal
Reason generates row address and controls signal, and it includes at least two effective open signals that row address, which controls signal, for according at least two
Effective open signal controls non-adjacent at least two wordline 40 and opens simultaneously.
In one embodiment, as shown in fig. 6, test pattern input module 10 includes test pattern input terminal 11, the
One phase inverter 100 and test pattern output end 12, test pattern input terminal 11 is for receiving test mode signal, the first reverse phase
Device 100 is used to test mode signal carrying out reverse phase operation, generates reverse phase and tests signal, test pattern output end 12 is for exporting
Reverse phase tests signal.
In one embodiment, row address input module 20 includes a plurality of row address signal line 201 and with each row
Multiple second phase inverters 200 that location signal wire is separately connected, each row address signal line 201 are respectively used to receive row address input letter
Corresponding row address signal in number, the second phase inverter 200 are used to carry out inverted logic operation to each row address signal, obtain reverse phase
Row address signal.
As shown in fig. 6, row address input module 20 includes nine row address signal lines 201 in a kind of example, use respectively
In inputting corresponding row address signal RA0~RA8, nine row address signal lines 201 connect one to one nine the second phase inverters
200, the output end 202 of nine corresponding second phase inverters exports reverse phase row address signal RAN0~RAN8.Certainly, row address is defeated
Enter the row address signal line number mesh that module 20 includes but is not limited to above embodiment, the number of the row address inputted as needed
The number of signal wire is determined, in the protection scope of present embodiment.
In one embodiment, logic decoding processor 30 includes first and door 310, second and door 320 and decoding
Device 330.
First row address signal for being used to have chosen with door 310 and reverse phase test signal carry out NAND Logic operation, raw
At anti-phase output row address.First includes first input end 311, the second input terminal 312 and the first output end 313 with door 310.
First input end 311 is connected to the row address signal line chosen, and the second input terminal 312 is connected to test pattern output end 12,
For receiving reverse phase test signal, the first output end 313 is connected to code translator 330.
Second reverse phase row address signal corresponding with the row address signal that door 320 is used to have chosen and reverse phase test signal
NAND Logic operation is carried out, positive is generated and exports row address, second includes third input terminal 321, the 4th input terminal with door 320
322 and second output terminal 323, third input terminal 321 be connected to corresponding second phase inverter of the row address signal line chosen
Output end 202, the 4th input terminal 322 is connected to test pattern output end 12, and second output terminal 323 is connected to code translator
330。
Code translator 330 is by anti-phase output row address, positive output row address, the row address signal do not chosen and unselected
The reverse phase row address signal taken carries out decoding processing, obtains row address control signal, and row address control signal is non-including that can make
Two effective open signals that two adjacent wordline open simultaneously.The decoding input terminal of code translator 30 is respectively connected to
One output end 313, second output terminal 323 and the row address signal line 201 that do not choose and the second phase inverter that do not choose
Output end 202, decoding output end are connected to each wordline 40.
Wherein, first reverse phase test signal is subjected to NAND Logic operation with the row address signal RA1 chosen with door 310
Export anti-phase output row address RANint1.Second with door 320 by the corresponding reverse phase row address of the row address signal RA1 chosen
Signal RAN1 and reverse phase test signal carry out NAND Logic operation, generate positive and export row address RAint1.
In one embodiment, code translator 30 include the first decoder 331, the first decoder 331 include one group just
Phase input terminal and one group of inverting input terminal, the first output end 313 and second output terminal 323 are respectively connected to the first decoder 331
Corresponding inverting input terminal and normal phase input end.Code translator 330 further includes the second decoder 332 and third decoder 333,
The input terminal of second decoder 332 includes for receiving the one of multiple row address signals group of normal phase input end and for receiving reverse phase
One group of inverting input terminal of row address signal.The input terminal of third decoder 333 includes for receiving multiple row address signals
One group of normal phase input end and one group of inverting input terminal for receiving reverse phase row address signal.
Specifically, the first decoder 331 includes three normal phase input ends, it is RA0, RA1, RA2 input terminal and three respectively
Inverting input terminal is RAN0, RAN1, RAN2 input terminal respectively.Wherein, RA0 input terminal and RA2 input terminal are defeated with row address respectively
Enter the row address signal of the row address signal line 201 and row address signal RA2 for receiving row address signal RA0 in module 20
Line 201 connects.RAN0 input terminal and RAN2 input terminal are used to export the second of RAN0 with row address input module 20 respectively
Inverter output 202 is connected with the second inverter output RAN2 for exporting RAN2.The RA1 of first decoder 331 is defeated
Enter end and connects one to one with second with the second output terminal 323 of the output anti-phase output row address RANint1 of door 320, first
The RAN1 input terminal of decoder 331 and first with door 310 output positive output row address RAint1 second output terminal 323 1
One is correspondingly connected with.
Second decoder 332 includes three normal phase input ends, is RA3, RA4, RA5 input terminal and three anti-phase inputs respectively
End, is RAN3, RAN4, RAN5 input terminal respectively.RA3 input terminal, RA4 input terminal and RA5 input terminal are defeated with row address respectively
The three row address signal lines 201 for receiving row address signal RA3, RA4, RA5 entered in module 20 connect one to one.
RAN3 input terminal, RAN4 input terminal and RAN5 input terminal respectively in row address input module 20 for export RAN3,
Three the second inverter outputs 202 of RAN4 and RAN5 connect one to one.
Third decoder 333 includes three normal phase input ends, is RA6, RA7, RA8 input terminal and three anti-phase inputs respectively
End, is RAN6, RAN7, RAN8 input terminal respectively.RA6 input terminal, RA7 input terminal and RA8 input terminal are defeated with row address respectively
The three row address signal lines 201 for receiving row address signal RA6, RA7, RA8 entered in module 20 connect one to one.
RAN6 input terminal, RAN7 input terminal and RAN8 input terminal respectively in row address input module 20 for export RAN6,
Three the second inverter outputs 202 of RAN7 and RAN8 connect one to one.
Code translator 30 further includes the 4th decoder 334, the output of the input terminal and the first decoder of the 4th decoder 334
The output end 337 of the output end 336 and third decoder of holding the 335, second decoder connects, the input terminal of the first decoder,
The input terminal of the input terminal of second decoder and the third decoder forms the signal input part 32 of logic decoding processor,
The output end of 4th decoder forms the signal output end 33 of logic decoding processor, is connected to each wordline 40.4th decoder
Each wordline of the second row address control signal control of 334 outputs opens and closes, and effectively opens letter according to described two
Number non-adjacent two wordline 40 of control open simultaneously.
It is WL0-WL512 respectively as shown in fig. 6, including 516 wordline 40 in storage array.Most latter linked wordline
40 number adjusts in suitable range according to actual needs, in the protection scope of the present embodiment.
Embodiment three
The utility model additionally provides a kind of semiconductor memory, including Word line control circuit described in any of the above embodiments dress
It sets.
Above description is only a specific implementation of the present invention, but the protection scope of the utility model is not limited to
In this, anyone skilled in the art within the technical scope disclosed by the utility model, it is each can to readily occur in it
Kind change or replacement, these should be covered within the scope of the utility model.Therefore, the protection scope of the utility model
It should be based on the protection scope of the described claims.
Claims (8)
1. a kind of Word line control circuit device, which is characterized in that including test pattern input module, row address input module and
The output end of logic decoding processor, test pattern input module output end and row address input module is connected to the logic and translates
The signal input part of code processor, the signal output end of the logic decoding processor and a plurality of wordline of storage array it is corresponding connect
It connects；
The test pattern input module is for receiving test mode signal, and the row address input module is for receiving multiple rows
Address signal, the logic decoding processor are used to carry out logic to the multiple row address signal and the test mode signal
And decoding processing, it generates row address and controls signal, the row address control signal includes at least two effective open signals, is used for
Non-adjacent at least two wordline are controlled to open simultaneously.
2. device as described in claim 1, which is characterized in that the test pattern input module includes test pattern input
End, the first phase inverter and the test pattern output end, the test pattern input terminal is for receiving the test pattern letter
Number, first phase inverter is used to the test mode signal carrying out reverse phase operation, generates reverse phase and tests signal, the test
Mode output end is for exporting the reverse phase test signal.
3. device as claimed in claim 2, which is characterized in that the row address input module includes a plurality of row address signal line
And multiple second phase inverters being separately connected with each row address signal line, each row address signal line are respectively used to connect
Receive corresponding row address signal in the row address input signal, second phase inverter be used for each row address signal into
Row inverted logic operation obtains multiple reverse phase row address signals.
4. device as claimed in claim 3, which is characterized in that the logic decoding processor include first with door, second with
Door and code translator；
Described first row address signal for being used to have chosen with door and reverse phase test signal progress and logical operation, generate
Anti-phase output row address, described first and door include first input end, the second input terminal and the first output end, and described first is defeated
Enter end and be connected to the corresponding row address signal line of row address signal chosen, second input terminal is connected to the survey
Die trial formula output end, for receiving the reverse phase test signal；
Described second reverse phase row address signal corresponding with the row address signal that door is used to have chosen and reverse phase test are believed
Number carry out and logical operation, generate positive export row address, described second with door include third input terminal, the 4th input terminal and
Second output terminal, the third input terminal are connected to the output of corresponding second phase inverter of row address signal chosen
End, the 4th input terminal are connected to the test pattern output end；
The code translator is used for the anti-phase output row address, positive output row address, the row ground that do not choose
Location signal and the reverse phase row address signal that do not choose carry out decoding processing, obtains row address control signal, the row
It includes at least two effective open signals that non-adjacent at least two wordline can be made to open simultaneously that location, which controls signal,.
5. device as claimed in claim 4, which is characterized in that the code translator includes the first decoder, and described first translates
Code device includes one group of normal phase input end and one group of inverting input terminal, and first output end and the second output terminal are separately connected
To corresponding inverting input terminal and corresponding normal phase input end.
6. device as claimed in claim 5, which is characterized in that the code translator further includes the second decoder and third decoding
Device, the input terminal of second decoder include for receiving the one of the row address signal that do not choose group of normal phase input end and being used for
Receive one group of inverting input terminal of the reverse phase row address signal that do not choose；
The input terminal of the third decoder includes for receiving the one of the row address signal that do not choose group of normal phase input end and use
In one group of inverting input terminal for receiving the reverse phase row address signal that do not choose.
7. device as claimed in claim 6, which is characterized in that the code translator further includes the 4th decoder, and the described 4th
The output end of the input terminal of decoder and first decoder, the output end of second decoder and the third decode
The output end of device connects；
The input terminal shape of the input terminal of first decoder, the input terminal of second decoder and the third decoder
At the signal input part of the logic decoding processor, the output end of the 4th decoder forms the logic decoding processor
Signal output end, be connected to each wordline.
8. a kind of semiconductor memory, including such as the described in any item Word line control circuit devices of claim 1-7.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821876360.8U CN208834750U (en) | 2018-11-14 | 2018-11-14 | Word line control circuit device and semiconductor memory |
| PCT/CN2019/116063 WO2020098549A1 (en) | 2018-11-14 | 2019-11-06 | Word line control method, word line control circuit device and semiconductor memory |
| US17/171,307 US11693584B2 (en) | 2018-11-14 | 2021-02-09 | Word line control method, word line control circuit device and semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821876360.8U CN208834750U (en) | 2018-11-14 | 2018-11-14 | Word line control circuit device and semiconductor memory |
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| Publication Number | Publication Date |
|---|---|
| CN208834750U true CN208834750U (en) | 2019-05-07 |
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| CN201821876360.8U Active CN208834750U (en) | 2018-11-14 | 2018-11-14 | Word line control circuit device and semiconductor memory |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020098549A1 (en) * | 2018-11-14 | 2020-05-22 | Changxin Memory Technologies, Inc. | Word line control method, word line control circuit device and semiconductor memory |
| CN114765054A (en) * | 2021-01-14 | 2022-07-19 | 长鑫存储技术有限公司 | Error correction system |
| CN115425957A (en) * | 2022-11-04 | 2022-12-02 | 西安水木芯邦半导体设计有限公司 | Multi-channel switch array control circuit and automatic detection system |
| CN114765054B (en) * | 2021-01-14 | 2024-05-14 | 长鑫存储技术有限公司 | Error correction system |
-
2018
- 2018-11-14 CN CN201821876360.8U patent/CN208834750U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020098549A1 (en) * | 2018-11-14 | 2020-05-22 | Changxin Memory Technologies, Inc. | Word line control method, word line control circuit device and semiconductor memory |
| US11693584B2 (en) | 2018-11-14 | 2023-07-04 | Changxin Memory Technologies, Inc. | Word line control method, word line control circuit device and semiconductor memory |
| CN114765054A (en) * | 2021-01-14 | 2022-07-19 | 长鑫存储技术有限公司 | Error correction system |
| CN114765054B (en) * | 2021-01-14 | 2024-05-14 | 长鑫存储技术有限公司 | Error correction system |
| CN115425957A (en) * | 2022-11-04 | 2022-12-02 | 西安水木芯邦半导体设计有限公司 | Multi-channel switch array control circuit and automatic detection system |
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