CN111181513B - Data security transmission circuit - Google Patents
Data security transmission circuit Download PDFInfo
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- CN111181513B CN111181513B CN202010132340.5A CN202010132340A CN111181513B CN 111181513 B CN111181513 B CN 111181513B CN 202010132340 A CN202010132340 A CN 202010132340A CN 111181513 B CN111181513 B CN 111181513B
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- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 7
- 230000003321 amplification Effects 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 description 7
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
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Abstract
The invention discloses a data safety transmission circuit, which comprises a frequency acquisition module 1, a frequency acquisition module 2 and a differential regulation module, wherein the frequency acquisition module 1 and the frequency acquisition module 2 adopt a frequency collector J1 and a frequency collector J2 of a model SJ-ADC to acquire carrier signal frequencies of adjacent data channels, the differential regulation module adopts an operational amplifier AR1, an operational amplifier AR2 and an operational amplifier AR3 to form a differential operational amplifier circuit to carry out differential-amplification regulation on signals output by the frequency acquisition module 1 and the frequency acquisition module 2, simultaneously adopts a frequency selection circuit consisting of capacitors C3-C5 to select a signal with single frequency, adopts a fine tuning circuit consisting of a triode Q1 and a triode Q2 to carry out potential detection regulation on the signal, and finally adopts a peak selection circuit consisting of the operational amplifier AR5, a diode D3 and a diode D4 to trigger a signal transmitter E1 to work, can compare and regulate the carrier signal frequencies of the adjacent data channels, and convert the carrier signals into error correction signals of a data control terminal.
Description
Technical Field
The invention relates to the technical field of data security, in particular to a data security transmission circuit.
Background
Data transmission quantity is increased more and more, which leads to continuous efforts to improve data transmission quantity, on the basis of improving data transmission quantity, data safety is ensured, meanwhile, along with the continuous increase of data transmission quantity, the protection difficulty of data safety is increased more and more, data safety transmission needs to be upgraded and optimized simultaneously, the increase of data transmission quantity passes through a multi-channel synchronous transmission mode or a bandwidth increasing mode, synchronous detection of multiple channels is needed simultaneously aiming at the multi-channel synchronous transmission, the method is different from the traditional single-channel detection and can play a safety role, the current prior art only carries out safe encryption detection on each channel on the basis of the multi-channel transmission, synchronous multi-channel detection cannot be realized, time errors among the channels are increased easily, and therefore data transmission safety error signals are caused, and false alarm of signal transmission is caused.
Disclosure of Invention
In view of the above, it is an object of the present invention to provide a data security transmission circuit, which can compare and adjust the frequency of the carrier signal of the adjacent data channel and convert the carrier signal into an error correction signal of the data control terminal.
The technical scheme of its solution is, a data security transmission circuit, including frequency acquisition module 1, frequency acquisition module 2, difference adjusting module, frequency acquisition module 1, frequency acquisition module 2 application model are SJ-ADC's frequency collector J1, frequency collector J2 gather adjacent data channel's carrier signal frequency, difference adjusting module application fortune amplifier AR1, fortune amplifier AR2, fortune amplifier AR3 constitute difference fortune amplifier circuit and carry out the difference-amplification regulation to frequency acquisition module 1, 2 output signal of frequency acquisition module, simultaneously application electric capacity C3-electric capacity C5 constitute the signal that the frequency selection circuit screened single frequency, application triode Q1, triode Q2 constitute fine setting circuit simultaneously and carry out the electric potential detection regulation to the signal, at last application fortune amplifier AR5 and diode D3, diode D4 constitute peak value circuit and select peak value signal trigger signal transmitter E1 work, send to in the data control terminal.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages;
1. the difference operational amplifier circuit formed by the operational amplifier AR1, the operational amplifier AR2 and the operational amplifier AR3 is used for carrying out difference-amplification regulation on output signals of the frequency acquisition module 1 and the frequency acquisition module 2, so that a static working point is effectively stabilized, a differential mode signal is amplified to inhibit a common mode signal, more importantly, the difference between the two paths of signals can be calculated in a difference mode, a difference signal of carrier signal frequencies of adjacent data channels is amplified, namely, a time error between the channels is amplified, and meanwhile, a frequency selection circuit formed by a capacitor C3-a capacitor C5 is used for screening out a signal with a single frequency, so that the stability of the difference signal is ensured;
2. the application triode Q1, triode Q2 constitutes the fine setting circuit and carries out the potential detection regulation to the signal, the fine setting circuit detects the potential difference of fortune ware AR3 output signal and frequency selection circuit output signal, prevent that the frequency selection circuit from adjusting the signal in-process and producing the clutter, wherein fortune ware AR4 plays the effect of synchronous buffer signal, at last application fortune ware AR5 and diode D3, diode D4 constitutes the peak value circuit and selects peak signal trigger signal transmitter E1 work, send to in the data control terminal, the peak value signal is convenient for directly the work of signal transmitter E1 that sets out, data control terminal received signal can error correction in time simultaneously.
Drawings
Fig. 1 is a diagram of a frequency acquisition module 1 of a data security transmission circuit according to the present invention.
Fig. 2 is a diagram of a frequency acquisition module 2 of a data security transmission circuit according to the present invention.
Fig. 3 is a block diagram of a differential adjustment circuit of a data security transmission circuit according to the present invention.
Detailed Description
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which proceeds with reference to the accompanying drawings, FIGS. 1 to 3. The structural contents mentioned in the following embodiments are all referred to the attached drawings of the specification.
In the first embodiment, a data security transmission circuit comprises a frequency acquisition module 1, a frequency acquisition module 2 and a differential adjustment module, wherein the frequency acquisition module 1 and the frequency acquisition module 2 acquire carrier signal frequencies of adjacent data channels by using a frequency collector J1 and a frequency collector J2 of a model SJ-ADC, the differential adjustment module uses an operational amplifier AR1, an operational amplifier AR2 and an operational amplifier AR3 to form a differential operational amplifier circuit to perform differential amplification adjustment on output signals of the frequency acquisition module 1 and the frequency acquisition module 2, simultaneously uses a capacitor C3-capacitor C5 to form a frequency selection circuit to select a signal with single frequency, uses a triode Q1 and a triode Q2 to form a fine adjustment circuit to perform potential detection adjustment on the signal, and finally uses the operational amplifier AR5, a diode D3 and a diode D4 to form a peak selection circuit to select a peak signal to trigger a signal transmitter E1 to work and transmit the peak signal to a data control terminal;
the difference adjusting module utilizes an operational amplifier AR1, an operational amplifier AR2 and an operational amplifier AR3 to form a difference operational amplifier circuit to perform difference-amplification adjustment on output signals of the frequency acquisition module 1 and the frequency acquisition module 2, effectively stabilizes a static working point, inhibits common-mode signals by amplifying differential-mode signals, more importantly, can perform difference calculation on two paths of signals, calculates the difference between the two paths of signals, amplifies the difference signals of carrier signal frequencies of adjacent data channels, namely amplifies time errors between the channels, and utilizes a frequency selection circuit consisting of a capacitor C3-a capacitor C5 to screen out signals with single frequency, so as to ensure the stability of the difference signals, and utilizes a fine tuning circuit consisting of a triode Q1 and a triode Q2 to perform potential detection adjustment on the signals, the fine tuning circuit detects the potential difference between the output signals of the operational amplifier AR3 and the output signals of the frequency selection circuit, so as to prevent clutter from being generated in the signal adjusting process of the frequency selection circuit, wherein the operational amplifier AR4 plays a role of synchronous buffer signal, and finally utilizes the operational amplifier AR5, a diode D3 and a diode D4 to form a peak value circuit to screen out a peak value signal triggering signal emitter E1 to send the work into a data control terminal, so that the peak value signal emitter can directly start the data control terminal and correct errors in time;
the differential regulation module has a specific structure that the in-phase input end of the operational amplifier AR1 is connected with one end of a resistor R3, the anti-phase input end of the operational amplifier AR1 is connected with the anti-phase input end of the operational amplifier AR2 and one end of a resistor R7 and a resistor R8, the in-phase input end of the operational amplifier AR2 is connected with one end of a resistor R4, the output end of the operational amplifier AR1 is connected with the other end of the resistor R7 and one end of a resistor R5, the other end of the resistor R5 is connected with the in-phase input end of the operational amplifier AR3 and one end of a resistor R6, the other end of the resistor R6 is grounded, the output end of the operational amplifier AR2 is connected with the other end of the resistor R8 and one end of a resistor R9, the other end of the resistor R9 is connected with the anti-phase input end of the operational amplifier AR3 and one end of a resistor R10, the other end of the resistor R10 is connected with the output end of the operational amplifier AR3, the in-phase input end of the operational amplifier AR4 and one end of a resistor R12 and one end of a capacitor C3, the inverting input end of the operational amplifier AR4 is connected with one end of a resistor R11, the output end of the operational amplifier AR4 is connected with the collector of a triode Q1, the collector of the triode Q2 and the other end of the resistor R11, the other end of a resistor R12 is connected with one end of a resistor R13 and one end of a capacitor C4, the other end of the capacitor C3 is connected with a resistor R14 and one end of a capacitor C5, the resistor R14 and the other end of the capacitor C4 are grounded, the other end of the resistor R13 is connected with the base of the capacitor C5 and the base of the triode Q1, the anode of a diode D4 and the non-inverting input end of the operational amplifier AR5, the emitter of the triode Q1 is connected with the base of the triode Q2 and the cathode of the diode D4, the cathode of the diode D3 and the output end of the operational amplifier AR5, the inverting input end of the operational amplifier AR5 is grounded, the emitter of the triode Q2 is connected with one end of the resistor R15, and the anode of the diode D3 is connected with the signal emitter E1.
In the second embodiment, on the basis of the first embodiment, the frequency acquisition module 1 and the frequency acquisition module 2 adopt a frequency acquisition unit J1 and a frequency acquisition unit J2 of a type SJ-ADC to acquire the carrier signal frequency of an adjacent data channel, a power supply end of the frequency acquisition unit J1 is connected to +5V, a grounding end of the frequency acquisition unit J1 is grounded, an output end of the frequency acquisition unit J1 is connected to one end of a resistor R1 and a cathode of a voltage regulator tube D1, an anode of the voltage regulator tube D1 is grounded, the other end of the resistor R1 is connected to one end of a capacitor C1 and the other end of a resistor R3, and the other end of the capacitor C1 is grounded; the power supply end of the frequency collector J2 is connected with +5V of a power supply, the grounding end of the frequency collector J2 is grounded, the output end of the frequency collector J2 is connected with one end of a resistor R2 and the negative electrode of a voltage-regulator tube D2, the positive electrode of the voltage-regulator tube D2 is grounded, the other end of the resistor R2 is connected with one end of a capacitor C2 and the other end of a resistor R4, and the other end of the capacitor C2 is grounded.
When the invention is used in detail, a data safety transmission circuit comprises a frequency acquisition module 1, a frequency acquisition module 2 and a differential regulation module, wherein the frequency acquisition module 1 and the frequency acquisition module 2 use a frequency collector J1 and a frequency collector J2 of a model SJ-ADC to acquire carrier signal frequencies of adjacent data channels, the differential regulation module uses an operational amplifier AR1, an operational amplifier AR2 and an operational amplifier AR3 to form a differential operational amplifier circuit to carry out differential-amplification regulation on output signals of the frequency acquisition module 1 and the frequency acquisition module 2, effectively stabilize a static working point, amplify differential mode signals to inhibit common mode signals, more importantly, can carry out differential calculation on two paths of signals, calculate the difference value between the two paths of signals and amplify the difference value signal of the carrier signal frequencies of the adjacent data channels, that is, time errors between channels are amplified, a frequency selection circuit consisting of capacitors C3-C5 is used for screening out signals with single frequency, stability of difference signals is guaranteed, a fine tuning circuit consisting of a triode Q1 and a triode Q2 is used for carrying out potential detection and adjustment on the signals, the fine tuning circuit detects potential differences of output signals of an operational amplifier AR3 and output signals of the frequency selection circuit, clutter is prevented from being generated in the process of adjusting signals of the frequency selection circuit, the operational amplifier AR4 plays a role in synchronous buffer signals, finally a peak circuit consisting of the operational amplifier AR5, a diode D3 and a diode D4 is used for screening out a peak signal trigger signal emitter E1 to work and sending the peak signal trigger signal emitter E1 to a data control terminal, the peak signal is convenient for directly starting the signal emitter E1 to work, and meanwhile, errors can be corrected in time when the signals received by the data control terminal.
While the invention has been described in further detail with reference to specific embodiments thereof, it is not intended that the invention be limited to the specific embodiments thereof; for those skilled in the art to which the present invention pertains and related technologies, the extension, operation method and data replacement should fall within the protection scope of the present invention based on the technical solution of the present invention.
Claims (2)
1. A data safety transmission circuit comprises a frequency acquisition module 1, a frequency acquisition module 2 and a differential regulation module, and is characterized in that the frequency acquisition module 1 and the frequency acquisition module 2 collect carrier signal frequencies of adjacent data channels by using a frequency collector J1 and a frequency collector J2 of a model SJ-ADC, the differential regulation module uses an operational amplifier AR1, an operational amplifier AR2 and an operational amplifier AR3 to form a differential operational amplifier circuit to carry out differential amplification regulation on output signals of the frequency acquisition module 1 and the frequency acquisition module 2, simultaneously uses a capacitor C3-capacitor C5 to form a frequency selection circuit to select a signal with single frequency, uses a triode Q1 and a triode Q2 to form a fine tuning circuit to carry out potential detection regulation on the signal, and finally uses the operational amplifier AR5, a diode D3 and a diode D4 to form a peak selection circuit to select a peak signal to trigger a signal transmitter E1 to work and transmit the signal to a data control terminal;
the differential regulation module comprises an operational amplifier AR1, wherein the non-inverting input end of the operational amplifier AR1 is connected with one end of a resistor R3, the inverting input end of the operational amplifier AR1 is connected with the inverting input end of the operational amplifier AR2 and one end of a resistor R7 and a resistor R8, the non-inverting input end of the operational amplifier AR2 is connected with one end of a resistor R4, the output end of the operational amplifier AR1 is connected with the other end of the resistor R7 and one end of a resistor R5, the other end of the resistor R5 is connected with the non-inverting input end of the operational amplifier AR3 and one end of a resistor R6, the other end of the resistor R6 is grounded, the output end of the operational amplifier AR2 is connected with the other end of the resistor R8 and one end of a resistor R9, the other end of the resistor R9 is connected with the inverting input end of the operational amplifier AR3 and one end of a resistor R10, the other end of the resistor R10 is connected with the output end of the operational amplifier AR3, the non-inverting input end of the operational amplifier AR4 and one end of a resistor R12 and one end of a capacitor C3, the inverting input end of the operational amplifier AR4 is connected with one end of a resistor R11, the output end of the operational amplifier AR4 is connected with the collector of a triode Q1, the collector of the triode Q2 and the other end of the resistor R11, the other end of a resistor R12 is connected with one end of a resistor R13 and one end of a capacitor C4, the other end of the capacitor C3 is connected with a resistor R14 and one end of a capacitor C5, the resistor R14 and the other end of the capacitor C4 are grounded, the other end of the resistor R13 is connected with the base of the capacitor C5 and the base of the triode Q1, the anode of a diode D4 and the non-inverting input end of the operational amplifier AR5, the emitter of the triode Q1 is connected with the base of the triode Q2 and the cathode of the diode D4, the cathode of the diode D3 and the output end of the operational amplifier AR5, the inverting input end of the operational amplifier AR5 is grounded, the emitter of the triode Q2 is connected with one end of the resistor R15, and the anode of the diode D3 is connected with the signal emitter E1.
2. The data security transmission circuit according to claim 1, wherein the frequency acquisition module 1 comprises a frequency acquisition device J1 with the model of SJ-ADC, a power supply end of the frequency acquisition device J1 is connected with +5V, a grounding end of the frequency acquisition device J1 is grounded, an output end of the frequency acquisition device J1 is connected with one end of a resistor R1 and a cathode of a voltage regulator tube D1, an anode of the voltage regulator tube D1 is grounded, the other end of the resistor R1 is connected with one end of a capacitor C1 and the other end of a resistor R3, and the other end of the capacitor C1 is grounded;
the frequency acquisition module 2 comprises a frequency collector J2 with the model of SJ-ADC, a power supply end of the frequency collector J2 is connected with +5V, a grounding end of the frequency collector J2 is grounded, an output end of the frequency collector J2 is connected with one end of a resistor R2 and the negative electrode of a voltage regulator tube D2, the positive electrode of the voltage regulator tube D2 is grounded, the other end of the resistor R2 is connected with one end of a capacitor C2 and the other end of a resistor R4, and the other end of the capacitor C2 is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010132340.5A CN111181513B (en) | 2020-02-29 | 2020-02-29 | Data security transmission circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010132340.5A CN111181513B (en) | 2020-02-29 | 2020-02-29 | Data security transmission circuit |
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| CN111181513A CN111181513A (en) | 2020-05-19 |
| CN111181513B true CN111181513B (en) | 2023-02-21 |
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| CN113242095B (en) * | 2021-06-29 | 2022-05-06 | 京鼎工程建设有限公司 | Computer electronic communication system |
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