CN111181376B - Three-phase staggered parallel buck PFC circuit and control method thereof - Google Patents

Three-phase staggered parallel buck PFC circuit and control method thereof Download PDF

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Publication number
CN111181376B
CN111181376B CN201911337631.1A CN201911337631A CN111181376B CN 111181376 B CN111181376 B CN 111181376B CN 201911337631 A CN201911337631 A CN 201911337631A CN 111181376 B CN111181376 B CN 111181376B
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phase
diode
circuit
cathode
power tube
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CN111181376A (en
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莫汉岐
吕志明
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Shenzhen Vapel Power Supply Technology Co ltd
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Shenzhen Vapel Power Supply Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4216—Arrangements for improving power factor of AC input operating from a three-phase input voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4291—Arrangements for improving power factor of AC input by using a Buck converter to switch the input current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a three-phase staggered parallel buck PFC circuit and a control method, wherein the three-phase staggered parallel buck PFC circuit uses a staggered parallel circuit, is provided with a buck inductor and a filter capacitor, performs PID control on a capacitor voltage outer ring and an inductor current inner ring through a main controller, and performs feedforward control operation simultaneously to obtain PWM control signals to control a switching tube, so that the volumes of the capacitor and the inductor of the circuit are reduced, the single capacity requirement of the switching tube is small, the current harmonic of a power grid is reduced, and the cost is reduced so as to improve the power factor of the power grid.

Description

Three-phase staggered parallel buck PFC circuit and control method thereof
Technical Field
The invention relates to the technical field of electronic power, in particular to a three-phase staggered parallel buck PFC circuit and a control method.
Background
Because of the uncontrollable rectifying source adopted in the partial rectifying link, a large amount of current harmonic waves are injected into the power grid, and the power factor of the power grid is reduced. The three-phase buck PFC technology has the advantages of controllable power factor, buck, small current harmonic, easy realization of short-circuit protection and the like, and has considerable advantages in the occasion with small power supply volume requirement, particularly in the aerospace field.
The traditional three-phase buck PFC circuit has large capacitance and inductance volume, high voltage resistance requirement on the capacitance, large capacity requirement on a single switch tube, poor power grid current harmonic wave and high system cost.
The above disadvantages are to be improved.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a three-phase staggered parallel buck PFC circuit and a control method.
The technical scheme of the invention is as follows:
a three-phase staggered parallel buck PFC circuit,
comprises a three-phase input voltage source, a three-phase EMC filter, a virtual midpoint capacitor, an interleaving parallel circuit and a step-down filter circuit,
the interleaved parallel circuit connects the buck filter circuits,
the three-phase input voltage source is connected with the staggered parallel circuit through the three-phase EMC filter and the virtual midpoint capacitor in sequence,
the interleaving parallel circuit comprises a first interleaving circuit and a second interleaving circuit,
the first interleaving circuit is connected in parallel with the second interleaving circuit.
The three-phase interleaved buck PFC circuit comprises three mutually parallel alternating current power supplies Va, an alternating current power supply Vb and an alternating current power supply Vc, wherein the alternating current power supply Va is connected with an A-phase circuit endpoint a, the alternating current power supply Vb is connected with a B-phase circuit endpoint B, and the alternating current power supply Vc is connected with a C-phase circuit endpoint C.
According to the three-phase staggered parallel buck PFC circuit, the virtual midpoint capacitor comprises an A-phase capacitor Ca, a B-phase capacitor Cb and a C-phase capacitor Cc, and the A-phase capacitor Ca, the B-phase capacitor Cb and the C-phase capacitor Cc are connected in parallel.
Further, one end of the a-phase capacitor Ca is connected to the a-phase circuit terminal a, one end of the B-phase capacitor Cb is connected to the B-phase circuit terminal B, one end of the C-phase capacitor Cc is connected to the C-phase circuit terminal C, and the other end of the a-phase capacitor Ca, the other end of the B-phase capacitor Cb, and the other end of the C-phase capacitor Cc are connected to each other.
In the three-phase interleaved parallel buck PFC circuit, the A-phase circuit endpoint a is respectively connected with the first interleaved circuit and the second interleaved circuit, the B-phase circuit endpoint B is respectively connected with the first interleaved circuit and the second interleaved circuit, and the C-phase circuit endpoint C is respectively connected with the first interleaved circuit and the second interleaved circuit.
The three-phase staggered parallel buck PFC circuit,
the first interleaving circuit comprises a first A-phase power tube S a1 First B-phase power tube S b1 First C-phase power tube S c1 ，
First A-phase power tube S a1 The emitter of the (A) phase third diode Da3 is connected with the anode of the A phase first diode Da1 respectivelyIs provided with an anode of the formula (I),
the cathode of the A-phase first diode Da1 is connected with the anode of the A-phase second diode Da2,
the cathodes of the A-phase second diode Da2 are respectively connected with the first A-phase power tube S a1 And the cathode of the a-phase fourth diode Da4,
first B-phase power tube S b1 The emitters of the first diode Db1 are respectively connected with the anode of the third diode Db3 in the B phase and the anode of the first diode Db1 in the B phase,
the cathode of the B-phase first diode Db1 is connected to the anode of the B-phase second diode Db2,
the cathode of the B-phase second diode Db2 is respectively connected with the cathode of the B-phase fourth diode Db4 and the first B-phase power tube S b1 Is provided with a collector electrode of the (c),
first C-phase power tube S c1 The emitter of the third diode Dc3 of the C phase and the anode of the first diode Dc1 of the C phase are respectively connected,
the cathode of the C-phase first diode Dc1 is connected with the anode of the C-phase second diode Dc2,
the cathodes of the C-phase second diode Dc2 are respectively connected with the first C-phase power tube S c1 And the collector of the C-phase fourth diode Dc4,
the cathode of the A-phase third diode Da3, the cathode of the B-phase third diode Db3 and the cathode of the C-phase third diode Dc3 are all connected with the cathode of the first diode D1,
the anode of the a-phase fourth diode Da4, the anode of the B-phase fourth diode Db4, and the anode of the C-phase fourth diode Dc4 are all connected to the anode of the first diode D1.
Further, the a-phase circuit terminal a is connected to the a-phase input end of the first interleaving circuit, the B-phase circuit terminal B is connected to the B-phase input end of the first interleaving circuit, and the C-phase circuit terminal C is connected to the C-phase input end of the first interleaving circuit.
Further, the a-phase input end of the first interleaving circuit is disposed between the a-phase first diode Da1 and the a-phase second diode Da2, the B-phase input end of the first interleaving circuit is disposed between the B-phase first diode Db1 and the B-phase second diode Db2, the C-phase input end of the first interleaving circuit is disposed between the C-phase first diode Dc1 and the C-phase second diode Dc2, and the three-phase input voltage source is respectively connected with the a-phase input end of the first interleaving circuit, the B-phase input end of the first interleaving circuit, and the C-phase input end of the first interleaving circuit.
The three-phase staggered parallel buck PFC circuit,
the second interleaving circuit comprises a second A-phase power tube S a2 Second B-phase power tube S b2 Second C-phase power tube S c2 ，
Second A-phase power tube S a2 The emitters of the fifth diode Da5 are respectively connected with the anode of the seventh diode Da7 of the A phase and the anode of the fifth diode Da5 of the A phase,
the cathode of the fifth diode Da5 of the a phase is connected with the anode of the sixth diode Da6 of the a phase,
the cathodes of the A-phase sixth diode Da6 are respectively connected with a second A-phase power tube S a2 And the cathode of the eighth diode Da8 of phase a,
second B-phase power tube S b2 The emitters of the fifth diode Db5 are respectively connected with the anode of the seventh diode Db7 in the B phase and the anode of the fifth diode Db5 in the B phase,
the cathode of the fifth diode Db5 of phase B is connected to the anode of the sixth diode Db6 of phase B,
the cathode of the B-phase sixth diode Db6 is respectively connected with the cathode of the B-phase eighth diode Db8 and the second B-phase power tube S b2 Is provided with a collector electrode of the (c),
second C-phase power tube S c2 The emitters of the fifth diode Dc5 are respectively connected with the anode of the seventh diode Dc7 of the C phase and the anode of the fifth diode Dc5 of the C phase,
the cathode of the C-phase fifth diode Dc5 is connected with the anode of the C-phase sixth diode Dc6,
the cathodes of the C-phase sixth diode Dc6 are respectively connected with the second C-phase power tube S c2 And the collector of the C-phase eighth diode Dc8,
the cathode of the A-phase seventh diode Da7, the cathode of the B-phase seventh diode Db7 and the cathode of the C-phase seventh diode Dc7 are connected with the cathode of the second diode D2,
the anode of the a-phase eighth diode Da8, the anode of the B-phase eighth diode Db8, and the anode of the C-phase eighth diode Dc8 are all connected to the anode of the second diode D2.
Further, the a-phase circuit terminal a is connected to the a-phase input end of the second interleaving circuit, the B-phase circuit terminal B is connected to the B-phase input end of the second interleaving circuit, and the C-phase circuit terminal C is connected to the C-phase input end of the second interleaving circuit.
Further, the a-phase input end of the second interleaving circuit is disposed between the a-phase fifth diode Da5 and the a-phase sixth diode Da6, the B-phase input end of the second interleaving circuit is disposed between the B-phase fifth diode Db5 and the B-phase sixth diode Db6, the C-phase input end of the second interleaving circuit is disposed between the C-phase fifth diode Dc5 and the C-phase sixth diode Dc6, and the three-phase input voltage source is respectively connected with the a-phase input end of the second interleaving circuit, the B-phase input end of the second interleaving circuit, and the C-phase input end of the second interleaving circuit.
In the three-phase interleaved parallel buck PFC circuit, a first output end of a first interleaved circuit is connected with a cathode of a first diode D1, a second output end of the first interleaved circuit is connected with an anode of the first diode D1, a third output end of a second interleaved circuit is connected with a cathode of a second diode D2, and a fourth output end of the second interleaved circuit is connected with an anode of the second diode D2.
The first output end of the first interleaving circuit is connected with one end of a first inductor L1, the second output end of the first interleaving circuit is respectively connected with the fourth output end of the second interleaving circuit and the other end of a first capacitor C1, the third output end of the second interleaving circuit is connected with one end of a second inductor L2, the other end of the first inductor L1 is respectively connected with the other end of the second inductor L2 and one end of the first capacitor C1, and the two ends of the first capacitor C1 are dc voltages V BUS 。
Further, the first capacitor C1 is a filter capacitor.
Further, the first inductor L1 and the second inductor L2 are both buck inductors.
A control method of a three-phase staggered parallel buck PFC circuit comprises the following steps:
s1, sampling power grid voltage and calculating a phase-locked loop: collecting the voltage of a three-phase input voltage source, performing phase-locked loop calculation on the power grid voltage to obtain the phase angles sin (theta) and cos (theta) of the power grid voltage,
s2, capacitor voltage outer ring control: collecting DC voltage V BUS With a given DC voltageComparing, performing PID control operation on the difference value of the two to obtain an inductance current reference value i * ，
S3, inductance current inner loop control: input inductor current reference i * And a first interleaved circuit inductor current feedback value i 1 The difference value is subjected to PID control operation to obtain a first loop output value out1; input the second interleaving circuit inductance current feedback value i 2 Which is related to the inductor current reference i * The difference value of (2) is subjected to PID control operation to obtain a second loop output value out2,
s4, feedforward control: the phase angles sin (theta) and cos (theta) of the grid voltage, the first loop output value out1 and the first loop output value out2 are subjected to feedforward control operation to obtain a first duty ratio control quantity duty1 and a second duty ratio control quantity duty2,
s5, generating PWM control signals in an interleaving and parallel mode: the first duty control amount duty1 and the second duty control amount duty2 are PWM modulated to generate a PWM control signal PWM (S a1 ，S b1 ，S c1 ) And PWM (S) a2 ，S b2 ，S c2 )。
The control method of the three-phase staggered parallel buck PFC circuit comprises a PFC circuit, a main controller, a PWM signal generation module and a phase-locked loop calculation module, wherein the main controller comprises a first PID regulator, a second PID regulator, a third PID regulator and a feedforward controller, the first PID regulator is connected with the PFC circuit, the first PID regulator is respectively connected with the second PID regulator and the third PID regulator, the feedforward controller is respectively connected with the phase-locked loop calculation module, the second PID regulator and the third PID regulator, and the PWM signal generation module is connected with the feedforward controller.
The control method of the three-phase staggered parallel buck PFC circuit comprises the PFC circuit and a main controller, wherein the main controller comprises a first PID regulator, a second PID regulator, a third PID regulator, a feedforward controller and a phase-locked loop calculation module; the voltage ring collects direct current voltage V BUS And a given DC voltageThe signal is used for sending the difference signal calculated by the signal and the signal to the first PID regulator; the first PID regulator receives the difference signal and outputs an inductor current reference value i * Signal to the first current loop and the second current loop; the first current loop acquires a first interleaved circuit inductance current feedback value i of the PFC circuit 1 A signal, the first current loop receives an inductance current reference value i * The signal and the difference signal calculated by the signal and the difference signal are sent to a second PID regulator; the second current loop collects a second interleaved circuit inductance current feedback value i of the PFC circuit 2 The second current loop receives the inductance current reference value i * The signal and the difference signal calculated by the signal and the difference signal are sent to a third PID regulator; the second PID regulator receives the signal of the first current loop and the phase angle sin (theta) and cos (theta) signals of the power grid voltage, and outputs a first loop output value out1 signal to the feedforward controller after operation; the third PID regulator receives the signal of the second current loop and the phase angle sin (theta) and cos (theta) signals of the power grid voltage, and outputs a second loop output value out2 signal to the feedforward controller after operation; the feedforward controller outputs a first duty ratio control amount duty1 signal and a second duty ratio control amount duty2 signal to a PWM signal generating module through operation, and the PWM signal generating module outputs a PWM control signal PWM (S) a1 ，S b1 ，S c1 ) To the first A-phase power tube S a1 First B-phase power tube S b1 First C-phase power tube S c1 Output PWM (S) a2 ，S b2 ，S c2 ) To the firstTwo A-phase power tube S a2 Second B-phase power tube S b2 Second C-phase power tube S c2 。
According to the control method of the three-phase staggered parallel buck PFC circuit, a power grid is divided into 6 sectors, and the duty ratio of power tubes corresponding to each sector is different.
In the control method of the three-phase interleaved parallel buck PFC circuit, the first a-phase power tube Sa1 of the first interleaved circuit and the second a-phase power tube Sa2 of the second interleaved circuit are controlled to be interleaved by 180 ° in duty ratio, the first B-phase power tube Sb1 of the first interleaved circuit and the second B-phase power tube Sb2 of the second interleaved circuit are controlled to be interleaved by 180 ° in duty ratio, and the first C-phase power tube Sc1 of the first interleaved circuit and the second C-phase power tube Sc2 of the second interleaved circuit are controlled to be interleaved by 180 ° in duty ratio.
In the control method of the three-phase staggered parallel buck PFC circuit, in the step S2 and the step S3, both the capacitor voltage outer loop control and the inductor voltage inner loop control adopt PID control, and the PID control operation formula is as follows
Wherein,,
e k inputting error amount for the time;
e k-1 for the last error input, the software records to obtain the value;
e k-2 for the last error input, the software records to obtain the value;
u k the output value is the PID operation;
u k-1 the software records this value for the output value of the last PID operation.
K p ，Integral requirement for PID controlAnd (5) a fixed parameter.
In the control method of the three-phase staggered parallel buck PFC circuit, in step S4, the feedforward control formula is as follows
Wherein duty1 is a first duty control amount;
V BUS the current bus voltage value;
V N is a power grid module value;
V max the instantaneous maximum value of the power grid can be obtained according to the phase angles sin (theta) and cos (theta) of the power grid voltage;
out1 is the PID regulator output value.
The control method of the three-phase staggered parallel buck PFC circuit,
in step S1, the phase-locked loop calculation formula is
And
calculating v twice before and after q Is a difference Deltav of (a) q =last v q Value-this time v q A value;
by continuously adjusting the angle value theta to enable v q After the value is 0, the phase lock is ended.
According to the scheme, the invention has the beneficial effects that,
compared with the traditional three-phase boosting PFC circuit, the invention has the beneficial effects that:
1. the requirement on the voltage resistance of the capacitor is low, and the volume of the capacitor is small;
2. the low-voltage high-current rear stage DC/DC design is easy;
3. short-circuit protection is easy to realize, and reliability is higher.
Compared with the traditional three-phase buck PFC circuit, the invention has the beneficial effects that:
1. under the condition of unchanged voltage ripple, the capacitor and the volume of the capacitor are small, the capacity requirement of a switching tube monomer is small, and the inductive power is low, so that the volume of the power supply can be further reduced;
2. under the condition that the capacitance of the capacitor is unchanged, the ripple wave is reduced after the capacitor is connected in parallel in a staggered way,
3. the current harmonic wave of the power grid is reduced, the inductance ripple is small, and the frequency of the inductance current is doubled;
4. the load can be directly driven to start.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a three-phase interleaved buck PFC circuit;
fig. 2 is a flowchart of a control method of a three-phase interleaved buck PFC circuit;
FIG. 3 is a schematic diagram of three-phase grid voltage waveforms and operating mode analysis points;
FIG. 4 is a schematic diagram of a spatial voltage vector distribution of an interleaved three-phase buck PFC;
FIG. 5 is a diagram showing an analysis of the switch status of sector 1 in FIG. 4;
fig. 6 is a diagram showing an analysis of the switch state of sector 2 in fig. 4.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly or indirectly on the other element. The terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features.
A three-phase staggered parallel buck PFC circuit is shown in FIG. 1, and comprises a three-phase input voltage source, a three-phase EMC filter, a virtual midpoint capacitor, a staggered parallel circuit and a buck filter circuit, wherein the staggered parallel circuit is connected with the buck filter circuit, the three-phase input voltage source is connected with the staggered parallel circuit through the three-phase EMC filter and the virtual midpoint capacitor in sequence, the staggered parallel circuit comprises a first staggered circuit and a second staggered circuit, and the first staggered circuit is connected with the second staggered circuit in parallel. The three-phase EMC filter is arranged on an EMC board, the virtual midpoint capacitor is arranged on a power board, and the EMC board and the power board are all areas on a PCB.
The three-phase input voltage source comprises three mutually parallel alternating current power supplies Va, alternating current power supplies Vb and alternating current power supplies Vc, wherein the alternating current power supplies Va are connected with an A-phase circuit endpoint a, the alternating current power supplies Vb are connected with a B-phase circuit endpoint B, and the alternating current power supplies Vc are connected with a C-phase circuit endpoint C.
The three-phase filter performs secondary filtering on the high-frequency signal generated by the power tube, and filters out the high-frequency part, so that the three-phase current becomes power frequency current, high-frequency harmonic interference is not injected into a power grid, and meanwhile, electromagnetic interference generated by the circuit is limited within a certain range. The three-phase filter can also filter out high-frequency harmonic wave parts contained in the three-phase input voltage source, so that the normal operation of the circuit is not affected.
The virtual midpoint capacitor comprises an A-phase capacitor Ca, a B-phase capacitor Cb and a C-phase capacitor Cc, wherein the A-phase capacitor Ca, the B-phase capacitor Cb and the C-phase capacitor Cc are connected in parallel. One end of the A-phase capacitor Ca is connected with the A-phase circuit endpoint a through a three-phase EMC filter, one end of the B-phase capacitor Cb is connected with the B-phase circuit endpoint B through the three-phase EMC filter, one end of the C-phase capacitor Cc is connected with the C-phase circuit endpoint C through the three-phase EMC filter, and the other end of the A-phase capacitor Ca, the other end of the B-phase capacitor Cb and the other end of the C-phase capacitor Cc are mutually connected. The virtual midpoint capacitor can perform first filtering on the high-frequency signal generated by the power tube and control interference radiation in the power board. In addition, since the three-phase input voltage source is a three-phase three-wire system, no zero line is connected to the circuit, the three-phase voltage cannot be sampled in the circuit, a sampling reference point can be provided for the internal sampling circuit by constructing a virtual midpoint, and then the three-phase voltage can be sampled under a certain condition, and corresponding software processing is performed.
The A-phase circuit endpoint a is respectively connected with the first interleaving circuit and the second interleaving circuit through the three-phase EMC filter, the B-phase circuit endpoint B is respectively connected with the first interleaving circuit and the second interleaving circuit through the three-phase EMC filter, and the C-phase circuit endpoint C is respectively connected with the first interleaving circuit and the second interleaving circuit through the three-phase EMC filter.
The first interleaving circuit comprises a first A-phase power tube S a1 First B-phase power tube S b1 First C-phase power tube S c1 First A phase power tube S a1 The emitter of the A phase third diode Da3 and the anode of the A phase first diode Da1 are respectively connected, the cathode of the A phase first diode Da1 is connected with the anode of the A phase second diode Da2, and the cathode of the A phase second diode Da2 is respectively connected with the first A phase power tube S a1 A collector of the first B-phase power tube S and a cathode of the A-phase fourth diode Da4 b1 The emitter of the B-phase third diode Db3 and the anode of the B-phase first diode Db1 are respectively connected, the cathode of the B-phase first diode Db1 is connected with the anode of the B-phase second diode Db2, and the cathode of the B-phase second diode Db2 is respectively connected with the cathode of the B-phase fourth diode Db4 and the first B-phase power tube S b1 Collector of the first C-phase power tube S c1 The emitter of the C-phase third diode Dc3 and the anode of the C-phase first diode Dc1 are respectively connected, the cathode of the C-phase first diode Dc1 is connected with the anode of the C-phase second diode Dc2, and the cathode of the C-phase second diode Dc2 is respectively connected with the first C-phase power tube S c1 The collector of the third diode D3 of A phase, the cathode of the third diode D3 of B phase and the cathode of the third diode D3 of C phase are connected with the cathode of the first diode D1, the anode of the fourth diode D4 of A phase and the fourth diode of B phaseThe anodes of Db4 and C-phase fourth diode Dc4 are connected with the anode of first diode D1.
The phase A input end of the first interleaving circuit is arranged between the phase A first diode Da1 and the phase A second diode Da2, the phase B input end of the first interleaving circuit is arranged between the phase B first diode Db1 and the phase B second diode Db2, the phase C input end of the first interleaving circuit is arranged between the phase C first diode Dc1 and the phase C second diode Dc2, and the three-phase input voltage source is respectively connected with the phase A input end of the first interleaving circuit, the phase B input end of the first interleaving circuit and the phase C input end of the first interleaving circuit.
The A-phase circuit endpoint a is connected with the A-phase input end of the first interleaving circuit, the B-phase circuit endpoint B is connected with the B-phase input end of the first interleaving circuit, and the C-phase circuit endpoint C is connected with the C-phase input end of the first interleaving circuit. The A-phase circuit endpoint a is connected with the A-phase input end of the first interleaving circuit, the B-phase circuit endpoint B is connected with the B-phase input end of the first interleaving circuit, and the C-phase circuit endpoint C is connected with the C-phase input end of the first interleaving circuit.
The second interleaving circuit comprises a second A-phase power tube S a2 Second B-phase power tube S b2 Second C-phase power tube S c2 Second A-phase power tube S a2 The emitter of the diode is respectively connected with the anode of the A-phase seventh diode Da7 and the anode of the A-phase fifth diode Da5, the cathode of the A-phase fifth diode Da5 is connected with the anode of the A-phase sixth diode Da6, and the cathode of the A-phase sixth diode Da6 is respectively connected with the second A-phase power tube S a2 A collector of the eighth diode Da8 and a cathode of the eighth diode Da8, a second B-phase power tube S b2 The emitter of the B-phase seventh diode Db7 and the anode of the B-phase fifth diode Db5 are respectively connected, the cathode of the B-phase fifth diode Db5 is connected with the anode of the B-phase sixth diode Db6, and the cathode of the B-phase sixth diode Db6 is respectively connected with the cathode of the B-phase eighth diode Db8 and the second B-phase power tube S b2 Collector of the second C-phase power tube S c2 The emitter of the third diode Dc7 is connected with the anode of the third diode Dc7 and the anode of the fourth diode Dc5, the cathode of the third diode Dc5 is connected with the anode of the fourth diode Dc6, and the cathode of the fourth diode Dc6 is connected with the second C-phase power tube S c2 The collector of the eighth diode Dc8 in C phase, the cathode of the seventh diode Da7 in a phase, the cathode of the seventh diode Db7 in B phase and the cathode of the seventh diode Dc7 in C phase are all connected to the cathode of the second diode D2, and the anode of the eighth diode Da8 in a phase, the anode of the eighth diode Db8 in B phase and the anode of the eighth diode Dc8 in C phase are all connected to the anode of the second diode D2.
The a-phase input end of the second interleaving circuit is arranged between the a-phase fifth diode Da5 and the a-phase sixth diode Da6, the B-phase input end of the second interleaving circuit is arranged between the B-phase fifth diode Db5 and the B-phase sixth diode Db6, and the C-phase input end of the second interleaving circuit is arranged between the C-phase fifth diode Dc5 and the C-phase sixth diode Dc 6.
The A phase circuit endpoint a is connected with the A phase input end of the second interleaving circuit, the B phase circuit endpoint B is connected with the B phase input end of the second interleaving circuit, and the C phase circuit endpoint C is connected with the C phase input end of the second interleaving circuit. The A phase circuit endpoint a is connected with the A phase input end of the second interleaving circuit, the B phase circuit endpoint B is connected with the B phase input end of the second interleaving circuit, and the C phase circuit endpoint C is connected with the C phase input end of the second interleaving circuit.
The first output end of the first interleaving circuit is connected with the cathode of the first diode D1, the second output end of the first interleaving circuit is connected with the anode of the first diode D1, the third output end of the second interleaving circuit is connected with the cathode of the second diode D2, and the fourth output end of the second interleaving circuit is connected with the anode of the second diode D2.
The first output end of the first interleaving circuit is connected with one end of a first inductor L1, the second output end of the first interleaving circuit is respectively connected with the fourth output end of the second interleaving circuit and the other end of a first capacitor C1, the third output end of the second interleaving circuit is connected with one end of a second inductor L2, the other end of the first inductor L1 is respectively connected with the other end of the second inductor L2 and one end of the first capacitor C1, and the two ends of the first capacitor C1 are direct-current voltage V BUS 。
The first capacitor C1 is a filter capacitor. The first inductor L1 and the second inductor L2 are both buck inductors.
Three-phase staggered parallel connection buck PThe control method of the FC circuit is shown in fig. 2, and comprises a PFC circuit and a main controller, wherein the main controller comprises a first PID regulator, a second PID regulator, a third PID regulator, a feedforward controller and a phase-locked loop calculation module; the voltage ring collects direct current voltage V BUS And a given DC voltageThe signal is used for sending the difference signal calculated by the signal and the signal to the first PID regulator; the first PID regulator receives the difference signal and outputs an inductor current reference value i * Signal to the first current loop and the second current loop; the first current loop collects a first interleaved circuit inductance current feedback value i of the PFC circuit 1 The signal, the first current loop receives the inductance current reference value i * The signal and the difference signal calculated by the signal and the difference signal are sent to a second PID regulator; the second current loop collects a second interleaved circuit inductance current feedback value i of the PFC circuit 2 The second current loop receives the inductor current reference value i * The signal and the difference signal calculated by the signal and the difference signal are sent to a third PID regulator; the second PID regulator receives the signal of the first current loop and the phase angle sin (theta) and cos (theta) signals of the power grid voltage, and outputs a first loop output value out signal to the feedforward controller after operation; the third PID regulator receives the signal of the second current loop and the phase angle sin (theta) and cos (theta) signals of the power grid voltage, and outputs a second loop output value out2 signal to the feedforward controller after operation; the feedforward controller outputs a first duty ratio control amount duty1 signal and a second duty ratio control amount duty2 signal to a PWM signal generating module through operation, and the PWM signal generating module outputs a PWM control signal PWM (S) a1 ，S b1 ，S c1 ) To the first A-phase power tube S a1 First B-phase power tube S b1 First C-phase power tube S c1 Output PWM (S) a2 ，S b2 ，S c2 ) To the second A-phase power tube S a2 Second B-phase power tube S b2 Second C-phase power tube S c2 。
The control step of the three-phase staggered parallel buck PFC circuit comprises the following steps:
s1, sampling power grid voltage and calculating a phase-locked loop: the main controller collects the voltage of the three-phase input voltage source, tracks the phase of the power grid voltage (namely a phase-locked loop (SPLL)), and simultaneously calculates the phase-locked loop to obtain accurate phase angles sin (theta) and cos (theta) of the power grid voltage.
The phase-locked loop has a calculation formula of
And
calculating v twice before and after q Is a difference Deltav of (a) q =last v q Value-this time v q A value;
by continuously adjusting the angle value theta to enable v q After the value is 0, the phase lock is ended.
S2, capacitor voltage outer ring control: the main controller collects the DC voltage VBUS and the given DC voltageComparing, performing PID control operation on the difference value of the two to obtain an inductance current reference value i * The method comprises the steps of carrying out a first treatment on the surface of the The capacitor voltage outer ring has the function of stabilizing the direct current bus voltage (namely, the capacitor voltage).
S3, inductance current inner loop control: the main controller inputs the inductance current reference value i * And a first interleaved circuit inductor current feedback value i 1 The difference value is subjected to PID control operation to obtain a first loop output value out1; input the second interleaving circuit inductance current feedback value i 2 Which is related to the inductor current reference i * And (2) performing PID control operation on the difference value of the first loop output value out2.
In step S2 and step S3, the capacitor voltage outer loop control and the inductor voltage inner loop control are both PID control, and the operation formula of the PID control is as followsWherein,,
e k inputting error amount for the time;
e k-1 for the last error input, the software records to obtain the value;
e k-2 for the last error input, the software records to obtain the value;
u k the output value is the PID operation;
u k-1 the software records this value for the output value of the last PID operation.
K p ，Tuning parameters are required for PID control.
S4, feedforward control: and the main controller carries out feedforward control operation on the phase angles sin (theta) and cos (theta), the first loop output value out1 and the first loop output value out2 of the power grid voltage according to a certain theory to obtain a first duty ratio control quantity duty1 and a second duty ratio control quantity duty2.
The feedforward control formula is that
Wherein duty1 is a first duty control amount;
V BUS the current bus voltage value;
V N is a power grid module value;
V max the instantaneous maximum value of the power grid can be obtained according to the phase angles sin (theta) and cos (theta) of the power grid voltage;
out1 is the PID regulator output value.
S5, generating PWM control signals in an interleaving and parallel mode: the main controller performs PWM modulation on the first and second duty control amounts duty1 and duty2 to generate a PWM control signal PWM (S) a1 ，S b1 ，S c1 ) And PWM (S) a2 ，S b2 ，S c2 ) For controlling the first A-phase power tube S a1 First B-phase power tube S b1 First C-phase power tube S c1 Second A-phase power tube S a2 Second B-phase power tube S b2 Second C-phase power tube S c2 。
As shown in fig. 3 and 4, the power grid is divided into 6 sectors, and the duty ratio of the power tube corresponding to each sector is different.
As shown in fig. 5 and 6, the power tube of the duty ratio power tube response of each path is finally obtained. The first A-phase power tube Sa1 of the first interleaving circuit and the second A-phase power tube Sa2 of the second interleaving circuit are subjected to 180-degree duty cycle control, the first B-phase power tube Sb1 of the first interleaving circuit and the second B-phase power tube Sb2 of the second interleaving circuit are subjected to 180-degree duty cycle control, and the first C-phase power tube Sc1 of the first interleaving circuit and the second C-phase power tube Sc2 of the second interleaving circuit are subjected to 180-degree duty cycle control.
Compared with the traditional three-phase boosting PFC circuit, the invention has the beneficial effects that:
1. the requirement on the voltage resistance of the capacitor is low, and the volume of the capacitor is small;
2. the low-voltage high-current rear stage DC/DC design is easy;
3. short-circuit protection is easy to realize, and reliability is higher.
Compared with the traditional three-phase buck PFC circuit, the invention has the beneficial effects that:
1. under the condition of unchanged voltage ripple, the capacitor and the volume of the capacitor are small, the capacity requirement of a switching tube monomer is small, and the inductive power is low, so that the volume of the power supply can be further reduced;
2. under the condition that the capacitance of the capacitor is unchanged, the ripple wave is reduced after the capacitor is connected in parallel in a staggered way,
3. the current harmonic wave of the power grid is reduced, the inductance ripple is small, and the frequency of the inductance current is doubled;
4. the load can be directly driven to start.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (6)

1. A three-phase staggered parallel buck PFC circuit is characterized in that,
comprises a three-phase input voltage source, a three-phase EMC filter, a virtual midpoint capacitor, an interleaving parallel circuit and a step-down filter circuit,
the interleaved parallel circuit connects the buck filter circuits,
the three-phase input voltage source is connected with the staggered parallel circuit through the three-phase EMC filter and the virtual midpoint capacitor in sequence,
the staggered parallel circuit comprises a first staggered circuit and a second staggered circuit, wherein the first staggered circuit comprises a first A-phase power tube S a1 First B-phase power tube S b1 First C-phase power tube S c1 ，
The first A-phase power tube S a1 The emitter of the A phase third diode Da3 and the anode of the A phase first diode Da1 are respectively connected, the cathode of the A phase first diode Da1 is connected with the anode of the A phase second diode Da2, and the cathode of the A phase second diode Da2 is respectively connected with the first A phase power tube S a1 And the cathode of the a-phase fourth diode Da4,
the first B-phase power tube S b1 The emitters of the B-phase third diode Db3 and the B-phase first diode Db1 are respectively connected, the cathode of the B-phase first diode Db1 is connected with the anode of the B-phase second diode Db2, and the cathode of the B-phase second diode Db2 is respectively connected with the cathode of the B-phase fourth diode Db4 and the first B-phase power tube S b1 Is provided with a collector electrode of the (c),
the first C-phase power tube S c1 The emitters of the C-phase third diode Dc3 and the C-phase first diode Dc1 are respectively connected, the cathode of the C-phase first diode Dc1 is connected with the anode of the C-phase second diode Dc2, and the cathode of the C-phase second diode Dc2 is respectively connected with the first C-phase power tube S c1 And the collector of the C-phase fourth diode Dc4,
the cathode of the A-phase third diode Da3, the cathode of the B-phase third diode Db3 and the cathode of the C-phase third diode Dc3 are all connected with the cathode of the first diode D1, the anode of the A-phase fourth diode Da4, the anode of the B-phase fourth diode Db4 and the anode of the C-phase fourth diode Dc4 are all connected with the anode of the first diode D1,
the second interleaving circuit comprises a second A-phase power tube S a2 Second B-phase power tube S b2 Second C-phase power tube S c2 ，
Second A-phase power tube S a2 The emitter of the diode is respectively connected with the anode of the A-phase seventh diode Da7 and the anode of the A-phase fifth diode Da5, the cathode of the A-phase fifth diode Da5 is connected with the anode of the A-phase sixth diode Da6, and the cathode of the A-phase sixth diode Da6 is respectively connected with the second A-phase power tube S a2 And the cathode of the eighth diode Da8 of phase a,
second B-phase power tube S b2 The emitter of the B-phase seventh diode Db7 and the anode of the B-phase fifth diode Db5 are respectively connected, the cathode of the B-phase fifth diode Db5 is connected with the anode of the B-phase sixth diode Db6, and the cathode of the B-phase sixth diode Db6 is respectively connected with the cathode of the B-phase eighth diode Db8 and the second B-phase power tube S b2 Is provided with a collector electrode of the (c),
second C-phase power tube S c2 The emitter of the third diode Dc7 is connected with the anode of the third diode Dc7 and the anode of the fourth diode Dc5, the cathode of the third diode Dc5 is connected with the anode of the fourth diode Dc6, and the cathode of the fourth diode Dc6 is connected with the second C-phase power tube S c2 And the collector of the C-phase eighth diode Dc8,
the cathode of the A-phase seventh diode Da7, the cathode of the B-phase seventh diode Db7 and the cathode of the C-phase seventh diode Dc7 are all connected with the cathode of the second diode D2, the anode of the A-phase eighth diode Da8, the anode of the B-phase eighth diode Db8 and the anode of the C-phase eighth diode Dc8 are all connected with the anode of the second diode D2,
first A-phase power tube S of first interleaving circuit a1 And a second A-phase power tube S of a second interleaving circuit a2 First B-phase power tube S of first interleaving circuit for controlling 180-degree duty ratio b1 And a second B-phase power tube S of a second interleaving circuit b2 First C-phase power tube S of first interleaving circuit for interleaving 180-degree duty cycle control c1 And (d)Second C-phase power tube S of two interleaving circuits c2 The 180 deg. duty cycle control is staggered,
the first interleaving circuit is connected in parallel with the second interleaving circuit,
the control step of the three-phase staggered parallel buck PFC circuit comprises the following steps:
s1, sampling the voltage of a power grid and calculating a phase-locked loop,
s2, performing capacitor voltage outer loop control,
s3, performing inductive current inner loop control,
s4, feedforward control is carried out, and a feedforward control formula is as follows
Wherein,,
duty1 is a first duty control amount;
V BUS the current bus voltage value;
V N is a power grid module value;
V max the instantaneous maximum value of the power grid can be obtained according to the phase angles sin (theta) and cos (theta) of the power grid voltage;
out1 is the output value of the PID regulator,
s5, generating PWM control signals in an interleaving parallel mode.
2. The three-phase interleaved parallel buck PFC circuit according to claim 1 wherein the a-phase input of the first interleaved circuit is disposed between the a-phase first diode Da1 and the a-phase second diode Da2, the B-phase input of the first interleaved circuit is disposed between the B-phase first diode Db1 and the B-phase second diode Db2, the C-phase input of the first interleaved circuit is disposed between the C-phase first diode Dc1 and the C-phase second diode Dc2, and the three-phase input voltage source is connected to the a-phase input of the first interleaved circuit, the B-phase input of the first interleaved circuit, and the C-phase input of the first interleaved circuit, respectively.
3. The three-phase interleaved parallel buck PFC circuit according to claim 1 wherein the a-phase input of the second interleaved circuit is disposed between the a-phase fifth diode Da5 and the a-phase sixth diode Da6, the B-phase input of the second interleaved circuit is disposed between the B-phase fifth diode Db5 and the B-phase sixth diode Db6, the C-phase input of the second interleaved circuit is disposed between the C-phase fifth diode Dc5 and the C-phase sixth diode Dc6, and the three-phase input voltage source is connected to the a-phase input of the second interleaved circuit, the B-phase input of the second interleaved circuit, and the C-phase input of the second interleaved circuit, respectively.
4. The three-phase interleaved parallel buck PFC circuit according to claim 1 wherein a first output terminal of the first interleaved circuit is connected to one end of a first inductor L1, a second output terminal of the first interleaved circuit is connected to a fourth output terminal of the second interleaved circuit and the other end of the first capacitor C1, a third output terminal of the second interleaved circuit is connected to one end of a second inductor L2, and the other end of the first inductor L1 is connected to the other end of the second inductor L2 and one end of the first capacitor C1, respectively.
5. The three-phase interleaved buck PFC circuit according to claim 1 wherein the power grid is divided into 6 sectors, each of which has a different duty cycle of the power tube.
6. The three-phase interleaved buck PFC circuit according to claim 1, comprising a PFC circuit, a main controller, a PWM signal generation module, and a phase-locked loop calculation module, wherein the main controller includes a first PID regulator, a second PID regulator, a third PID regulator, and a feedforward controller, the first PID regulator is connected to the PFC circuit, the first PID regulator is connected to the second PID regulator and the third PID regulator, respectively, and the feedforward controller is connected to the phase-locked loop calculation module, the second PID regulator, and the third PID regulator, respectively, and the PWM signal generation module is connected to the feedforward controller.
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