CN111181376A - Three-phase interleaved parallel buck PFC circuit and control method thereof - Google Patents

Three-phase interleaved parallel buck PFC circuit and control method thereof Download PDF

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CN111181376A
CN111181376A CN201911337631.1A CN201911337631A CN111181376A CN 111181376 A CN111181376 A CN 111181376A CN 201911337631 A CN201911337631 A CN 201911337631A CN 111181376 A CN111181376 A CN 111181376A
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phase
diode
circuit
interleaved
anode
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CN111181376B (en
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莫汉岐
吕志明
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Shenzhen Vapel Power Supply Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4216—Arrangements for improving power factor of AC input operating from a three-phase input voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4291—Arrangements for improving power factor of AC input by using a Buck converter to switch the input current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a three-phase interleaved parallel buck PFC circuit and a control method, wherein the three-phase interleaved parallel buck PFC circuit uses an interleaved parallel circuit, is provided with a buck inductor and a filter capacitor, carries out PID (proportion integration differentiation) control on a capacitor voltage outer ring and an inductor current inner ring through a main controller, and simultaneously carries out feedforward control operation to obtain a PWM (pulse width modulation) control signal to control a switching tube, so that the volumes of the capacitor and the inductor of the circuit are reduced, the single capacity requirement of the switching tube is small, the current harmonic wave of a power grid is reduced, the cost is reduced, and the power factor of the power grid is improved.

Description

Three-phase interleaved parallel buck PFC circuit and control method thereof
Technical Field
The invention relates to the technical field of electronic power, in particular to a three-phase staggered parallel buck PFC circuit and a control method thereof.
Background
The uncontrollable rectification source adopted in part of rectification links of the power grid injects a large amount of current harmonic waves into the power grid, so that the power factor of the power grid is reduced. The three-phase buck PFC technology has the advantages of controllable power factor, voltage reduction, small current harmonic wave, easy realization of short-circuit protection and the like, and has considerable advantages in occasions with small power supply volume requirements, particularly in the aerospace field.
The traditional three-phase buck PFC circuit is large in capacitor and inductor volume, high in requirement on voltage resistance of the capacitor, large in demand on capacity of a single switching tube, poor in current harmonic of a power grid and high in system cost.
The above disadvantages need to be improved.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a three-phase interleaved parallel buck PFC circuit and a control method thereof.
The technical scheme of the invention is as follows:
a three-phase cross-parallel buck PFC circuit,
comprises a three-phase input voltage source, a three-phase EMC filter, a virtual midpoint capacitor, an interleaved parallel circuit and a step-down filter circuit,
the interleaved parallel circuit is connected with the voltage reduction filter circuit,
the three-phase input voltage source is connected with the interleaved parallel circuit through the three-phase EMC filter and the virtual midpoint capacitor in sequence,
the interleaved parallel circuit includes a first interleaved circuit and a second interleaved circuit,
the first interleaving circuit is connected in parallel with the second interleaving circuit.
According to the three-phase staggered parallel buck PFC circuit, the three-phase input voltage source comprises three alternating current power supplies Va, Vb and Vc which are mutually connected in parallel, the alternating current power supply Va is connected with the A-phase circuit end point a, the alternating current power supply Vb is connected with the B-phase circuit end point B, and the alternating current power supply Vc is connected with the C-phase circuit end point C.
In the three-phase interleaved buck-type PFC circuit, the virtual midpoint capacitor includes an a-phase capacitor Ca, a B-phase capacitor Cb, and a C-phase capacitor Cc, and the a-phase capacitor Ca, the B-phase capacitor Cb, and the C-phase capacitor Cc are connected in parallel.
Furthermore, one end of the phase a capacitor Ca is connected to the phase a circuit terminal a, one end of the phase B capacitor Cb is connected to the phase B circuit terminal B, one end of the phase C capacitor Cc is connected to the phase C circuit terminal C, and the other end of the phase a capacitor Ca, the other end of the phase B capacitor Cb, and the other end of the phase C capacitor Cc are connected to each other.
In the three-phase interleaved buck PFC circuit, the A-phase circuit end point a is respectively connected with the first interleaved circuit and the second interleaved circuit, the B-phase circuit end point B is respectively connected with the first interleaved circuit and the second interleaved circuit, and the C-phase circuit end point C is respectively connected with the first interleaved circuit and the second interleaved circuit.
The three-phase interleaved buck PFC circuit,
the first interleaving circuit comprises a first A-phase power tube Sa1First B phase power tube Sb1And a first C-phase power tube Sc1，
First A-phase power tube Sa1Respectively connected to the anode of the a-phase third diode Da3 and the anode of the a-phase first diode Da1,
the cathode of the a-phase first diode Da1 is connected to the anode of the a-phase second diode Da2,
the cathodes of the A-phase second diodes Da2 are respectively connected with the first A-phase power tube Sa1And the cathode of the phase a fourth diode Da4,
first B-phase power tube Sb1Respectively connected to the anode of the B-phase third diode Db3 and the anode of the B-phase first diode Db1,
the cathode of the B-phase first diode Db1 is connected to the anode of the B-phase second diode Db2,
the cathode of the B-phase second diode Db2 is connected to the cathode of the B-phase fourth diode Db4 and the first B-phase power tube Sb1The collector electrode of (a) is provided,
first C-phase power tube Sc1Respectively connected to the anode of the C-phase third diode Dc3 and the anode of the C-phase first diode Dc1,
the cathode of the C-phase first diode Dc1 is connected to the anode of the C-phase second diode Dc2,
the cathodes of the C-phase second diodes Dc2 are respectively connected with the first C-phase power tube Sc1And the cathode of the C-phase fourth diode Dc4,
the cathode of the a-phase third diode Da3, the cathode of the B-phase third diode Db3, and the cathode of the C-phase third diode Dc3 are connected to the cathode of the first diode D1,
an anode of the a-phase fourth diode Da4, an anode of the B-phase fourth diode Db4, and an anode of the C-phase fourth diode Dc4 are connected to an anode of the first diode D1.
Furthermore, a phase-A circuit terminal a is connected with a phase-A input end of the first interleaving circuit, a phase-B circuit terminal B is connected with a phase-B input end of the first interleaving circuit, and a phase-C circuit terminal C is connected with a phase-C input end of the first interleaving circuit.
Further, an a-phase input terminal of the first interleaving circuit is disposed between the a-phase first diode Da1 and the a-phase second diode Da2, a B-phase input terminal of the first interleaving circuit is disposed between the B-phase first diode Db1 and the B-phase second diode Db2, a C-phase input terminal of the first interleaving circuit is disposed between the C-phase first diode Dc1 and the C-phase second diode Dc2, and the three-phase input voltage sources are respectively connected to the a-phase input terminal of the first interleaving circuit, the B-phase input terminal of the first interleaving circuit, and the C-phase input terminal of the first interleaving circuit.
The three-phase interleaved buck PFC circuit,
the second interleaving circuit comprises a second A-phase power tube Sa2And a second B-phase power tube Sb2And a second C-phase power tube Sc2，
Second A-phase power tube Sa2Respectively connected to the anode of the a-phase seventh diode Da7 and the anode of the a-phase fifth diode Da5,
the cathode of the a-phase fifth diode Da5 is connected to the anode of the a-phase sixth diode Da6,
the cathodes of the A-phase sixth diodes Da6 are respectively connected with the second A-phase power tube Sa2And the cathode of the phase a eighth diode Da8,
second B-phase power tube Sb2Respectively connected to the anode of the B-phase seventh diode Db7 and the anode of the B-phase fifth diode Db5,
the cathode of the B-phase fifth diode Db5 is connected to the anode of the B-phase sixth diode Db6,
sixth dipole of B phaseThe cathode of the tube Db6 is connected to the cathode of the B-phase eighth diode Db8 and the second B-phase power tube Sb2The collector electrode of (a) is provided,
second C-phase power tube Sc2Respectively connected to the anode of the C-phase seventh diode Dc7 and the anode of the C-phase fifth diode Dc5,
the cathode of the C-phase fifth diode Dc5 is connected to the anode of the C-phase sixth diode Dc6,
the cathodes of the C-phase sixth diodes Dc6 are respectively connected with the second C-phase power tube Sc2And the cathode of the C-phase eighth diode Dc8,
the cathode of the a-phase seventh diode Da7, the cathode of the B-phase seventh diode Db7, and the cathode of the C-phase seventh diode Dc7 are connected to the cathode of the second diode D2,
an anode of the a-phase eighth diode Da8, an anode of the B-phase eighth diode Db8, and an anode of the C-phase eighth diode Dc8 are connected to an anode of the second diode D2.
Furthermore, a phase-A circuit terminal a is connected with a phase-A input end of the second interleaving circuit, a phase-B circuit terminal B is connected with a phase-B input end of the second interleaving circuit, and a phase-C circuit terminal C is connected with a phase-C input end of the second interleaving circuit.
Further, an a-phase input terminal of the second interleaving circuit is disposed between the a-phase fifth diode Da5 and the a-phase sixth diode Da6, a B-phase input terminal of the second interleaving circuit is disposed between the B-phase fifth diode Db5 and the B-phase sixth diode Db6, a C-phase input terminal of the second interleaving circuit is disposed between the C-phase fifth diode Dc5 and the C-phase sixth diode Dc6, and the three-phase input voltage sources are respectively connected to the a-phase input terminal of the second interleaving circuit, the B-phase input terminal of the second interleaving circuit, and the C-phase input terminal of the second interleaving circuit.
In the three-phase interleaved buck PFC circuit, the first output terminal of the first interleaved circuit is connected to the cathode of the first diode D1, the second output terminal of the first interleaved circuit is connected to the anode of the first diode D1, the third output terminal of the second interleaved circuit is connected to the cathode of the second diode D2, and the fourth output terminal of the second interleaved circuit is connected to the anode of the second diode D2.
In the three-phase interleaved buck PFC circuit, a first output end of the first interleaved circuit is connected to one end of a first inductor L1, a second output end of the first interleaved circuit is connected to a fourth output end of the second interleaved circuit and the other end of a first capacitor C1, a third output end of the second interleaved circuit is connected to one end of a second inductor L2, the other end of the first inductor L1 is connected to the other end of the second inductor L2 and one end of a first capacitor C1, and two ends of a first capacitor C1 are dc voltages V1BUS。
Further, the first capacitor C1 is a filter capacitor.
Further, the first inductor L1 and the second inductor L2 are both step-down inductors.
A control method of a three-phase interleaved parallel buck PFC circuit comprises the following steps:
s1, sampling the voltage of a power grid and calculating a phase-locked loop: collecting the voltage of a three-phase input voltage source, performing phase-locked loop calculation on the power grid voltage to obtain phase angles sin (theta) and cos (theta) of the power grid voltage,
s2, controlling a capacitor voltage outer ring: collecting DC voltage VBUSWith a given DC voltage
Figure BDA0002331368930000061
Comparing, and carrying out PID control operation on the difference value of the two values to obtain an inductive current reference value i*，
S3, inductive current inner loop control: input inductor current reference value i*And a first interleaved circuit inductor current feedback value i1Carrying out PID control operation on the difference value to obtain a first loop output value out 1; inputting the feedback value i of the inductive current of the second interleaving circuit2Which is related to the inductor current reference value i*Performs PID control operation to obtain a second loop output value out2,
s4, feedforward control: the phase angles sin (theta) and cos (theta) of the power grid voltage, the first loop output value out1 and the first loop output value out2 are subjected to feedforward control operation to obtain a first duty ratio control quantity 1 and a second duty ratio control quantity 2,
s5, generating PWM control signals in a staggered parallel mode: PWM-modulating the first duty1 and the second duty2 to generate a PWM control signal PWM (S)a1，Sb1，Sc1) And PWM (S)a2，Sb2，Sc2)。
The control method of the three-phase interleaved parallel buck PFC circuit comprises the PFC circuit, a main controller, a PWM signal generation module and a phase-locked loop calculation module, wherein the main controller comprises a first PID regulator, a second PID regulator, a third PID regulator and a feedforward controller, the first PID regulator is connected with the PFC circuit, the first PID regulator is respectively connected with the second PID regulator and the third PID regulator, the feedforward controller is respectively connected with the phase-locked loop calculation module, the second PID regulator and the third PID regulator, and the PWM signal generation module is connected with the feedforward controller.
The control method of the three-phase interleaved parallel buck PFC circuit comprises the PFC circuit and a main controller, wherein the main controller comprises a first PID regulator, a second PID regulator, a third PID regulator, a feedforward controller and a phase-locked loop calculation module; voltage ring acquisition direct-current voltage VBUSAnd a given DC voltage
Figure BDA0002331368930000062
The signal is used for sending a difference signal obtained by the operation of the signal and the reference signal to a first PID regulator; the first PID regulator receives the difference signal and outputs an inductive current reference value i*Signals to the first current loop and the second current loop; the first current loop acquires a first interleaved circuit inductive current feedback value i of the PFC circuit1A signal, the first current loop receiving an inductor current reference value i*The signal and the difference signal calculated by the two are sent to a second PID regulator; the second current loop acquires a second interleaved circuit inductive current feedback value i of the PFC circuit2Said second current loop receiving an inductor current reference value i*The difference signal of the two operations is sent to the secondThree PID regulators; the second PID regulator receives the signal of the first current loop and the phase angle sin (theta) and cos (theta) signals of the power grid voltage, and outputs a first loop output value out1 signal to the feedforward controller after operation; the third PID regulator receives a signal of a second current loop and phase angle sin (theta) and cos (theta) signals of the power grid voltage, and outputs a second loop output value out2 signal to the feedforward controller after operation; the feedforward controller outputs a first duty control amount duty1 signal and a second duty control amount duty2 signal to the PWM signal generation module through operation, and the PWM signal generation module outputs a PWM control signal PWM (S)a1，Sb1，Sc1) To the first A phase power tube Sa1First B phase power tube Sb1And a first C-phase power tube Sc1Output PWM (S)a2，Sb2，Sc2) To a second A-phase power tube Sa2And a second B-phase power tube Sb2And a second C-phase power tube Sc2。
According to the control method of the three-phase staggered parallel buck PFC circuit, a power grid is divided into 6 sectors, and the duty ratios of power tubes corresponding to the sectors are different.
In the control method of the three-phase interleaved buck PFC circuit, the A-phase power tube S of the first interleaved circuita1And a phase power tube S of the second interleaving circuita2Staggered by 180 degrees, and the B-phase power tube S of the first staggered circuitb1B phase power tube S of the second interleaving circuitb2Staggered by 180 degrees, and the C-phase power tube S of the first staggered circuitc1C-phase power tube S of the second interleaving circuitc2Staggered 180 degrees.
In the above control method for three-phase interleaved buck PFC circuit, in steps S2 and S3, the capacitor voltage outer loop control and the inductor voltage inner loop control both adopt PID control, and the PID control operation formula is
Figure BDA0002331368930000071
Wherein the content of the first and second substances,
ekinputting the error amount of the current time;
ek-1the software records the value for the last error input;
ek-2for the last error input, the software records and obtains the value;
ukthe output value of the PID operation is obtained;
uk-1the software records the output value of the last PID operation.
Figure BDA0002331368930000081
And controlling parameters needing to be adjusted for PID.
In step S4, the feedforward control formula of the control method for the three-phase interleaved buck PFC circuit is as follows
Figure BDA0002331368930000082
Wherein the content of the first and second substances,
VBUSthe current bus voltage value is obtained;
VNthe power grid module value is obtained;
Vmaxthe instantaneous maximum value of the power grid can be obtained according to the phase angle sin theta (theta) and cos (theta) of the power grid voltage;
out1 is the PID output value.
The control method of the three-phase interleaved buck PFC circuit,
in step S1, the phase-locked loop is calculated as
Figure BDA0002331368930000083
And
Figure BDA0002331368930000084
twice before and after the calculation of vqDifference value Δ v of (1)qLast time vqValue-this time vqA value;
by continuously adjusting the angle value theta so that v isqAfter the value is 0, the phase locking is finished.
The invention according to the above scheme has the advantages that,
compared with the traditional three-phase boost PFC circuit, the invention has the beneficial effects that:
1. the requirement on the voltage resistance of the capacitor is low, and the volume of the capacitor is small;
2. the design of low-voltage large-current post-stage DC/DC is easy;
3. the short-circuit protection is easy to realize, and the reliability is higher.
Compared with the traditional three-phase buck PFC circuit, the buck PFC circuit has the beneficial effects that:
1. under the condition that the voltage ripple is not changed, the size of the capacitor and the capacitor is small, the capacity requirement of the single switch tube is small, and the inductive power is low, so that the size of the power supply can be further reduced;
2. under the condition that the capacity of the capacitor is not changed, the ripple of the capacitor is reduced after the capacitors are connected in parallel in a staggered way,
3. the current harmonic wave of the power grid is reduced, the inductance ripple is small, and the frequency of the inductance current is doubled;
4. the load can be directly driven to start.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic diagram of a three-phase interleaved buck PFC circuit;
FIG. 2 is a flow chart of a control method of a three-phase interleaved buck PFC circuit;
FIG. 3 is a schematic diagram of a voltage waveform and a working mode analysis point of a three-phase power grid;
FIG. 4 is a schematic diagram of a space voltage vector distribution of an interleaved parallel three-phase buck PFC;
FIG. 5 is a diagram of a switch state analysis of sector 1 of FIG. 4;
fig. 6 is a diagram of a switch state analysis of sector 2 in fig. 4.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly or indirectly connected to the other element. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features.
A three-phase interleaved parallel buck PFC circuit is shown in figure 1 and comprises a three-phase input voltage source, a three-phase EMC filter, a virtual midpoint capacitor, an interleaved parallel circuit and a buck filter circuit, wherein the interleaved parallel circuit is connected with the buck filter circuit, the three-phase input voltage source is connected with the interleaved parallel circuit through the three-phase EMC filter and the virtual midpoint capacitor in sequence, the interleaved parallel circuit comprises a first interleaved circuit and a second interleaved circuit, and the first interleaved circuit is connected with the second interleaved circuit in parallel. The three-phase EMC filter is arranged on the EMC board, the virtual midpoint capacitor is arranged on the power board, and the EMC board and the power board are both areas on the PCB.
The three-phase input voltage source comprises three alternating current power supplies Va, Vb and Vc which are connected in parallel, wherein the alternating current power supply Va is connected with an A-phase circuit end point a, the alternating current power supply Vb is connected with a B-phase circuit end point B, and the alternating current power supply Vc is connected with a C-phase circuit end point C.
The three-phase filter carries out secondary filtering on a high-frequency signal generated by the power tube, and filters out a high-frequency part, so that three-phase current becomes power frequency current, high-frequency harmonic interference is not injected into a power grid, and electromagnetic interference generated by the circuit is limited within a certain range. The three-phase filter can also filter high-frequency harmonic parts contained in the three-phase input voltage source, so that the normal operation of the circuit is not influenced.
The virtual midpoint capacitor comprises an A-phase capacitor Ca, a B-phase capacitor Cb and a C-phase capacitor Cc, wherein the A-phase capacitor Ca, the B-phase capacitor Cb and the C-phase capacitor Cc are mutually connected in parallel. One end of the A-phase capacitor Ca is connected with an A-phase circuit endpoint a through a three-phase EMC filter, one end of the B-phase capacitor Cb is connected with a B-phase circuit endpoint B through a three-phase EMC filter, one end of the C-phase capacitor Cc is connected with a C-phase circuit endpoint C through a three-phase EMC filter, and the other end of the A-phase capacitor Ca, the other end of the B-phase capacitor Cb and the other end of the C-phase capacitor Cc are mutually connected. The virtual midpoint capacitor can filter the high-frequency signal generated by the power tube for the first time, and control the interference radiation in the power plate. In addition, because the three-phase input voltage source is a three-phase three-wire system, no zero line is connected into the circuit, three-phase voltage cannot be sampled inside the circuit, a virtual midpoint is constructed, a sampling reference point can be provided for an internal sampling circuit, and then the three-phase voltage can be sampled under a certain condition to perform corresponding software processing.
The A phase circuit terminal a is respectively connected with the first interleaving circuit and the second interleaving circuit through a three-phase EMC filter, the B phase circuit terminal B is respectively connected with the first interleaving circuit and the second interleaving circuit through a three-phase EMC filter, and the C phase circuit terminal C is respectively connected with the first interleaving circuit and the second interleaving circuit through a three-phase EMC filter.
The first interleaving circuit comprises a first A-phase power tube Sa1First B phase power tube Sb1And a first C-phase power tube Sc1First A phase power tube Sa1Respectively connected to the anode of the a-phase third diode Da3 and the anode of the a-phase first diode Da1, the cathode of the a-phase first diode Da1 is connected to the anode of the a-phase second diode Da2, and the cathode of the a-phase second diode Da2 is connected to the first a-phase power tube Sa1Collector of the first phase-B power transistor S, and cathode of the a-phase fourth diode Da4b1Respectively connected to the anode of the B-phase third diode Db3 and the anode of the B-phase first diode Db1, the cathode of the B-phase first diode Db1 is connected to the anode of the B-phase second diode Db2, and the cathode of the B-phase second diode Db2 is connected to the cathode of the B-phase fourth diode Db4 and the first B-phase power transistor Sb1The first C-phase power tube Sc1The emitting electrodes are respectively connected with the C phaseThe anode of the third diode Dc3 and the anode of the C-phase first diode Dc1, the cathode of the C-phase first diode Dc1 is connected with the anode of the C-phase second diode Dc2, and the cathodes of the C-phase second diode Dc2 are respectively connected with the first C-phase power tube Sc1The collector of (a) and the cathode of the C-phase fourth diode Dc4, the cathode of the a-phase third diode Da3, the cathode of the B-phase third diode Db3, and the cathode of the C-phase third diode Dc3 are all connected to the cathode of the first diode D1, and the anode of the a-phase fourth diode Da4, the anode of the B-phase fourth diode Db4, and the anode of the C-phase fourth diode Dc4 are all connected to the anode of the first diode D1.
An A-phase input end of the first interleaving circuit is arranged between the A-phase first diode Da1 and the A-phase second diode Da2, a B-phase input end of the first interleaving circuit is arranged between the B-phase first diode Db1 and the B-phase second diode Db2, a C-phase input end of the first interleaving circuit is arranged between the C-phase first diode Dc1 and the C-phase second diode Dc2, and three-phase input voltage sources are respectively connected with the A-phase input end of the first interleaving circuit, the B-phase input end of the first interleaving circuit and the C-phase input end of the first interleaving circuit.
The A-phase circuit terminal a is connected with the A-phase input end of the first interleaving circuit, the B-phase circuit terminal B is connected with the B-phase input end of the first interleaving circuit, and the C-phase circuit terminal C is connected with the C-phase input end of the first interleaving circuit. The A-phase circuit terminal a is connected with the A-phase input end of the first interleaving circuit, the B-phase circuit terminal B is connected with the B-phase input end of the first interleaving circuit, and the C-phase circuit terminal C is connected with the C-phase input end of the first interleaving circuit.
The second interleaving circuit comprises a second A-phase power tube Sa2And a second B-phase power tube Sb2And a second C-phase power tube Sc2Second A-phase power tube Sa2Respectively connected to the anode of the a-phase seventh diode Da7 and the anode of the a-phase fifth diode Da5, the cathode of the a-phase fifth diode Da5 is connected to the anode of the a-phase sixth diode Da6, and the cathode of the a-phase sixth diode Da6 is connected to the second a-phase power tube Sa2Collector of the second phase-a eighth diode Da8, and the second phase-B power tube Sb2Respectively connected to an anode of the B-phase seventh diode Db7 and an anode of the B-phase fifth diode Db5, the B-phase fifth diodeThe cathode of the tube Db5 is connected to the anode of the B-phase sixth diode Db6, and the cathode of the B-phase sixth diode Db6 is connected to the cathode of the B-phase eighth diode Db8 and the second B-phase power tube Sb2Collector electrode of the second C-phase power tube Sc2The emitters of the first and second diodes are respectively connected with the anode of the C-phase seventh diode Dc7 and the anode of the C-phase fifth diode Dc5, the cathode of the C-phase fifth diode Dc5 is connected with the anode of the C-phase sixth diode Dc6, and the cathode of the C-phase sixth diode Dc6 is respectively connected with the second C-phase power tube Sc2The collector of (a) and the cathode of the C-phase eighth diode Dc8, the cathode of the a-phase seventh diode Da7, the cathode of the B-phase seventh diode Db7, and the cathode of the C-phase seventh diode Dc7 are all connected to the cathode of the second diode D2, and the anode of the a-phase eighth diode Da8, the anode of the B-phase eighth diode Db8, and the anode of the C-phase eighth diode Dc8 are all connected to the anode of the second diode D2.
An a-phase input terminal of the second interleaving circuit is disposed between the a-phase fifth diode Da5 and the a-phase sixth diode Da6, a B-phase input terminal of the second interleaving circuit is disposed between the B-phase fifth diode Db5 and the B-phase sixth diode Db6, and a C-phase input terminal of the second interleaving circuit is disposed between the C-phase fifth diode Dc5 and the C-phase sixth diode Dc 6.
The A-phase circuit terminal a is connected with the A-phase input end of the second interleaving circuit, the B-phase circuit terminal B is connected with the B-phase input end of the second interleaving circuit, and the C-phase circuit terminal C is connected with the C-phase input end of the second interleaving circuit. The A-phase circuit terminal a is connected with the A-phase input end of the second interleaving circuit, the B-phase circuit terminal B is connected with the B-phase input end of the second interleaving circuit, and the C-phase circuit terminal C is connected with the C-phase input end of the second interleaving circuit.
The first output of the first interleaving circuit is connected to the cathode of a first diode D1, the second output of the first interleaving circuit is connected to the anode of a first diode D1, the third output of the second interleaving circuit is connected to the cathode of a second diode D2, and the fourth output of the second interleaving circuit is connected to the anode of a second diode D2.
The first output terminal of the first interleaving circuit is connected to one end of the first inductor L1, and the second output terminal of the first interleaving circuit is connected to the fourth output terminal of the second interleaving circuit and the first capacitor, respectivelyThe other end of the capacitor C1 is connected, the third output end of the second interleaving circuit is connected with one end of the second inductor L2, the other end of the first inductor L1 is connected with the other end of the second inductor L2 and one end of the first capacitor C1, and the two ends of the first capacitor C1 are direct-current voltage VBUS。
The first capacitor C1 is a filter capacitor. The first inductor L1 and the second inductor L2 are both step-down inductors.
A control method of a three-phase interleaved parallel buck PFC circuit is shown in figure 2 and comprises the PFC circuit and a main controller, wherein the main controller comprises a first PID regulator, a second PID regulator, a third PID regulator, a feedforward controller and a phase-locked loop calculation module; voltage ring acquisition direct-current voltage VBUSAnd a given DC voltage
Figure BDA0002331368930000131
The signal is used for sending a difference signal obtained by the operation of the signal and the reference signal to a first PID regulator; the first PID regulator receives the difference signal and outputs an inductive current reference value i*Signals to the first current loop and the second current loop; the first current loop acquires a first interleaved circuit inductive current feedback value i of the PFC circuit1A first current loop receiving an inductor current reference value i*The signal and the difference signal calculated by the two are sent to a second PID regulator; the second current loop acquires a second interleaved circuit inductive current feedback value i of the PFC circuit2The second current loop receives the inductor current reference value i*The signal and the difference signal calculated by the two are sent to a third PID regulator; the second PID regulator receives the signal of the first current loop and the phase angle sin (theta) and cos (theta) signals of the power grid voltage, and outputs a first loop output value out1 signal to the feedforward controller after operation; the third PID regulator receives the signal of the second current loop and the phase angle sin (theta) and cos (theta) signals of the power grid voltage, and outputs a second loop output value out2 signal to the feedforward controller after operation; the feedforward controller outputs a first duty control amount duty1 signal and a second duty control amount duty2 signal to the PWM signal generation module through operation, and the PWM signal generation module outputs a PWM control signal PWM (S)a1，Sb1，Sc1) To the first A phase power tube Sa1First B phase power tube Sb1And a first C-phase power tube Sc1Output PWM (S)a2，Sb2，Sc2) To a second A-phase power tube Sa2And a second B-phase power tube Sb2And a second C-phase power tube Sc2。
The method comprises the following steps:
s1, sampling the voltage of a power grid and calculating a phase-locked loop: the main controller collects the voltage of a three-phase input voltage source, tracks the phase of the power grid voltage (namely, a phase-locked loop SPLL), and calculates the phase-locked loop to obtain accurate phase angles sin (theta) and cos (theta) of the power grid voltage.
The phase-locked loop has the formula
Figure BDA0002331368930000141
And
Figure BDA0002331368930000142
twice before and after the calculation of vqDifference value Δ v of (1)qLast time vqValue-this time vqA value;
by continuously adjusting the angle value theta so that v isqAfter the value is 0, the phase locking is finished.
S2, controlling a capacitor voltage outer ring: the main controller collects the DC voltage VBUSWith a given DC voltage
Figure BDA0002331368930000143
Comparing, and carrying out PID control operation on the difference value of the two values to obtain an inductive current reference value i*(ii) a The capacitor voltage outer ring has the function of stabilizing the direct current bus voltage (namely the capacitor voltage).
S3, inductive current inner loop control: the main controller inputs an inductive current reference value i*And a first interleaved circuit inductor current feedback value i1Carrying out PID control operation on the difference value to obtain a first loop output value out 1; inputting the feedback value i of the inductive current of the second interleaving circuit2With an inductor current referenceValue i*And performs PID control operation to obtain a second loop output value out 2.
In steps S2 and S3, PID control is adopted for both the capacitor voltage outer loop control and the inductor voltage inner loop control, and the operation formula of the PID control is as follows
Figure BDA0002331368930000151
Wherein the content of the first and second substances,
ekinputting the error amount of the current time;
ek-1the software records the value for the last error input;
ek-2for the last error input, the software records and obtains the value;
ukthe output value of the PID operation is obtained;
uk-1the software records the output value of the last PID operation.
Figure BDA0002331368930000152
And controlling parameters needing to be adjusted for PID.
S4, feedforward control: the main controller performs feed-forward control operation on the phase angles sin (theta) and cos (theta) of the power grid voltage, the first loop output value out1 and the first loop output value out2 according to a certain theory to obtain a first duty ratio control quantity 1 and a second duty ratio control quantity 2.
The feed forward control formula is
Figure BDA0002331368930000153
Wherein the content of the first and second substances,
VBUSthe current bus voltage value is obtained;
VNthe power grid module value is obtained;
Vmaxthe instantaneous maximum value of the power grid can be obtained according to the phase angle sin (theta) and cos (theta) of the power grid voltage;
out1 is the PID output value.
S5, generating PWM control signals in a staggered parallel mode: the main controller controls the first duty ratio duty1 and the second duty2 perform PWM modulation to generate a PWM control signal PWM (S)a1，Sb1，Sc1) And PWM (S)a2，Sb2，Sc2) For controlling the first A-phase power transistor Sa1First B phase power tube Sb1A first C-phase power tube Sc1And a second A-phase power tube Sa2And a second B-phase power tube Sb2And a second C-phase power tube Sc2。
As shown in fig. 3 and 4, the power grid is divided into 6 sectors, and the duty ratios of the power tubes corresponding to the sectors are different.
As shown in fig. 5 and 6, the power tubes with duty ratio power tube responses of each path are obtained finally. A-phase power tube S of first interleaving circuita1And a phase A power tube S of the second interleaving circuita2Stagger 180 degrees, the B phase power tube S of the first stagger circuitb1B phase power tube S of second interleaving circuitb2Stagger 180 degrees, the C phase power tube S of the first staggered circuitc1C-phase power tube S of second interleaving circuitc2Staggered 180 degrees.
Compared with the traditional three-phase boost PFC circuit, the invention has the beneficial effects that:
1. the requirement on the voltage resistance of the capacitor is low, and the volume of the capacitor is small;
2. the design of low-voltage large-current post-stage DC/DC is easy;
3. the short-circuit protection is easy to realize, and the reliability is higher.
Compared with the traditional three-phase buck PFC circuit, the buck PFC circuit has the beneficial effects that:
1. under the condition that the voltage ripple is not changed, the size of the capacitor and the capacitor is small, the capacity requirement of the single switch tube is small, and the inductive power is low, so that the size of the power supply can be further reduced;
2. under the condition that the capacity of the capacitor is not changed, the ripple of the capacitor is reduced after the capacitors are connected in parallel in a staggered way,
3. the current harmonic wave of the power grid is reduced, the inductance ripple is small, and the frequency of the inductance current is doubled;
4. the load can be directly driven to start.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (10)

1. A three-phase interleaved buck PFC circuit is characterized in that,
comprises a three-phase input voltage source, a three-phase EMC filter, a virtual midpoint capacitor, an interleaved parallel circuit and a step-down filter circuit,
the interleaved parallel circuit is connected with the voltage reduction filter circuit,
the three-phase input voltage source is connected with the interleaved parallel circuit through the three-phase EMC filter and the virtual midpoint capacitor in sequence,
the interleaved parallel circuit includes a first interleaved circuit and a second interleaved circuit,
the first interleaving circuit is connected in parallel with the second interleaving circuit.
2. A three-phase interleaved buck PFC circuit according to claim 1,
the first interleaving circuit includes a first A-phase power transistor, a first B-phase power transistor and a first C-phase power transistor,
the emitters of the first A-phase power tube are respectively connected with the anode of the A-phase third diode Da3 and the anode of the A-phase first diode Da1, the cathode of the A-phase first diode Da1 is connected with the anode of the A-phase second diode Da2, the cathode of the A-phase second diode Da2 is respectively connected with the collector of the first A-phase power tube and the cathode of the A-phase fourth diode Da4,
the emitter of the first B-phase power tube is respectively connected with the anode of a B-phase third diode Db3 and the anode of a B-phase first diode Db1, the cathode of the B-phase first diode Db1 is connected with the anode of a B-phase second diode Db2, the cathode of the B-phase second diode Db2 is respectively connected with the cathode of a B-phase fourth diode Db4 and the collector of the first B-phase power tube,
the emitter of the first C-phase power tube is respectively connected with the anode of a C-phase third diode Dc3 and the anode of a C-phase first diode Dc1, the cathode of the C-phase first diode Dc1 is connected with the anode of a C-phase second diode Dc2, the cathode of the C-phase second diode Dc2 is respectively connected with the collector of the first C-phase power tube and the cathode of a C-phase fourth diode Dc4,
a cathode of the a-phase third diode Da3, a cathode of the B-phase third diode Db3, and a cathode of the C-phase third diode Dc3 are connected to a cathode of the first diode D1, and an anode of the a-phase fourth diode Da4, an anode of the B-phase fourth diode Db4, and an anode of the C-phase fourth diode Dc4 are connected to an anode of the first diode D1.
3. A three-phase interleaved buck PFC circuit according to claim 2 wherein the a-phase input of the first interleaved circuit is disposed between the a-phase first diode Da1 and the a-phase second diode Da2, the B-phase input of the first interleaved circuit is disposed between the B-phase first diode Db1 and the B-phase second diode Db2, the C-phase input of the first interleaved circuit is disposed between the C-phase first diode Dc1 and the C-phase second diode Dc2, and the three-phase input voltage source is connected to the a-phase input of the first interleaved circuit, the B-phase input of the first interleaved circuit, and the C-phase input of the first interleaved circuit, respectively.
4. A three-phase interleaved buck PFC circuit according to claim 1,
the second interleaving circuit comprises a second A-phase power tube, a second B-phase power tube and a second C-phase power tube,
the emitters of the second A-phase power tube are respectively connected with the anode of the A-phase seventh diode Da7 and the anode of the A-phase fifth diode Da5, the cathode of the A-phase fifth diode Da5 is connected with the anode of the A-phase sixth diode Da6, the cathode of the A-phase sixth diode Da6 is respectively connected with the collector of the second A-phase power tube and the cathode of the A-phase eighth diode Da8,
the emitters of the second B-phase power tube are respectively connected with the anode of the B-phase seventh diode Db7 and the anode of the B-phase fifth diode Db5, the cathode of the B-phase fifth diode Db5 is connected with the anode of the B-phase sixth diode Db6, the cathode of the B-phase sixth diode Db6 is respectively connected with the cathode of the B-phase eighth diode Db8 and the collector of the second B-phase power tube,
the emitter of the second C-phase power tube is respectively connected with the anode of the C-phase seventh diode Dc7 and the anode of the C-phase fifth diode Dc5, the cathode of the C-phase fifth diode Dc5 is connected with the anode of the C-phase sixth diode Dc6, the cathode of the C-phase sixth diode Dc6 is respectively connected with the collector of the second C-phase power tube and the cathode of the C-phase eighth diode Dc8,
a cathode of the a-phase seventh diode Da7, a cathode of the B-phase seventh diode Db7, and a cathode of the C-phase seventh diode Dc7 are connected to a cathode of the second diode D2, and an anode of the a-phase eighth diode Da8, an anode of the B-phase eighth diode Db8, and an anode of the C-phase eighth diode Dc8 are connected to an anode of the second diode D2.
5. A three-phase interleaved buck PFC circuit according to claim 4 wherein the a-phase input of the second interleaved circuit is disposed between the a-phase fifth diode Da5 and the a-phase sixth diode Da6, the B-phase input of the second interleaved circuit is disposed between the B-phase fifth diode Db5 and the B-phase sixth diode Db6, the C-phase input of the second interleaved circuit is disposed between the C-phase fifth diode Dc5 and the C-phase sixth diode Dc6, and the three-phase input voltage source is connected to the a-phase input of the second interleaved circuit, the B-phase input of the second interleaved circuit and the C-phase input of the second interleaved circuit respectively.
6. A three-phase interleaved buck PFC circuit according to claim 1, wherein a first output of the first interleaving circuit is connected to one end of a first inductor L1, a second output of the first interleaving circuit is connected to a fourth output of the second interleaving circuit and another end of a first capacitor C1, respectively, a third output of the second interleaving circuit is connected to one end of a second inductor L2, and another end of the first inductor L1 is connected to another end of the second inductor L2 and another end of the first capacitor C1, respectively.
7. A control method of a three-phase interleaved parallel buck PFC circuit is characterized by comprising the following steps:
s1, sampling the voltage of a power grid and calculating a phase-locked loop,
s2, carrying out outer ring control on the capacitor voltage,
s3, controlling an inductance current inner loop,
s4, carrying out feedforward control on the data,
and S5, generating PWM control signals in a staggered parallel connection mode.
8. The method as claimed in claim 7, wherein the grid is divided into 6 sectors, and the duty cycle of the power tube corresponding to each sector is different.
9. The method as claimed in claim 7, wherein the A-phase power transistor of the first interleaved circuit and the A-phase power transistor of the second interleaved circuit are interleaved by 180 °, the B-phase power transistor of the first interleaved circuit and the B-phase power transistor of the second interleaved circuit are interleaved by 180 °, and the C-phase power transistor of the first interleaved circuit and the C-phase power transistor of the second interleaved circuit are interleaved by 180 °.
10. The method as claimed in claim 7, comprising a PFC circuit, a main controller, a PWM signal generation module and a phase-locked loop calculation module, wherein the main controller comprises a first PID regulator, a second PID regulator, a third PID regulator and a feedforward controller, the first PID regulator is connected to the PFC circuit, the first PID regulator is respectively connected to the second PID regulator and the third PID regulator, the feedforward controller is respectively connected to the phase-locked loop calculation module, the second PID regulator and the third PID regulator, and the PWM signal generation module is connected to the feedforward controller.
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