CN111180342A - Shielded gate field effect transistor and method of forming the same - Google Patents
Shielded gate field effect transistor and method of forming the same Download PDFInfo
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- CN111180342A CN111180342A CN202010099468.6A CN202010099468A CN111180342A CN 111180342 A CN111180342 A CN 111180342A CN 202010099468 A CN202010099468 A CN 202010099468A CN 111180342 A CN111180342 A CN 111180342A
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention provides a shielded gate field effect transistor and a forming method thereof. After the first dielectric layer and the shielding electrode are sequentially formed, the part, higher than the shielding electrode, of the first dielectric layer is directly etched, so that the thickness of the etched part, higher than the shielding electrode, of the first dielectric layer is sequentially reduced from bottom to top, the appearance of an upper groove above the shielding electrode can be modified, the filling difficulty of the insulating filling layer can be reduced, the filling performance of the insulating filling layer in the upper groove is improved, gaps are avoided, and therefore when the insulating filling layer is subsequently etched to form an isolation layer, a gapless isolation layer can be formed, and mutual isolation between the gate electrode and the shielding electrode is guaranteed.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate field effect transistor and a forming method thereof.
Background
Because the Shielded Gate field effect transistor (SGT) has a low Gate-drain capacitance Cgd, a very low on-resistance, and a high withstand voltage, it is more favorable for flexible application of a semiconductor integrated circuit. Particularly, in the shielded gate field effect transistor, the shielding electrode is arranged below the gate electrode, so that the gate-drain capacitance can be greatly reduced, and the drift region of the shielded gate field effect transistor also has higher impurity carrier concentration, so that the shielded gate field effect transistor can provide additional benefits for the breakdown voltage of a device, and correspondingly can reduce the on-resistance.
Although the shielded gate field effect transistor has many performance advantages compared to other trench field effect transistors, the fabrication process is more complicated. For example, the isolation performance between the gate electrode and the shield electrode is one of the important indexes of the shielded gate field effect transistor, but the preparation process of the isolation layer between the gate electrode and the shield electrode is difficult to control, and the formed isolation layer is easy to generate a gap, thereby causing the gate electrode and the shield electrode to be short-circuited.
Disclosure of Invention
The invention aims to provide a method for forming a shielded gate field effect transistor, which aims to solve the problem that short circuit is easy to occur between a gate electrode and a shielding electrode in the existing shielded gate field effect transistor.
To solve the above technical problem, the present invention provides a method for forming a shielded gate field effect transistor, comprising:
providing a substrate, wherein a grid groove is formed in the substrate;
sequentially forming a first dielectric layer and a shielding electrode in the grid groove, wherein the first dielectric layer covers the bottom wall and the side wall of the grid groove, and the shielding electrode is formed on the first dielectric layer and is upwards filled to a first height position from the bottom of the grid groove;
etching the part of the first dielectric layer higher than the first height position so that the thickness dimension of the etched first dielectric layer in the direction vertical to the side wall of the groove is sequentially reduced from the first height position to the upper part;
filling an insulating filling layer in the gate trench, wherein the insulating filling layer covers a part of the first dielectric layer higher than a first height position and the shielding electrode;
etching the first dielectric layer and the insulating filling layer to remove the parts, higher than the second height position, in the first dielectric layer and the insulating filling layer, wherein the rest insulating filling layer forms an isolation layer to cover the top surface of the shielding electrode; and the number of the first and second groups,
and forming a gate electrode in the gate groove, wherein the gate electrode is positioned on the isolation layer and the first dielectric layer.
Optionally, before etching a portion of the first dielectric layer higher than the first height position, a thickness of the first dielectric layer in a direction perpendicular to a sidewall of the trench is greater than or equal to 3000 angstroms.
Optionally, a portion of the first dielectric layer higher than the first height position is etched, so that the portion of the etched first dielectric layer higher than the first height position has an inclined outer sidewall, and an included angle between the inclined outer sidewall of the first dielectric layer and the top surface of the shield electrode is greater than or equal to 110 degrees
Optionally, the bottom surface of the isolation layer covers the top surface of the shielding electrode, and the top surface of the isolation layer further extends laterally from the edge of the shielding electrode to connect the first dielectric layer.
Optionally, an aspect ratio of a portion of the gate trench higher than the first height position is greater than or equal to 2.
Optionally, after forming the isolation layer and before forming the gate electrode, the method further includes:
and forming a second dielectric layer on the side wall of the grid groove higher than the second height position.
Optionally, a thickness dimension of the first dielectric layer in a direction perpendicular to a sidewall of the trench is greater than a thickness dimension of the second dielectric layer in a direction perpendicular to the sidewall of the trench.
Based on the above-mentioned method for forming a shielded gate field effect transistor, the present invention also provides a shielded gate field effect transistor, comprising:
a substrate having a gate trench formed therein;
the first dielectric layer is formed on the side wall of the grid groove lower than the second height position, the thickness of the first dielectric layer is sequentially reduced from the first height position to the second height position, and the first height is lower than the second height position;
the shielding electrode is formed on the first dielectric layer and is positioned at the bottom of the gate trench, the top position of the shielding electrode corresponds to the first height position, and a groove is formed by the top surface of the shielding electrode and the side wall of the first dielectric layer higher than the first height position;
an isolation layer filled in the groove to cover the shielding electrode; and the number of the first and second groups,
and the gate electrode is formed in the gate groove and is positioned above the isolation layer and the first dielectric layer.
Optionally, a portion of the first dielectric layer between the first height position and the second height position is an inclined sidewall facing a sidewall of the isolation layer, and the inclined sidewall of the first dielectric layer is inclined in a direction facing a sidewall of the gate trench.
Optionally, the bottom surface of the isolation layer covers the top surface of the shielding electrode and is connected to a portion of the first dielectric layer corresponding to the first height position, and the top surface of the isolation layer extends laterally beyond the edge of the shielding electrode to be connected to a portion of the first dielectric layer corresponding to the second height position.
Optionally, the cross-sectional shape of the isolation layer along the height direction is an inverted trapezoid.
Optionally, the withstand voltage range of the shielded gate field effect transistor is greater than 60V.
In the forming method of the shielded gate field effect transistor, before the insulating filling layer is filled, the first dielectric layer formed on the side wall of the gate groove is etched, so that the thickness of the etched first dielectric layer at the position higher than the first height position is sequentially reduced from bottom to top, and correspondingly, the outer side wall of the etched first dielectric layer has a larger inclination angle relative to the height direction, thereby effectively modifying the appearance of an upper groove positioned above the shielding electrode, being beneficial to reducing the filling difficulty of a subsequent insulating filling layer, improving the filling performance of the insulating filling layer in the upper groove and avoiding a gap from being formed in the insulating filling layer. Therefore, when the insulating filling layer is etched to form the isolation layer, the formed isolation layer can be prevented from generating a gap, and the problem that the gate electrode and the shielding electrode are easy to short circuit can be effectively solved.
Therefore, the shielding grid field effect transistor formed by the forming method provided by the invention has the advantages that the isolation layer between the shielding electrode and the grid electrode has better compactness without a gap, and the short circuit problem between the shielding electrode and the grid electrode is favorably avoided. In the shielded gate field effect transistor, the first dielectric layer is higher than the shielding electrode, so that the shielding electrode can be better coated to improve the isolation performance between the shielding electrode and the substrate. And the isolation layer is filled in the groove surrounded by the first dielectric layer, so that the width of the isolation layer is larger than that of the shielding electrode, the isolation layer can more fully cover the shielding electrode, and the isolation performance between the shielding electrode and the gate electrode is further ensured.
Drawings
FIGS. 1a to 1c are schematic structural views of a shielded gate field effect transistor during a manufacturing process thereof;
FIG. 2 is a flow chart illustrating a method of forming a shielded gate field effect transistor according to an embodiment of the invention;
fig. 3a to fig. 3g are schematic structural diagrams of a method for forming a shielded gate field effect transistor in a manufacturing process according to an embodiment of the invention.
Wherein the reference numbers are as follows:
10-a substrate;
11-a gate trench;
20-a shield electrode;
31-an insulating filling layer;
31 a-voids;
30-an isolation layer;
30 a-a notch;
40-a gate electrode;
61-a dielectric layer;
100-a substrate;
110-a gate trench;
200-a shield electrode;
300-an isolation layer;
310 a-a layer of insulating material;
310-insulating filling layer;
400-a gate electrode;
500-mask layer;
510-lining oxide layer;
520-a first hard mask layer;
530-a second hard mask layer;
610-a first dielectric layer;
610 a-an outer sidewall;
620-second dielectric layer;
h1 — first height position;
h2-second elevation position.
Detailed Description
As described in the background art, in the current process of preparing the isolation layer between the gate electrode and the shield electrode, a gap is easily generated in the isolation layer. In view of the above problems, the inventors of the present invention have found, after research, that a gap is easily generated in the spacer between the gate electrode and the shield electrode, because: the insulating filling material used for forming the isolation layer is provided with a gap, and then when the insulating filling material is etched to form the isolation layer, a gap is generated in the formed isolation layer.
Specifically, a method of forming a shielded gate field effect transistor generally includes the following steps.
In a first step, referring to fig. 1a specifically, a substrate 10 is provided, a gate trench 11 is formed in the substrate 10, and a dielectric layer 61 and a shielding electrode 20 are further formed in the gate trench 11, where the dielectric layer 61 covers sidewalls and a bottom wall of the entire gate trench.
In a second step, with continued reference to fig. 1a, the gate trench 11 is filled with an insulating filling layer 31.
It should be noted that the upper trench of the gate trench 11 above the shield electrode 20 still has a large aspect ratio, which may result in a difficult filling of the upper trench. Particularly, when the dielectric layer 61 with a larger thickness is further formed on the sidewall of the gate trench 110, the aspect ratio of the upper trench is further increased, and the filling difficulty of the insulating material is further increased. Based on this, it is common practice to remove the portion of the dielectric layer 61 above the shield electrode 20 before filling the insulating filling layer, exposing the sidewall of the gate trench 11, so as to increase the aspect ratio of the upper trench of the gate trench 11.
However, as shown in fig. 1b, even if the dielectric layer is partially removed, the problem of difficulty in filling the insulating filling layer 31 cannot be effectively solved, and the gap 31a is still easily generated in the insulating filling layer 31 filled in the gate trench 11.
In a third step, specifically referring to fig. 1b, the insulating filling layer 31 is etched to form an isolation layer 30. As described above, since the insulating filling layer 31 has the gap 31a, when the insulating filling layer 31 is etched to form the isolation layer 30, the gap 30a is generated in the isolation layer 30 corresponding to the projection position of the gap 31 a.
A fourth step, shown in particular with reference to fig. 1c, forms a gate electrode 40 in said gate trench 11. As shown in fig. 1c, due to the gap 30a in the isolation layer 30, the gate electrode 40 is shorted to the shielding electrode 20.
In order to solve the technical problems, the invention provides a forming method of a shielded gate field effect transistor, which can effectively improve the problem that a gap is easy to generate in an insulating filling layer, so that a formed isolation layer cannot generate a gap, and the defect of short circuit between a gate electrode and a shielded electrode is avoided.
The shielded gate field effect transistor and the method for forming the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2 is a schematic flow chart of a method for forming a shielded gate field effect transistor according to an embodiment of the invention, and fig. 3a to 3g are schematic structural diagrams of the method for forming a shielded gate field effect transistor according to an embodiment of the invention in a manufacturing process thereof. The method for forming the shielded gate field effect transistor in this embodiment will be described in detail below with reference to fig. 2 and 3a to 3 g.
In step S100, specifically referring to fig. 3a, a substrate 100 is provided, wherein a gate trench 110 is formed in the substrate 100. In the subsequent process, the gate trench 110 is utilized to sequentially accommodate the shield electrode and the gate electrode from bottom to top.
Specifically, the forming method of the gate trench 110 includes, for example: firstly, forming a mask layer 500 on the top surface of the substrate 100, so as to define the pattern of the gate trench by using the mask layer 500; next, the substrate 100 is etched using the mask layer 500 as a mask to form the gate trench 110.
The mask layer 500 may have a stacked structure in which a plurality of film layers are stacked. Specifically, the mask layer 500 includes a liner oxide layer 510 formed on the top surface of the substrate 100 and a first hard mask layer 520 formed on the liner oxide layer 510, where the first hard mask layer 520 includes, for example, silicon nitride. Of course, the mask layer 500 may further include a second hard mask layer 530, and the material of the second hard mask layer 530 may be different from that of the first hard mask layer 520, for example, including silicon oxide.
That is, in this embodiment, since the first hard mask layer 520 and the second hard mask layer 530 are covered on the substrate 100 with the substrate oxide layer 510 therebetween, the stress applied to the substrate 100 by the hard mask layer over the substrate oxide layer can be relieved by the substrate oxide layer 510, and the top surface of the substrate 100 can be protected. And, because the depth of the formed gate trench 110 is large, on the basis, by providing two or more hard mask layers (the first hard mask layer 520 and the second hard mask layer 530), the mask layer 500 is prevented from being consumed in a large amount when the substrate 100 is etched, and the pattern accuracy of the mask layer 500 is improved.
In this embodiment, the sidewalls of the gate trench 110 may be vertical sidewalls, or slightly inclined sidewalls. That is, in the present embodiment, the inclination angle of the sidewall of the gate trench 110 with respect to the height direction is small. Note that the "inclination angle of the sidewall of the gate trench 110 with respect to the height direction" described here is: the angle between the sidewall of the gate trench 110 and the height direction.
In step S200, referring to fig. 3b specifically, a first dielectric layer 610 and a shielding electrode 200 are sequentially formed in the gate trench 110, the first dielectric layer 610 covers the bottom wall and the sidewall of the gate trench 110, the shielding electrode 200 is formed on the first dielectric layer 610 and located at the bottom of the gate trench 110, and specifically, the top position of the shielding electrode 200 corresponds to a first height position H1. At this time, a portion of the first dielectric layer 610 higher than the first height position H1 is exposed in the gate trench 110.
The first dielectric layer 610 may be formed by a thermal oxidation process, for example, and the material of the first dielectric layer 610 includes silicon oxide (SiO), for example.
It should be noted that the thickness of the first dielectric layer 610 may be adjusted according to the requirement of the withstand voltage of the formed shielded gate field effect transistor. For example, when the formed shielded gate field effect transistor is a high voltage transistor (the withstand voltage range is, for example, greater than or equal to 60V, and more specifically, the withstand voltage range of the high voltage transistor is between 80V and 150V), the first dielectric layer 610 may have a larger thickness in the direction perpendicular to the trench sidewall for maintaining the high withstand voltage performance of the transistor. For example, the thickness dimension of the first dielectric layer 610 in the direction perpendicular to the trench sidewall may be greater than or equal to 3000 angstroms, and more specifically, the thickness dimension of the first dielectric layer 610 may be further between 5000 angstroms and 7000 angstroms, for example.
Further, after the first dielectric layer 610 is formed, i.e., the shielding electrode 200 is filled in the gate trench 110, the shielding electrode 200 is correspondingly formed on the first dielectric layer 610.
Specifically, the shielding electrode 200 may be formed by using an etch-back process to lower the top surface of the shielding electrode 200 to the first height position H1, where the first height position H1 is lower than the top position of the gate trench 110. And, after forming the shield electrode 200, a portion of the gate trench 110 higher than the shield electrode 200 constitutes an upper trench. It is to be understood that the portion of the gate trench 110 higher than the first height position H1 constitutes an upper trench, the portion of the gate trench 110 lower than the first height position H1 constitutes a lower trench, and the shield electrode 200 is filled in the lower trench.
It should be noted that the upper trench of the gate trench 110 above the first height position H1 still has a large aspect ratio, such as an aspect ratio greater than or equal to 2, and even the aspect ratio of the upper trench may be greater than 2.5. However, the difficulty of filling material in trenches with aspect ratios of 2 or more is generally high. In particular, in the present embodiment, the first dielectric layer 610 with a larger thickness is further formed on the sidewall of the gate trench 110, so as to further increase the aspect ratio of the upper trench, and further increase the filling difficulty when directly filling the insulating material.
In step S300, referring to fig. 3c specifically, a portion of the first dielectric layer 610 higher than the first height position H1 is etched, so that the thickness dimension of the etched first dielectric layer 610 in the direction perpendicular to the trench sidewall decreases sequentially from the first height position H1 upward. The portion of the first dielectric layer 610 higher than the first height position H1 is, for example, the upper portion of the first dielectric layer 610.
As described above, the first dielectric layer 610 in the embodiment has a larger thickness, and therefore, the upper portion of the first dielectric layer 610 with the thickness increasing from top to bottom can be directly formed by etching the first dielectric layer 610.
Specifically, in the etching process of the first dielectric layer 610, since the etching gas may generate a polymerization product in the etching process of the first dielectric layer, the polymerization product may further adhere to the sidewall of the first dielectric layer 610, at this time, since the etching strength of the bottom of the first dielectric layer 610 is weaker than the etching strength of the top of the first dielectric layer 610, the consumption of the first dielectric layer 610 may gradually decrease from top to bottom as the etching is continuously performed, and thus an inclined sidewall is formed. The etching gas for etching the first dielectric layer 610 may be selected according to the material of the first dielectric layer 610. For example, if the material of the first dielectric layer 610 comprises silicon oxide, the etching gas used may comprise trifluoromethane (CHF 3).
As shown in fig. 3c, the thickness of the upper portion of the first dielectric layer 610 above the first height position H1 decreases from bottom to top, so that the opening size of the newly defined upper trench correspondingly has portions that increase from bottom to top. It can also be understood that, by adjusting the thickness dimension of the upper portion of the first dielectric layer 610 such that the inclination angle of the outer sidewall 610a of the upper portion of the first dielectric layer 610 with respect to the height direction is larger than the inclination angle of the sidewall of the gate trench 110, the inclination angle of the sidewall of the newly defined upper trench with respect to the height direction is increased. Therefore, the filling performance of the upper groove with the wide upper part and the narrow lower part can be improved, and the problem that the insulating filling layer filled in the upper groove has a gap is favorably avoided.
In this embodiment, the outer sidewall 610a of the upper portion of the first dielectric layer 610 is an inclined sidewall, and the inclined sidewall of the first dielectric layer 610 (i.e., the outer sidewall 610a) is inclined in a direction toward the sidewall of the gate trench, at this time, an included angle θ between the inclined sidewall of the first dielectric layer 610 and the top surface of the shielding electrode 200 may be greater than 110 °, and further, an included angle θ between the inclined sidewall of the first dielectric layer 610 and the top surface of the shielding electrode 200 may be in a range of 110 ° to 140 °.
In an alternative, the etched first dielectric layer 610 has an upper portion with an inclined sidewall extending to the top of the gate trench, so that the upper trench, which is located above the shielding electrode 200 and is re-defined by the upper portion of the first dielectric layer 610, has an inverted trapezoid structure as a whole. However, it should be appreciated that in other embodiments, the top of the inclined sidewall of the upper portion of the first dielectric layer 610 may be lower than the top of the gate trench 110, so that the portion of the upper trench defined near the shield electrode 200 is in an inverted trapezoid structure, and the portion of the upper trench higher than the first dielectric layer is in a rectangular structure, which still reduces the difficulty in filling the upper trench subsequently.
In addition, in this embodiment, the outer sidewall 610a of the upper portion of the first medium layer 610 is close to a straight line, so that the upper groove defined by the upper portion of the first medium layer has an inverted trapezoid structure. However, in other embodiments, the outer sidewall 610a of the upper portion of the first dielectric layer 610 may also be an arcuate sidewall, and may be such that the shape of the redefined upper channel appears as a bowl.
In step S400, referring to fig. 3d and fig. 3e in particular, an insulating filling layer 310 is filled in the gate trench 110, and the insulating filling layer 310 covers an upper portion of the first dielectric layer 610 higher than the first height position H1 and the shield electrode 200. At this time, the insulation filling layer 310 is filled in the newly defined upper trench.
Referring to fig. 3d, the insulating filling layer 310 is a planarized film layer, so that the insulating filling layer 310 has a flat top surface. Specifically, the method for forming the insulating filling layer 310 may include the following steps.
First, referring specifically to fig. 3d, a deposition process is performed to deposit an insulating material layer 310a on the substrate 100, wherein the insulating material layer 310a fills the upper trench of the gate trench 110 and covers the top surface of the substrate 100 (in this embodiment, the insulating material layer 310a correspondingly covers the mask layer 500).
It should be noted that, since the outer sidewall 610a of the first dielectric layer 610 has a larger inclination angle with respect to the height direction, the opening size of the defined upper trench has a portion that increases from bottom to top (for example, the upper trench is made to have an inverted trapezoid structure), so that the filling performance of the insulating material layer 310a in the upper trench can be improved, and a void in the insulating material layer 310a can be avoided.
The material of the insulating material layer 310a may be the same as the material of the first dielectric layer 610, for example, the materials of the insulating material layer 310a and the first dielectric layer 610 may both include silicon oxide (SiO). In this way, when the insulating material layer 310a and the upper portion of the first dielectric layer 610 are etched later, the etching rates of the insulating material layer 310a and the first dielectric layer 610 can be balanced, and the etching of the insulating material layer 310a and the first dielectric layer 610 can be accurately controlled.
Further, a deposition process for the insulating material layer 310a is, for example, a High Density Plasma (HDP) process, so as to further reduce the filling difficulty of the insulating material layer 310a and improve the filling performance of the insulating material layer 310a in the gate trench 110.
In a second step, referring to fig. 3e in particular, a planarization process is performed to planarize the insulating material layer, so as to form the insulating filling layer 310. In this embodiment, the planarization process is specifically a chemical mechanical polishing process, and the first hard mask layer 520 in the mask layer can be used as a polishing stop layer, so that the top surface of the planarized insulating filling layer 310 is a flat surface and is flush with the top surface of the first hard mask layer 520.
Since the insulating filling layer 310 has a flat top surface, when the insulating filling layer 310 is etched subsequently, the insulating filling layer 310 can be consumed uniformly from top to bottom, so that the etched insulating filling layer can still maintain the flat top surface.
In step S500, referring to fig. 3f in particular, the first dielectric layer 610 and the insulating filling layer 310 are etched to remove the portions of the first dielectric layer 610 and the insulating filling layer 310 higher than the second height position H2, and the remaining insulating filling layer constitutes an isolation layer 300 to cover the top surface of the shielding electrode 200. Wherein the second height position H2 is higher than the first height position H1 and lower than the top position of the gate trench 110.
As described above, the insulating filling layer 310 in the embodiment has no void formed therein and has a flat top surface, so that when performing the etching process, the insulating filling layer can be consumed uniformly from top to bottom to the second height position H2, thereby avoiding the formation of a gap in the remaining insulating filling layer, which is equivalent to the formation of no gap in the isolation layer 300.
In this embodiment, after the etching of the first dielectric layer 610, the sidewall of the gate trench 110 higher than the second height position H2 may be further exposed. The remaining first dielectric layer 610 covers the periphery of the shielding electrode 200 and may be used to form a field oxide layer, and a portion of the remaining first dielectric layer 610 between the first height position H1 and the second height position H2 surrounds the periphery of the isolation layer 300.
And the isolation layer 300 is correspondingly located between the first height position H1 and the second height position H2, and covers the shielding electrode 200 with the isolation layer 300 to avoid exposing the shielding electrode 200, so that the gate electrode formed subsequently above the isolation layer 300 can be prevented from being shorted with the shielding electrode 200.
In step S600, referring to fig. 3g in particular, a gate electrode 400 is formed in the gate trench 110, wherein the gate electrode 400 is located on the isolation layer 300 and the first dielectric layer 610, so as to be electrically isolated from the shielding electrode 200 by the isolation layer 300. The gate electrode 400 and the shield electrode 200 may be formed of the same material, for example, the gate electrode 400 and the shield electrode 200 may both include polysilicon.
Further, before forming the gate electrode 400, the method further includes: a second dielectric layer 620 is formed on sidewalls of the gate trench 110 higher than the second height position H2. Specifically, the second dielectric layer 620 may be formed by a thermal oxidation process, and the second dielectric layer 620 is used for forming a gate oxide layer. In this embodiment, the thickness of the second dielectric layer 620 is smaller than the thickness of the first dielectric layer 610.
Based on the above forming method, the present embodiment further provides a shielded gate field effect transistor, which can be specifically shown in fig. 3g, where the shielded gate field effect transistor includes:
a substrate 100, wherein a gate trench 110 is formed in the substrate 100;
a first dielectric layer 610 formed on a sidewall of the gate trench 110 lower than the second height position H2, wherein a thickness dimension of the first dielectric layer 610 decreases from a first height position H1 to a second height position H2, and the first height position H1 is lower than the second height position H2;
a shield electrode 200 formed on the first dielectric layer 610 and filling the bottom of the gate trench 110, wherein the top of the shield electrode 200 corresponds to a first height position H1, and a groove is surrounded by the top surface of the shield electrode 200 and the sidewall of the first dielectric layer 610 higher than the first height position H1;
an isolation layer 300 filled in the groove to cover the shielding electrode 200; and the number of the first and second groups,
and a gate electrode 400 formed in the gate trench 110 and over the isolation layer 300 and the first dielectric layer 610. That is, the isolation layer 300 is spaced between the gate electrode 400 and the shield electrode 200 to isolate them from each other.
With continued reference to fig. 3g, the connection surface of the isolation layer 300 and the first dielectric layer 610 is an inclined connection surface. The inclined angle of the connection surface between the isolation layer 300 and the first dielectric layer 610 with respect to the height direction is, for example, 20 ° to 50 °.
Specifically, the portion of the first dielectric layer 610 covering the sidewall of the gate trench is higher than the shield electrode 200 and extends upward to the periphery of the isolation layer 300, so that the isolation between the shield electrode 200 and the substrate 100 can be better achieved. Also, a portion of the first dielectric layer 610 between the first height position H1 and the second height position H2 is a sloped sidewall toward a sidewall of the isolation layer 300, and the sloped sidewall of the first dielectric layer 610 is sloped in a direction toward a sidewall of the gate trench 110.
And, the isolation layer 300 is filled in the groove surrounded by the first dielectric layer, so that, in match with the first dielectric layer 610, the sidewall of the isolation layer 300 facing the first dielectric layer 610 is correspondingly an inclined sidewall, and the inclined sidewall of the isolation layer 300 is also inclined in a direction facing the sidewall of the gate trench 110. It can be understood that, in this embodiment, a connection surface of the first dielectric layer 610 and the isolation layer 300 at the connection position is an inclined connection surface, so that the first dielectric layer 610 and the isolation layer 300 can be connected more closely, which is beneficial to improving the isolation performance of the first dielectric layer 610 and the isolation layer 300.
In this embodiment, the cross-sectional shape of the groove surrounded by the first dielectric layer 610 in the height direction is a regular trapezoid, and accordingly, the cross-sectional shape of the isolation layer 300 filled in the groove in the height direction is an inverted trapezoid. Specifically, the bottom surface of the isolation layer 300 covers the top surface of the shielding electrode 200, and the boundary of the inclined sidewall of the inverted trapezoid of the isolation layer 300 exceeds the boundary of the shielding electrode to connect with the portion of the first dielectric layer 610 higher than the first height position H1. At this time, namely, equivalently, the width dimension of the isolation layer 300 covering the shield electrode 200 is larger than the width dimension of the shield electrode 200, so that the isolation performance between the shield electrode 200 and the gate electrode 400 can be further secured.
In addition, a second dielectric layer 620 is further formed on the sidewall of the gate trench 110 corresponding to the gate electrode 400, so that the second dielectric layer 620 is utilized to realize the isolation between the gate electrode 400 and the substrate 100.
The thickness of the first dielectric layer 610 and the second dielectric layer 620 may be adjusted according to the requirement of the voltage resistance of the shielded gate field effect transistor. For example, when the shielded gate field effect transistor is a high voltage transistor (the withstand voltage range is, for example, greater than or equal to 60V, and more specifically, the withstand voltage range of the high voltage transistor is between 80V and 150V), the first dielectric layer 610 may have a larger thickness (for example, the thickness of the first dielectric layer 610 is greater than that of the second dielectric layer 620) in order to satisfy the withstand voltage performance of the high voltage transistor. In a specific embodiment, the thickness of the first dielectric layer 610 is greater than 3000 angstroms, and the thickness of the second dielectric layer 620 is between 500 angstroms and 1000 angstroms.
In summary, in the method for forming a shielded gate field effect transistor provided in this embodiment, after the shielding electrode is formed, the outer sidewall of the first dielectric layer is modified by etching the portion of the first dielectric layer higher than the shielding electrode, so that the thickness of the etched first dielectric layer is sequentially reduced (for example, the etched first dielectric layer has an inclined outer sidewall), and accordingly, the outer sidewall of the etched first dielectric layer has a larger inclination angle with respect to the height direction, thereby redefining the topography of the upper trench of the gate trench. Based on the structure, when the insulating filling layer is filled, the filling performance of the insulating filling layer in the upper groove can be effectively improved, a gap is prevented from being formed in the insulating filling layer, and further, when the insulating filling layer is etched subsequently to form the isolation layer, a gap can be prevented from being formed in the formed isolation layer. Therefore, the isolation layer can be used for effectively avoiding the problem that short circuit is easy to occur between the gate electrode and the shielding electrode, and ensuring effective isolation between the gate electrode and the shielding electrode.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (10)
1. A method for forming a shielded gate field effect transistor includes
Providing a substrate, wherein a grid groove is formed in the substrate;
sequentially forming a first dielectric layer and a shielding electrode in the grid groove, wherein the first dielectric layer covers the bottom wall and the side wall of the grid groove, the shielding electrode is formed on the first dielectric layer and is positioned at the bottom of the grid groove, and the top position of the shielding electrode corresponds to a first height position;
etching the part of the first dielectric layer higher than the first height position so that the thickness dimension of the etched first dielectric layer in the direction vertical to the side wall of the groove is sequentially reduced from the first height position to the upper part;
filling an insulating filling layer in the gate trench, wherein the insulating filling layer covers a part of the first dielectric layer higher than a first height position and the shielding electrode;
etching the first dielectric layer and the insulating filling layer to remove parts, higher than a second height position, in the first dielectric layer and the insulating filling layer, wherein the rest insulating filling layer forms an isolation layer to cover the top surface of the shielding electrode, and the second height position is higher than the first height position; and the number of the first and second groups,
and forming a gate electrode in the gate groove, wherein the gate electrode is positioned on the isolation layer and the first dielectric layer.
2. The method of claim 1, wherein a thickness of the first dielectric layer in a direction perpendicular to the trench sidewalls is greater than or equal to 3000 angstroms prior to etching the portion of the first dielectric layer above the first height location.
3. The method of claim 1, wherein the portion of the first dielectric layer above the first height position is etched such that the portion of the first dielectric layer above the first height position has an inclined outer sidewall, and an angle between the inclined outer sidewall of the first dielectric layer and the top surface of the shield electrode is greater than or equal to 110 °.
4. The method of claim 1, wherein an aspect ratio of a portion of the gate trench above the first height position is greater than or equal to 2.
5. The method of forming a shielded gate field effect transistor according to claim 1, further comprising, after forming the isolation layer and before forming the gate electrode:
and forming a second dielectric layer on the side wall of the grid groove higher than the second height position.
6. The method of claim 5, wherein a thickness dimension of the first dielectric layer in a direction perpendicular to a trench sidewall is greater than a thickness dimension of the second dielectric layer in a direction perpendicular to a trench sidewall.
7. A shielded gate field effect transistor, comprising:
a substrate having a gate trench formed therein;
the first dielectric layer is formed on the side wall of the grid groove lower than the second height position, the thickness of the first dielectric layer is sequentially reduced from the first height position to the second height position, and the first height position is lower than the second height position;
the shielding electrode is formed on the first dielectric layer and is positioned at the bottom of the gate trench, the top position of the shielding electrode corresponds to the first height position, and a groove is formed by the top surface of the shielding electrode and the side wall of the first dielectric layer higher than the first height position in a surrounding mode;
an isolation layer filled in the groove to cover the shielding electrode; and the number of the first and second groups,
and the gate electrode is formed in the gate groove and is positioned above the isolation layer and the first dielectric layer.
8. The shielded gate field effect transistor of claim 7 wherein a portion of the first dielectric layer between the first elevational position and the second elevational position is a sloped sidewall toward a sidewall of the isolation layer, and wherein the sloped sidewall of the first dielectric layer is sloped in a direction toward a sidewall of the gate trench.
9. The shielded gate field effect transistor of claim 7 wherein said spacer has an inverted trapezoidal cross-sectional shape along the height direction.
10. The method according to any one of claims 7 to 9, wherein the breakdown voltage range of the shielded gate field effect transistor is greater than 60V.
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