CN115910764A - Shielded gate field effect transistor and preparation method thereof - Google Patents
Shielded gate field effect transistor and preparation method thereof Download PDFInfo
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- CN115910764A CN115910764A CN202211493315.5A CN202211493315A CN115910764A CN 115910764 A CN115910764 A CN 115910764A CN 202211493315 A CN202211493315 A CN 202211493315A CN 115910764 A CN115910764 A CN 115910764A
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Abstract
The invention provides a shielded gate field effect transistor and a preparation method thereof. In the preparation method, the first isolation layer is formed by oxidizing the protruding part of the shielding electrode, and the gap between the first isolation layer and the second dielectric layer is further filled by using the insulating material with fluidity under the preset condition, so that not only can the gap in the shape of a sharp corner in the gap be filled, the bottom of the gate electrode is prevented from generating an included angle structure, but also the thickness of the isolation layer can be compensated, the isolation effect between the gate electrode and the shielding electrode is improved, the leakage current phenomenon of the device is further reduced, and the reliability of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate field effect transistor and a preparation method thereof.
Background
Because the Shielded Gate field effect transistor (SGT) has a low Gate-drain capacitance Cgd, a very low on-resistance, and a high withstand voltage, it is more favorable for flexible application of a semiconductor integrated circuit.
Particularly, in the shielded gate field effect transistor, the shielding electrode is arranged below the gate electrode, so that the gate-drain capacitance can be greatly reduced, and the drift region of the shielded gate field effect transistor also has higher impurity carrier concentration, so that the shielded gate field effect transistor can provide additional benefits for the breakdown voltage of a device, and correspondingly can reduce the on-resistance. An isolation layer (IPO) is typically disposed between the shield electrode and the gate electrode to isolate the shield electrode and the gate electrode from each other.
In one conventional fabrication method, such as that shown with reference to fig. 1, the protruding top of shield electrode 30 may be directly oxidized to form isolation layer 40. Although this method can effectively simplify the process, the bottom of the isolation layer 40 formed by oxidation is easily oxidized to a thickness too small due to insufficient oxidation, so that a sharp corner pointing to the shield electrode 30 is generated in the gap between the isolation layer 40 and the trench sidewall (as shown by the dashed line box in fig. 1). In this way, when forming the gate electrode 50, as shown in fig. 2, the part of the gate electrode 50 filling the sharp corner points to the shielding electrode 30, and the thickness of the isolation layer 40 between the gate electrode 50 and the shielding electrode 30 is small, so that the reverse gate-source leakage current (IGSSR) of the device is increased, and the negative high-temperature gate bias (HTGB) of the device is affected, which causes a problem in the reliability of the device.
Disclosure of Invention
The invention aims to provide a preparation method of a shielded gate field effect transistor, so that reverse gate source leakage current of a prepared and formed device is reduced, and reliability of the device is improved.
In order to solve the above technical problem, the present invention provides a method for manufacturing a shielded gate field effect transistor, comprising: providing a substrate, wherein a groove is formed in the substrate, and a first dielectric layer is formed on the bottom and the side wall of the groove; forming a shielding electrode on the first dielectric layer, wherein the shielding electrode is lower than the top of the groove; etching the first dielectric layer to remove the part of the first dielectric layer, which is higher than the shielding electrode, and enabling the top of the shielding electrode to protrude out of the top of the etched first dielectric layer; performing an oxidation process to form a second dielectric layer on the side wall of the groove higher than the first dielectric layer, and oxidizing the protruding part of the shielding electrode to form a first isolation layer, wherein a gap is formed between the first isolation layer and the second dielectric layer; forming a second isolation layer of a material that is flowable under predetermined conditions to fill at least a bottom of the gap; and forming a gate electrode in the trench, the gate electrode being located on the first isolation layer and the second isolation layer.
Optionally, oxidizing the protruding portion of the shielding electrode to form a first isolation layer includes: the top surface and sidewalls of the projection of the shield electrode are oxidized, and the oxidation thickness at the bottom position of the projection sidewalls is smaller than the oxidation thickness at the top position of the projection sidewalls.
Optionally, the top of the liquid insulating material filled in the gap is not higher than the top of the first isolation layer.
Optionally, the method for forming the second isolation layer includes: and spin-coating a liquid insulating material to fill at least the bottom of the gap, and curing the liquid insulating material to form the second isolation layer.
Optionally, the liquid insulating material comprises silicone. Wherein the method of curing the liquid insulating material may include performing annealing curing under an inert gas at a temperature of 400 ℃ to 500 ℃. And, the method of curing the liquid insulating material may further include performing annealing curing in an atmosphere of nitrogen or argon.
The present invention also provides a shielded gate field effect transistor comprising: a substrate having a trench formed therein; the first dielectric layer is formed at the bottom and the side wall of the groove; the shielding electrode is formed on the first dielectric layer, and the top of the shielding electrode protrudes out of the first dielectric layer; the second dielectric layer is formed on the side wall of the groove higher than the first dielectric layer; a first isolation layer formed on a top surface and sidewalls of the projection of the shield electrode; the second isolation layer is filled in a gap between the first isolation layer and the second dielectric layer; and the gate electrode is filled in the groove and is positioned on the first isolation layer and the second isolation layer.
Optionally, the top surface of the second isolation layer filled in the gap is not higher than the top surface of the first isolation layer, the top surface of the second isolation layer in the gap is an inward concave arc surface, and the bottom surface of the gate electrode at the position of the gap correspondingly presents an arc bottom surface.
Optionally, if a pointed region pointing to the shielding electrode is formed at a corner position where the first isolation layer and the first dielectric layer are connected, the second isolation layer fills the pointed region.
In the preparation method of the shielded gate field effect transistor, after the convex part of the shielding electrode is oxidized to form the first isolation layer, the gap between the first isolation layer and the second dielectric layer is filled by using the insulating material with fluidity under the preset condition, the flowing insulating material can well fill the bottom of the gap, and the bottom of the corresponding filling gap points to the gap in the shape of the sharp corner of the shielding electrode. Therefore, the bottom of the gate electrode can be prevented from generating a sharp-angled structure, the thickness of the isolation layer can be compensated, the isolation effect between the gate electrode and the shielding electrode is improved, the reverse gate source leakage current (IGSSR) of the device is reduced, the negative high-temperature gate bias (HTGB) of the device is optimized, and the reliability of the device is improved.
Drawings
Fig. 1-2 are schematic structural diagrams of a shielded gate field effect transistor during a manufacturing process thereof.
Fig. 3 is a flow chart illustrating a method for manufacturing a shielded gate field effect transistor according to an embodiment of the invention.
Fig. 4-8 are schematic structural diagrams of a shielded gate field effect transistor in a manufacturing process according to an embodiment of the invention.
Wherein the reference numbers are as follows:
30-a shield electrode;
40-an isolation layer;
50-a gate electrode;
100-a substrate;
100 a-trench;
210-a first dielectric layer;
220-a second dielectric layer;
300-a shield electrode;
410-a first isolation layer;
420-a second isolation layer;
500-gate electrode.
Detailed Description
The core idea of the invention is to provide a preparation method of a shielded gate field effect transistor, which can effectively compensate the gap with a sharp corner shape generated in the side gap of an isolation layer due to the limitation of the oxidation process of the isolation layer, thereby avoiding the sharp corner part pointing to a shielding electrode formed at the bottom of a gate electrode, being beneficial to improving the leakage current phenomenon of a device and improving the reliability of the device.
Referring specifically to fig. 3, the method for manufacturing the shielded gate field effect transistor includes the following steps.
Step S100, providing a substrate, wherein a groove is formed in the substrate, and a first dielectric layer is formed on the bottom and the side wall of the groove.
Step S200, forming a shielding electrode on the first dielectric layer, and making the shielding electrode lower than the top of the trench.
Step S300, etching the first dielectric layer to remove the part of the first dielectric layer higher than the shielding electrode and make the top of the shielding electrode protrude out of the top of the etched first dielectric layer.
Step S400, performing an oxidation process to form a second dielectric layer on the sidewall of the trench higher than the first dielectric layer, and oxidizing the protruding portion of the shielding electrode to form a first isolation layer, wherein a gap is formed between the first isolation layer and the sidewall of the trench.
Step S500, forming a second isolation layer, a material of the second isolation layer having fluidity under a predetermined condition to fill at least a bottom of the gap.
Step S600, forming a gate electrode in the trench, the gate electrode being located on the first isolation layer and the second isolation layer.
The shielded gate field effect transistor and the method for forming the same according to the present invention will be described in further detail with reference to fig. 4-8 and the embodiments. Fig. 4-8 are schematic structural diagrams of a shielded gate field effect transistor in a manufacturing process of the shielded gate field effect transistor according to an embodiment of the invention. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It will be understood that relative terms, such as "above," "below," "top," "bottom," "above," and "below," may be used in relation to various elements shown in the figures. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures. For example, if the device were inverted relative to the view in the drawings, an element described as "above" another element, for example, would now be below that element.
In step S100, referring specifically to fig. 4, a substrate 100 is provided, a trench 100a is formed in the substrate 100, and a first dielectric layer 210 is formed on the bottom and the sidewall of the trench 100a.
Specifically, the forming method of the trench 100a includes, for example: first, a patterned mask layer is formed on the top surface of the substrate 100; next, the substrate 100 is etched using the patterned mask layer as a mask to form the trench 100a.
Referring specifically to fig. 4, after the trench 100a is formed, a first dielectric layer 210 may be formed by using an oxidation process or a deposition process, wherein the first dielectric layer 210 covers the sidewalls and the bottom wall of the trench 100a, and in this step, the first dielectric layer 210 covers the entire inner surface of the trench 100a. Wherein the material of the first dielectric layer 210 includes, for example, silicon oxide (SiO) 2 ). It should be noted that the thickness of the first dielectric layer 210 can be adjusted according to the requirement of the withstand voltage of the formed shielded gate field effect transistor. For example, when the formed shielded gate field effect transistor is a low voltage transistor (with a withstand voltage of less than 60V, for example), the thickness of the first dielectric layer 210 in the direction perpendicular to the trench sidewall can be made smaller than 2000 angstroms, and more specifically, the thickness of the first dielectric layer 210 is between 800 angstroms and 1500 angstroms, for example.
In step S200, referring specifically to fig. 4, a shielding electrode 300 is formed on the first dielectric layer 210, and the shielding electrode 300 is lower than the top of the trench.
Specifically, after filling the electrode material of the shielding electrode into the trench 100a, the electrode material in the trench may be etched by using an etch-back process to reduce the height of the electrode, so as to form the shielding electrode 300. The material of the shield electrode 300 includes, for example, polysilicon.
In step S300, referring to fig. 5 specifically, the first dielectric layer 210 is etched to remove a portion of the first dielectric layer 210 higher than the shielding electrode 300, and the top of the shielding electrode 300 protrudes from the top of the etched first dielectric layer.
Specifically, the first dielectric layer 210 may be etched by using a dry etching process, or the first dielectric layer 210 may be etched by using a wet etching process. After the portion of the first dielectric layer 210 higher than the shield electrode 300 is removed, the sidewall of the upper portion of the trench may be exposed, and a second dielectric layer (i.e., a gate dielectric layer) may be formed on the exposed sidewall of the trench in a subsequent process. In order to ensure that the first dielectric layer 210 above the shielding electrode can be sufficiently removed, the first dielectric layer 210 is usually over-etched, so that the top of the etched first dielectric layer 210 is lower than the top of the shielding electrode 300, and accordingly the top of the shielding electrode 300 protrudes.
In this embodiment, after etching the first dielectric layer 210 and before forming the second dielectric layer, the method further includes: the exposed sidewalls of the trench 110a are oxidized to form a sacrificial oxide layer, and then the sacrificial oxide layer is removed to repair the etching damage of the trench sidewalls.
In step S400, referring specifically to fig. 6, an oxidation process is performed to form a second dielectric layer 220 (i.e., a gate dielectric layer) on the sidewalls of the trench 110a higher than the first dielectric layer 210, and to oxidize the protruding portion of the shield electrode 300 to form a first isolation layer 410, wherein a gap is formed between the first isolation layer 410 and the trench sidewalls.
In this embodiment, the second dielectric layer 220 and the first isolation layer 410 may be formed simultaneously in the same oxidation process. In the process of oxidizing the protruding portion of the shielding electrode 300, the top surface of the protruding portion of the shielding electrode 300 and the sidewall of the protruding portion of the shielding electrode 300 are oxidized, and the corner position where the protruding portion of the shielding electrode 300 meets the first dielectric layer 210 is easily oxidized insufficiently to generate only a thin oxide, so that the oxidized thickness at the bottom position of the sidewall of the protruding portion is smaller than the oxidized thickness at the top position of the sidewall of the protruding portion, and a space recessed toward the shielding electrode 300 is generated in the gap between the first isolation layer 410 and the second dielectric layer 220, for example, in this embodiment, a sharp-corner-shaped gap (a sharp-corner region shown by a dashed-line frame in fig. 6) pointing to the shielding electrode 300 is generated in the gap between the first isolation layer 410 and the second dielectric layer 220, and the sharp-corner-shaped gap is also located at the corner position where the first dielectric layer 210 and the first isolation layer 410 are connected to each other.
In step S500, referring specifically to fig. 7, a second isolation layer 420 is formed, and a material of the second isolation layer 420 has fluidity under a predetermined condition to fill at least a bottom of the gap.
As described above, a sharp corner region directed to shielding electrode 300 is generated in the gap between first isolation layer 410 and second dielectric layer 220, and the sharp corner region is located at the bottom of the gap, so that second isolation layer 420 having fluidity in a flowing state can fill at least the bottom of the gap, and accordingly, the sharp corner region. Therefore, on one hand, the phenomenon that a subsequently formed gate electrode fills the sharp-angled region to generate a sharp-angled structure can be avoided; on the other hand, the filled second isolation layer 420 may also be used to compensate for the thickness of the spacers in the sharp corner regions, improving the isolation effect between the gate electrode and the shield electrode 300.
In this embodiment, the liquid insulating material filled in the gap is not higher than the top of the gap (i.e., not higher than the top of the first isolation layer 410), as long as it is ensured that the liquid insulating material can fill the gap in the shape of the sharp corner at the bottom of the gap. In addition, since the filling height of the liquid insulating material in the gap is not higher than the top of the gap, the top surface of the second isolation layer 420 formed by the insulating material after curing in the gap presents a concave arc surface.
In a specific example, the preparation method of the second isolation layer 420 includes: a liquid insulating material is spin-coated to fill at least the bottom of the gap and cured to form the second isolation layer 420.
In an alternative embodiment, the liquid insulating material used comprises, for example, siloxane (R) n Si(OH) 4-n ) The siloxane type masking liquid can better fill narrow gaps, has stronger filling capacity, generates dehydration reaction during curing, can generate a film with the main component of silicon oxide, and realizes better electrical isolation capacity. Specifically, a coating process may be preferentially adopted to spin-coat the liquid silicone-containing insulating material, which fills at least the sharp corner regions at the bottom of the gap, wherein the coating thickness of the liquid silicone-containing insulating material may be selected according to practical requirements, and may be selected in a thickness range of 200 angstroms to 6000 angstroms, for example. Thereafter, an annealing curing process is performed, for example, the annealing curing may be performed at 400 to 500 ℃ under an inert gas atmosphere, so that the siloxane undergoes a dehydration reaction to form a solid oxide film (i.e., the second isolation layer 420). The inert gas used includes, for example, nitrogen or argon.
In step S600, referring specifically to fig. 8, a gate electrode 500 is formed in the trench 100a, the gate electrode 500 being located on the first isolation layer 410 and the second isolation layer 420. The gate electrode 500 and the shield electrode 300 may be formed of the same material, for example, the gate electrode 500 and the shield electrode 300 may both include polysilicon.
As described above, the gate electrode 500 is formed without a pointed structure directed to the shield electrode 300 with compensation of the second isolation layer 420, and it is advantageous to increase the thickness of the isolation layer at the pointed corners of the gate electrode 500 and the shield electrode 300. In this embodiment, since the top surface of the second isolation layer 420 in the gap is an arc surface, the bottom surface of the gate electrode 500 at the gap position is correspondingly made to be an arc surface.
Further, after the gate electrode 500 is formed, it may further include: source regions are formed in the substrate on both sides of the trench 100a. The source region may be formed by an ion implantation process.
Based on the manufacturing method shown above, the structure of the formed shielded gate field effect transistor is explained below with reference to fig. 8. As shown in fig. 8, the fabrication of the formed shielded gate field effect transistor includes: a trench formed in the substrate 100; a shield electrode 300 formed in a lower portion of the trench; a gate electrode 500 formed in an upper portion of the trench; and a first isolation layer 410 and a second isolation layer 420 between the shield electrode 300 and the gate electrode 500.
Further, a first dielectric layer 210 is formed on the bottom and the sidewall of the trench, and the first dielectric layer 210 specifically covers the inner surface of the lower portion of the trench. And a second dielectric layer 220 (i.e., a gate dielectric layer) is further formed on the sidewall of the upper portion of the trench, wherein the second dielectric layer 220 is located above the first dielectric layer 210 and connected to the first dielectric layer 210.
Furthermore, the shielding electrode 300 is formed on the first dielectric layer 210, and the top of the shielding electrode 300 protrudes from the first dielectric layer 210.
As shown with continued reference to fig. 8, a first isolation layer 410 is formed on the top surface and sidewalls of the protruding portion of the shielding electrode 300. Specifically, the thickness of the first isolation layer 410 at the bottom position of the sidewall of the protrusion is smaller than the thickness of the first isolation layer 410 at the top position of the sidewall of the protrusion, so that a pointed region in the shape of a pointed angle is defined by the first isolation layer 410 at the bottom position of the sidewall of the protrusion. That is, the thickness of the first isolation layer 410 at the corner position where the first dielectric layer 210 is connected is small, so that a sharp corner region pointing to the shielding electrode 300 is formed at the corner position where the first isolation layer 410 and the first dielectric layer 210 are connected.
And a second isolation layer 420 is filled in a gap between the first isolation layer 410 and the second dielectric layer 220. Specifically, the second isolation layer 420 at least fills the bottom of the gap, and further fills the sharp corner region at the bottom of the sidewall of the protruding portion, thereby forming a sharp corner structure pointing to the shielding electrode 300. By filling the sharp corner region, the gate electrode 500 can be prevented from filling the sharp corner region, so that the gate electrode 500 does not have a sharp corner structure pointing to the shielding electrode 300, and the leakage current phenomenon of the device is improved; in addition, the isolation thickness at the bottom of the sidewall of the protruding portion can be compensated, and the isolation effect between the gate electrode 500 and the shield electrode 300 can be improved.
In this embodiment, the top surface of the second isolation layer 420 filled in the gap is not higher than the top surface of the first isolation layer 410, and the second isolation layer 420 is formed by using a liquid insulating material in a flowing state, so that the top surface of the prepared second isolation layer 420 in the gap can be an arc-shaped surface which is concave, and the bottom surface of the corresponding adjustment gate electrode 500 at the position of the gap is an arc-shaped bottom surface.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention will still fall within the protection scope of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense.
Claims (10)
1. A method for manufacturing a shielded gate field effect transistor, comprising:
providing a substrate, wherein a groove is formed in the substrate, and a first dielectric layer is formed on the bottom and the side wall of the groove;
forming a shielding electrode on the first dielectric layer, wherein the shielding electrode is lower than the top of the groove;
etching the first dielectric layer to remove the part of the first dielectric layer, which is higher than the shielding electrode, and enabling the top of the shielding electrode to protrude out of the top of the etched first dielectric layer;
performing an oxidation process to form a second dielectric layer on the side wall of the groove higher than the first dielectric layer, and oxidizing the protruding part of the shielding electrode to form a first isolation layer, wherein a gap is formed between the first isolation layer and the second dielectric layer;
forming a second isolation layer of a material that is flowable under predetermined conditions to fill at least a bottom of the gap; and the number of the first and second groups,
forming a gate electrode in the trench, the gate electrode being on the first isolation layer and the second isolation layer.
2. The method of claim 1, wherein a top surface of the second spacer filled in the gap is not higher than a top surface of the first spacer.
3. The method of claim 2, wherein a top surface of the second spacer within the gap is a concave curved surface, and a bottom surface of the gate electrode at the position of the gap is correspondingly a curved bottom surface.
4. The method of manufacturing a shielded gate field effect transistor according to claim 1, wherein the method of forming the second spacer layer comprises: and spin-coating a liquid insulating material to fill at least the bottom of the gap, and curing the liquid insulating material to form the second isolation layer.
5. The method of making a shielded gate field effect transistor according to claim 4 wherein said liquid insulating material comprises siloxane.
6. The method of fabricating a shielded gate field effect transistor according to claim 5 wherein the step of curing the liquid insulating material comprises: and annealing and curing under inert gas at 400-500 deg.c.
7. The method of fabricating a shielded gate field effect transistor according to claim 5 wherein the step of curing the liquid insulating material comprises: and annealing and curing under the atmosphere of nitrogen or argon.
8. A shielded gate field effect transistor comprising:
a substrate having a trench formed therein;
the first dielectric layer is formed at the bottom and the side wall of the groove;
the shielding electrode is formed on the first dielectric layer, and the top of the shielding electrode protrudes out of the first dielectric layer;
the second dielectric layer is formed on the side wall of the groove higher than the first dielectric layer;
a first isolation layer formed on a top surface and sidewalls of the projection of the shield electrode;
the second isolation layer is filled in a gap between the first isolation layer and the second dielectric layer;
and the gate electrode is filled in the groove and is positioned on the first isolation layer and the second isolation layer.
9. The shielded gate field effect transistor of claim 8 wherein the top surface of said second spacer filled in the gap is no higher than the top surface of said first spacer, and wherein the top surface of said second spacer in the gap is a concave curved surface, and wherein the bottom surface of said gate electrode at the position of the gap correspondingly presents a curved bottom surface.
10. The shielded gate field effect transistor of claim 8 wherein a pointed region is formed at a corner location where said first spacer and said first dielectric layer meet and directed toward said shield electrode, said second spacer filling said pointed region.
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| CN202211493315.5A CN115910764A (en) | 2022-11-25 | 2022-11-25 | Shielded gate field effect transistor and preparation method thereof |
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