CN112466933B - Shielded gate field effect transistor and forming method thereof - Google Patents

Shielded gate field effect transistor and forming method thereof Download PDF

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CN112466933B
CN112466933B CN202110150812.4A CN202110150812A CN112466933B CN 112466933 B CN112466933 B CN 112466933B CN 202110150812 A CN202110150812 A CN 202110150812A CN 112466933 B CN112466933 B CN 112466933B
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oxide layer
field effect
effect transistor
trench
layer
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CN112466933A (en
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袁家贵
何云
马平
黄艳
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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SMIC Manufacturing Shaoxing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a shielded gate field effect transistor and a forming method thereof. The gate oxide layer is prepared by combining a thermal oxidation process and a deposition process, the whole thickness of the gate oxide layer is favorably reduced, and the thickness of the oxide layer at the corner position is improved by depositing the oxide layer based on high covering performance, so that the problem that the turn-on voltage of a device and the leakage current of the device are mutually restricted in the prior art can be effectively solved, and the voltage resistance of the device is improved.

Description

Shielded gate field effect transistor and forming method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate field effect transistor and a forming method thereof.
Background
A Shielded Gate field effect transistor (SGT) is more advantageous for flexible application of a semiconductor integrated circuit because it has a low Gate-drain capacitance Cgd, a very low on-resistance, and a high withstand voltage. Particularly, in the shielded gate field effect transistor, the shielding electrode is arranged below the gate electrode, so that the gate-drain capacitance can be greatly reduced, and the drift region of the shielded gate field effect transistor also has higher impurity carrier concentration, so that the shielded gate field effect transistor can provide additional benefits for the breakdown voltage of a device, and correspondingly can reduce the on-resistance.
In some application scenarios, a low voltage shielded gate field effect transistor is required, and the low voltage shielded gate field effect transistor generally needs to have a lower turn-on voltage. At present, the following problems are faced when realizing the ground turn-on voltage of the low-voltage shielded gate field effect transistor:
1. when the thickness of a gate oxide layer of a transistor is reduced to reduce the starting voltage (Vth), the leakage current phenomenon between a gate source and a grid source can be further caused;
2. when the turn-on voltage (Vth) is reduced by reducing the ion concentration in the body region of the transistor, a large leakage current is generated between the source and drain of the device.
Disclosure of Invention
The invention aims to provide a method for forming a shielded gate field effect transistor, which aims to solve the problem that the phenomena of the starting voltage of a device and the leakage current of the device are mutually restricted.
To solve the above technical problem, the present invention provides a method for forming a shielded gate field effect transistor, comprising:
providing a substrate and forming a groove in the substrate;
forming a shield electrode in a lower portion of the trench and forming an isolation layer on the shield electrode;
forming a gate oxide layer in an upper portion of the trench, comprising: performing a thermal oxidation process to form a thermal oxide layer on the exposed sidewall of the trench; and performing a low-pressure deposition process to form a deposited oxide layer, wherein the deposited oxide layer covers the thermal oxide layer, the isolation layer and the corner position where the thermal oxide layer is connected with the isolation layer; and the number of the first and second groups,
a gate electrode is filled in an upper portion of the trench.
Optionally, the method for performing a low pressure deposition process to form a deposited oxide layer includes: the low pressure deposition process is performed using tetraethylorthosilicate as the silicon source.
Optionally, after the performing the low pressure deposition process, the method further includes: and performing a heat treatment process to densify the deposited oxide layer.
Optionally, a thermal oxidation process is performed to prepare the thermal oxide layer at a target thickness less than 500 a, and/or a low pressure deposition process is performed to form the deposited oxide layer at a target thickness greater than 100 a.
Optionally, a sum of thicknesses of the thermal oxide layer and the deposited oxide layer above corner locations is less than 600 a.
Optionally, the method for forming the shielded gate field effect transistor further includes: forming a body region in the substrate, the body region having a lateral boundary extending to a trench sidewall, and the body region having an ion concentration of 9E12 atoms/cm3~1.1E13 atoms/cm3。
The present invention also provides a shielded gate field effect transistor comprising:
a substrate having a trench formed therein;
a shield electrode formed in a lower portion of the trench;
an isolation layer formed on the shielding electrode;
the gate oxide layer is formed in the upper part of the groove and comprises a thermal oxide layer and a deposited oxide layer, the thermal oxide layer is formed on the side wall of the upper part of the groove, and the deposited oxide layer covers the thermal oxide layer, the isolation layer and the corner position where the thermal oxide layer is connected with the isolation layer; and the number of the first and second groups,
and the gate electrode is filled in the upper part of the groove.
Optionally, the thermal oxide layer has a thickness above the corner locations that is less than 500 a, and/or the deposited oxide layer has a thickness above 100 a.
Optionally, a sum of thicknesses of the thermal oxide layer and the deposited oxide layer above corner locations is less than 600 a.
Optionally, the threshold voltage of the shielded gate field effect transistor is less than or equal to 2V.
In the forming method of the shielded gate field effect transistor, the gate oxide layer is prepared by combining the thermal oxidation process and the deposition process, so that the thickness of the oxide layer at the corner position is increased by using the deposited oxide layer to improve the leakage current phenomenon of the device, and at the moment, the sum of the thicknesses of the thermal oxide layer and the deposited oxide layer at the position higher than the corner position is favorably reduced, and further, the starting voltage of the device is reduced. Namely, the shielded gate field effect transistor prepared based on the forming method provided by the invention can further ensure the thickness of the gate oxide layer at the corner position on the basis of reducing the thickness of the gate oxide layer on the side wall of the groove, effectively overcomes the problem that the turn-on voltage of the device and the leakage current of the device are mutually restricted in the prior art, and improves the voltage resistance of the device.
Drawings
Fig. 1 is a schematic structural diagram of reducing the thickness of a gate oxide layer to reduce the turn-on voltage.
Fig. 2 is a flow chart illustrating a method for forming a shielded gate field effect transistor according to an embodiment of the invention.
Fig. 3-8 are schematic structural diagrams illustrating a method for forming a shielded gate field effect transistor in a manufacturing process according to an embodiment of the invention.
Wherein the reference numbers are as follows: 10-a gate oxide layer; 11-corner position; 100-a substrate; 110-a trench; 210-a shielding dielectric layer; 220-a shield electrode; 300-an isolation layer; 400-a gate oxide layer; 410-thermal oxidation layer; 420-depositing an oxide layer; 500-a gate electrode; 600-a mask layer; 610-a first oxide layer; 620-a nitride layer; 630-second oxide layer.
Detailed Description
As described in the background, in order to reduce the turn-on voltage of the shielded gate field effect transistor, one method is to reduce the thickness of the gate oxide layer, and the other method is to reduce the ion concentration of the body region, however, both methods can reduce the turn-on voltage of the device and induce the leakage current phenomenon of the device.
Fig. 1 is a schematic structural diagram of reducing the thickness of a gate oxide layer to reduce the turn-on voltage. As shown in fig. 1, a gate oxide layer 10 with a small thickness is formed, so that the formed shielded gate field effect transistor has a low turn-on voltage. However, due to the required thin thickness of the gate oxide layer 10, incomplete oxidation often occurs at the corner positions 11 when performing the oxidation process for preparation (for example, the sidewalls of the corner positions are difficult to be fully contacted with oxygen), which may result in the gate oxide layer thickness at the corner positions 11 being too small, and thus, a large gate-source leakage current (I) is inducedGS) To a problem of (a).
Although the turn-on voltage of the device can be reduced (for example, from 2.0V to 1.6V) by reducing the ion concentration of the body region, the depletion boundary is further expanded to the source region when the body junction is depleted, so that larger source and drain leakage current (I) is generatedDS) E.g. by causing leakage current (I) between source and drainDS) 1000nA is achieved, power consumption of the device is increased, and voltage resistance of the device is reduced.
Therefore, the thickness of the gate oxide layer or the ion concentration of the body region cannot be reduced without limit in consideration of the leakage current phenomenon of the device. In other words, the existing method is difficult to balance the problems of the turn-on voltage and the leakage current of the device.
Therefore, the invention provides a method for forming a shielded gate field effect transistor, which can reduce the turn-on voltage of a device under the condition of ensuring the leakage current and voltage resistance of the device. Specifically, referring to fig. 2, the method for forming the shielded gate field effect transistor includes:
step S100, providing a substrate and forming a groove in the substrate;
step S200, forming a shielding electrode in the lower part of the groove, and forming an isolation layer on the shielding electrode;
step S300, forming a gate oxide layer in an upper portion of the trench, including: performing a thermal oxidation process to form a thermal oxide layer on the exposed sidewall of the trench; and performing a low pressure deposition process to form a deposited oxide layer covering the thermal oxide layer and the isolation layer;
step S400, filling a gate electrode in an upper portion of the trench.
The forming method of the shielded gate field effect transistor combines the thermal oxidation process and the low-pressure deposition process to form the gate oxide layer together, thereby being beneficial to reducing the thickness of the gate oxide layer and avoiding the problem that the oxide layer is too thin at the corner position close to the isolation layer. Therefore, the reduction of the starting voltage is realized, and the leakage current phenomenon which is easy to appear in the prior art is improved.
The shielded gate field effect transistor and the method for forming the same according to the present invention will be described in detail with reference to fig. 3 to 8. Fig. 3 to 8 are schematic structural diagrams of a method for forming a shielded gate field effect transistor in an embodiment of the invention during a manufacturing process thereof. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In step S100, as shown with particular reference to fig. 3, a substrate 100 is provided and a trench 110 is formed in the substrate 100. In the subsequent process, the trench 110 is utilized to sequentially accommodate the shield electrode and the gate electrode from bottom to top.
Specifically, the forming method of the trench 110 includes, for example: first, a mask layer 600 is formed on the top surface of the substrate 100 to define the pattern of the trench by using the mask layer 600; next, the substrate 100 is etched using the mask layer 600 as a mask to form the trench 110. The mask layer 600 may be a stacked structure formed by stacking a plurality of film layers. Specifically, the mask layer 600 includes a first silicon oxide layer 610, a nitride layer 620, and a second silicon oxide layer 630 sequentially formed on the top surface of the substrate 100.
In this embodiment, the sidewall of the trench 110 may be a vertical sidewall or a sidewall close to the vertical sidewall. That is, the inclination angle of the side wall of the groove 110 with respect to the height direction is small, for example, the inclination angle is 5 ° or less, and even the inclination angle may be further 1 ° or less. Note that the "inclination angle of the sidewall of the trench 110 with respect to the height direction" described herein is: the angle between the sidewall of the trench 110 and the height direction.
In step S200, referring to fig. 4 and 5 in particular, a shielding electrode 220 is formed in a lower portion of the trench 110, and an isolation layer 300 is formed on the shielding electrode 220, wherein the isolation layer 300 covers the shielding electrode 220.
Further, a shielding dielectric layer 210 is formed between the shielding electrode 220 and the inner wall of the trench 110. Specifically, the method for forming the shielding dielectric layer 210 and the shielding electrode 220 may include the following steps.
In a first step, specifically referring to fig. 4, a shielding dielectric layer 210 is formed on the inner wall of the trench 110. That is, the shielding dielectric layer 210 covers the bottom and sidewalls of the trench 110.
The shielding dielectric layer 210 may be formed by a thermal oxidation process, and the material of the formed shielding dielectric layer 210 may include silicon oxide. And the thickness of the shielding dielectric layer 210 can be adjusted correspondingly according to the requirement of the withstand voltage of the formed shielded gate field effect transistor.
In the second step, an electrode material layer is filled in the trench 110, and the trench 110 may be filled with the electrode material layer. The electrode material layer may be formed using a deposition process, and may include, for example, polysilicon.
And a third step, continuing to refer to fig. 4, of etching the electrode material layer to reduce the height of the electrode material layer, so as to form the shielding electrode 220. At this time, under the protection of the shielding dielectric layer 210, the sidewall of the trench can be prevented from being exposed when the electrode material layer is etched back, and thus the sidewall of the trench is prevented from being damaged by etching.
In a further aspect, a portion of the shielding dielectric layer 210 above the shielding electrode 220 may be removed continuously. Specifically, the shielding dielectric layer 210 may be partially removed by using a dry etching process, or the shielding dielectric layer 210 may be partially removed by using a wet etching process.
Referring next to fig. 5, after forming the shield electrode 220, an isolation layer 300 may be formed in the trench 110. The method for forming the isolation layer 300 specifically includes: first, a High Density Plasma (HDP) process is used to fill the trench 110 with an isolation material layer (wherein the isolation material layer includes, for example, silicon oxide); next, the isolation material layer is etched to partially remove the isolation material layer, and an isolation layer 300 is formed using the remaining isolation material layer, the isolation layer 300 covering the top surface of the shielding electrode 300.
In step S300, and with particular reference to fig. 6 and 7, a gate oxide layer 400 is formed comprising: performing a thermal oxidation process to form a thermal oxide layer 410 on the exposed sidewalls of the trench 110; and performing a low pressure deposition process to form a deposited oxide layer 420, wherein the deposited oxide layer 420 covers the thermal oxide layer 410, the isolation layer 300, and corner positions where the thermal oxide layer 410 and the isolation layer 300 meet.
The thermal oxide layer 410 formed by the thermal oxidation process has high density and can effectively ensure the dielectric constant of the gate oxide layer 400. And, when the deposited oxide layer 420 is formed by using the low pressure deposition process, the formed deposited oxide layer 420 can have a higher coverage performance at the corner where the thermal oxide layer 410 and the isolation layer 300 meet because of its better step coverage capability and film uniformity, thereby preventing the thickness of the oxide layer at the corner from being too small.
Referring specifically to fig. 6, when a thermal oxidation process is performed to form the thermal oxide layer 410, since the trench sidewall at the corner position is difficult to be sufficiently contacted with oxygen, the thickness of the oxide layer formed at the corner position is thinner than the thickness of the oxide layer at other positions higher than the corner position. In particular, for a shielded gate field effect transistor, the isolation layer 300 exists in the trench 110, and when a thermal oxidation process is performed, the isolation layer 300 does not form an oxide thereon, and is not favorable for oxygen to diffuse to the adjacent trench sidewall (i.e., corner position), thereby further resulting in that the thickness of the oxide layer at the corner position is much smaller than that at other sidewall positions. Furthermore, when the trench sidewall of the trench 110 is a vertical sidewall or a sidewall close to the vertical sidewall, this further aggravates the problem of the over-thinning of the oxide layer at the corner position.
For example, the thickness of the thermal oxide layer 410 may be up to 500 a above the corner location, however the thickness of the thermal oxide layer 410 at the corner location may be approximately only 120 a-170 a. Whereas when the oxide layer thickness at the corner locations is lower than 150 a, the leakage current between the gate sources will not be negligible, so when forming a gate oxide layer in the prior art by means of a thermal oxidation process only, the gate oxide layer needs to be prepared with a target thickness higher than 500 a, even if the target thickness needs to be higher than 600 a, which cannot be further reduced.
Of course, in this embodiment, since the deposited oxide layer 420 is also continuously prepared after the thermal oxide layer 410 is formed to compensate for the thickness of the upper gate oxide layer 400, a thermal oxidation process may be performed to prepare the thermal oxide layer 410 at a target thickness that is lower than 500 a when the thermal oxide layer 410 has a thickness above the bottom corner location that is less than 500 a and has a target thickness or is close to the target thickness; and the thickness of the thermal oxide layer 410 at the corner position is less than the target thickness. In this embodiment, a thickness of 200A-400A, for example, is the target thickness, or a thickness of 250A-350A may be further used as the target thickness, at which time the thickness of the thermal oxide layer 410 at corner locations is greater than 50A, for example, approximately 60A-100A.
Referring next to fig. 7, a deposited oxide layer 420 is formed by performing a low pressure deposition process, and the deposited oxide layer 420 may uniformly cover the thermal oxide layer 410, the isolation layer 300, and the corner positions where the thermal oxide layer 410 meets the isolation layer 300. That is, in the present embodiment, the thickness of the corner position is compensated by the deposited oxide layer 420 with better coverage and film uniformity, so as to improve the problem of gate-source leakage current caused by too thin oxide layer at the corner position.
It is appreciated that the deposited oxide layer 420, which has better coverage and film uniformity, has substantially similar film thickness at each location. For example, the deposited oxide layer 420 has a thickness of approximately 200 a over the thermal oxide layer 410, then typically also has a thickness of approximately 200 a at the corner locations, even since the deposited oxide layer 420 is also deposited over the isolation layer 300, and thus may have a thickness greater than 200 a at the adjoining corner locations.
In this embodiment, a low pressure deposition process is performed to form the deposited oxide layer 420 with a target thickness of greater than 100 a, and accordingly the thickness of the formed deposited oxide layer 420 may be greater than 100 a, at which time the thickness of the deposited oxide layer 420 at corner locations is also correspondingly greater than 100 a. For example, the deposited oxide layer 420 may be formed to a thickness further greater than 200A, or greater than or equal to 300A. In particular, the sum of the thicknesses of the thermal oxide layer 410 and the deposited oxide layer 420 above the corner locations may be controlled to be less than 600 a to achieve a lower turn-on voltage for the finally formed transistor (e.g., the turn-on voltage of the device may be reduced to less than 2V, or even further reduced to 1.6 +/-0.3V).
Further, the low pressure deposition process forms the deposited oxide layer 420, and particularly, the low pressure deposition process (LP-TEOS) is performed with Tetraethylorthosilicate (TEOS) as a silicon source. The process of forming the deposited oxide layer 420 by using LP-TEOS is, for example: at high temperatures (e.g., above 700 ℃), TEOS decomposes to form silica. The decomposition formula for TEOS decomposition is, for example:
Si(OC2H5)4 → SiO2 +4C2H4 +2H2O
it should be appreciated that in the LP-TEOS process, the deposited oxide layer 420 is formed under high temperature conditions, and thus it is advantageous to improve the compactness of the formed deposited oxide layer 420. In addition, the LP-TEOS process can be a furnace tube process, and an ion bombardment process does not exist, so that bombardment ions are prevented from existing in the formed oxide layer.
In a further aspect, after forming the deposited oxide layer 420, the method further includes: a thermal treatment process is performed to further densify the deposited oxide layer 420 such that the deposited oxide layer 420 formed by the deposition process can be closer in structure and performance to the thermal oxide layer 410 formed by thermal oxidation.
In step S400, as shown with particular reference to fig. 8, a gate electrode 500 is filled in an upper portion of the trench 110. The material of the gate electrode 500 includes, for example, polysilicon.
Further, the method for forming the shielded gate field effect transistor further comprises: a body region (not shown) and a source region (not shown) are formed in the substrate 100. The lateral boundary of the body region extends to the trench sidewall, and the body region has an ion concentration of, for example, 9E12 atoms/cm3~1.1E13 atoms/cm3。
The structure of the shielded gate field effect transistor prepared based on the above-described formation method is described in detail below. Referring specifically to fig. 8, the shielded gate field effect transistor includes: a trench 110 formed in the substrate 100; a shield electrode 220 formed in a lower portion of the trench 110; a gate oxide layer 400 and a gate electrode 500 formed in an upper portion of the trench 110; and an isolation layer 300 between the shield electrode 220 and the gate electrode 500.
Wherein the gate oxide layer 400 includes a thermal oxide layer 410 and a deposited oxide layer 420. The thermal oxide layer 410 is formed on the upper sidewall of the trench 110 by a thermal oxidation process. The deposited oxide layer 420 is formed by a low pressure deposition process and covers the thermal oxide layer 410, the isolation layer 300, and the corner position where the thermal oxide layer 410 and the isolation layer 300 are connected.
As described above, the gate oxide layer 400 in the present embodiment includes not only the thermal oxide layer 410 formed by the thermal oxidation process, but also the deposited oxide layer 420 formed by the low pressure deposition process. The deposited oxide layer 420 formed by the low-pressure deposition process has better coverage performance and film uniformity, so that the thickness of the oxide layer at the corner position where the thermal oxide layer 410 is connected with the isolation layer 300 can be effectively ensured, and the leakage current phenomenon of the device can be further improved. Based on this, the thickness of the thermal oxide layer 410 is allowed to decrease further (e.g., the thickness of the thermal oxide layer 410 above the corner locations may be made less than 500 a) and the thickness of the gate oxide layer 400 may be further compensated for with a thinner deposited oxide layer 420 (e.g., the thickness of the deposited oxide layer 420 may be made greater than 100 a). At this point, it is advantageous on the one hand to reduce the sum of the thicknesses of the thermal oxide layer 410 and the deposited oxide layer 420 above the corner locations (e.g., the sum of the thicknesses of the thermal oxide layer 410 and the deposited oxide layer 420 above the corner locations may be made less than 600 a) to achieve a low on-voltage for the device; on the other hand, the oxide layer thickness at the corner locations may be compensated for based on a high coverage performance deposited oxide layer 420 (e.g., the oxide layer thickness at the corner locations may be made higher than 150 a).
The following specific example further illustrates the advantages provided by the shielded gate field effect transistor in this embodiment. When the thermal oxide layer is lowered from above 500 a to 300 a, i.e., the turn-on voltage of the device is correspondingly lowered by about 0.9V, while when an oxide layer 420 of 100 a-200 a is superimposed, the turn-on voltage of the device is correspondingly raised by about 0.3V, thereby achieving a reduction in the turn-on voltage of the device as a whole (i.e., a reduction of about 0.6V).
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims (10)

1. A method of forming a shielded gate field effect transistor, comprising:
providing a substrate and forming a groove in the substrate;
forming a shield electrode in a lower portion of the trench and forming an isolation layer on the shield electrode;
forming a gate oxide layer in an upper portion of the trench, comprising: performing a thermal oxidation process to form a thermal oxidation layer on the exposed side wall of the trench, wherein the thickness of the bottom position of the thermal oxidation layer is smaller than the thickness of other positions above the bottom position; and performing a low-pressure deposition process to form a deposited oxide layer, wherein the deposited oxide layer covers the thermal oxide layer, the isolation layer and the corner position where the thermal oxide layer is connected with the isolation layer; and the number of the first and second groups,
a gate electrode is filled in an upper portion of the trench.
2. The method of claim 1, wherein performing a low pressure deposition process to form a deposited oxide layer comprises: the low pressure deposition process is performed using tetraethylorthosilicate as the silicon source.
3. The method of forming a shielded gate field effect transistor according to claim 1 further comprising, after performing the low pressure deposition process: and performing a heat treatment process to densify the deposited oxide layer.
4. The method of forming a shielded gate field effect transistor of claim 1 wherein a thermal oxidation process is performed to produce the thermal oxide layer at a target thickness less than 500 a and/or a low pressure deposition process is performed to form the deposited oxide layer at a target thickness greater than 100 a.
5. The method of forming a shielded gate field effect transistor of claim 1 wherein the sum of the thicknesses of the thermal oxide layer and the deposited oxide layer above the corner locations is less than 600 a.
6. The method of forming a shielded gate field effect transistor according to claim 1 further comprising: forming a body region in the substrate, a lateral boundary of the body region extending to a trench sidewall, andthe ion concentration of the body region is 9E12 atoms/cm3~1.1E13 atoms/cm3。
7. A shielded gate field effect transistor comprising:
a substrate having a trench formed therein;
a shield electrode formed in a lower portion of the trench;
an isolation layer formed on the shielding electrode;
the gate oxide layer is formed in the upper part of the trench and comprises a thermal oxide layer and a deposited oxide layer, the thermal oxide layer is formed on the side wall of the upper part of the trench, the thickness of the bottom position of the thermal oxide layer is smaller than that of other positions above the bottom position, and the deposited oxide layer covers the thermal oxide layer, the isolation layer and the corner position where the thermal oxide layer is connected with the isolation layer; and the number of the first and second groups,
and a gate electrode filled in an upper portion of the trench.
8. The shielded gate field effect transistor of claim 7 wherein the thermal oxide layer has a thickness above the corner locations that is less than 500A and/or the deposited oxide layer has a thickness greater than 100A.
9. The shielded gate field effect transistor of claim 7 wherein the sum of the thicknesses of the thermal oxide layer and the deposited oxide layer above the corner locations is less than 600A.
10. The shielded gate field effect transistor of claim 7 wherein the shielded gate field effect transistor has a threshold voltage of 2V or less.
CN202110150812.4A 2021-02-04 2021-02-04 Shielded gate field effect transistor and forming method thereof Active CN112466933B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6071794A (en) * 1999-06-01 2000-06-06 Mosel Vitelic, Inc. Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator
US6444528B1 (en) * 2000-08-16 2002-09-03 Fairchild Semiconductor Corporation Selective oxide deposition in the bottom of a trench
US6551900B1 (en) * 1999-12-09 2003-04-22 Yifu Chung Trench gate oxide formation method
US10749006B2 (en) * 2019-01-11 2020-08-18 Leadpower-Semi Co., Ltd. Trench power transistor and method of producing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6071794A (en) * 1999-06-01 2000-06-06 Mosel Vitelic, Inc. Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator
US6551900B1 (en) * 1999-12-09 2003-04-22 Yifu Chung Trench gate oxide formation method
US6444528B1 (en) * 2000-08-16 2002-09-03 Fairchild Semiconductor Corporation Selective oxide deposition in the bottom of a trench
US10749006B2 (en) * 2019-01-11 2020-08-18 Leadpower-Semi Co., Ltd. Trench power transistor and method of producing the same

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