CN111164964B

CN111164964B - Image pickup apparatus and image pickup method

Info

Publication number: CN111164964B
Application number: CN201880064204.8A
Authority: CN
Inventors: 中村良助; 坂野頼人; 铃木敦史
Original assignee: Sony Semiconductor Solutions Corp
Current assignee: Sony Semiconductor Solutions Corp
Priority date: 2017-10-27
Filing date: 2018-10-02
Publication date: 2022-08-16
Anticipated expiration: 2038-10-02
Also published as: JP2023011858A; CN115483236A; KR102489552B1; JP7439213B2; KR20200073212A; WO2019082614A1; JPWO2019082614A1; JP7181887B2; US11122230B2; KR20220165836A; CN111164964A; US20210211599A1; KR102577163B1

Abstract

The disclosed image pickup apparatus includes: the image display device includes a first switch coupling a first light receiving device and a first charge accumulating section to each other, a second switch coupling a predetermined node and the first charge accumulating section to each other, a third switch applying a predetermined voltage to the predetermined node, a fourth switch coupling a second light receiving device and a second charge accumulating section to each other, a fifth switch coupling the second charge accumulating section and the predetermined node to each other, an output section outputting a pixel voltage, a driving section, and a processor determining first to fourth values. The driving part turns on the second and third switches and turns off the first, fourth, and fifth switches in a first period, turns off the third switch and turns on the fifth switch in a second period, turns on the fourth switch in a third period, and turns off the fourth switch in a fourth period. The processor determines the third value based on the pixel voltages in the second and fourth periods.

Description

Image pickup apparatus and image pickup method

Technical Field

The present disclosure relates to an image pickup apparatus that performs an image pickup operation and an image pickup method used in such an image pickup apparatus.

Background

In an image pickup apparatus, a wide dynamic range is desired. For example, patent document 1 discloses an image pickup apparatus including a photodiode and a storage capacitor that accumulates photoelectric charges overflowing from the photodiode and expands a dynamic range.

List of cited documents

Patent document

Patent document 1: japanese unexamined patent application publication No. 2005-328493.

Disclosure of Invention

In an image pickup apparatus, a captured image is desired to have higher image quality, and further improvement in image quality is desired.

It is desirable to provide an image pickup apparatus and an image pickup method capable of improving the image quality of a picked-up image.

An image pickup apparatus according to an embodiment of the present disclosure includes: a first light receiving device and a second light receiving device; a first charge accumulation section and a second charge accumulation section; a first switch; a second switch; a third switch; a fourth switch; a fifth switch; an output section; a drive section; and a processor. The first switch couples the first light receiving device and the first charge accumulating portion to each other by being placed in an on state. The second switch couples the predetermined node and the first charge accumulation section to each other by being placed in an on state. The third switch applies a predetermined voltage to a predetermined node by being placed in an on state. The fourth switch couples the second light receiving device and the second charge accumulating section to each other by being placed in an on state. The fifth switch couples the second charge accumulation section and the predetermined node to each other by being placed in an on state. The driving section drives each switch. The processor determines a first value, a second value, a third value, and a fourth value based on the pixel voltage and generates a pixel value based on the values. In the first period, the above-described driving section places the second switch and the third switch in the on state, and places the first switch, the fourth switch, and the fifth switch in the off state. In a second period after the first period, the driving section places the third switch in an off state and places the fifth switch in an on state. The driving section places the fourth switch in an on state in a third period after the second period, and places the fourth switch in an off state in a fourth period after the third period. The processor determines a third value based on the pixel voltage in the second period and the pixel voltage in the fourth period.

The image pickup method according to the embodiment of the present disclosure includes: driving respective switches of an image pickup pixel including first and second light receiving devices, first and second charge accumulating sections, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and an output section, the first switch coupling the first light receiving device and the first charge accumulating section to each other by being placed in an on state, the second switch coupling the predetermined node and the first charge accumulating section to each other by being placed in an on state, the third switch applying a predetermined voltage to the predetermined node by being placed in an on state, the fourth switch coupling the second light receiving device and the second charge accumulating section to each other by being placed in an on state, the fifth switch coupling the second charge accumulating section and the predetermined node to each other by being placed in an on state, and the output section outputting a pixel voltage corresponding to the voltage in the first charge accumulating section; determining a first value, a second value, a third value, and a fourth value based on the pixel voltage; in the first period, the second switch and the third switch are placed in an on state, and the first switch, the fourth switch, and the fifth switch are placed in an off state; in a second period after the first period, placing the third switch in an off state and placing the fifth switch in an on state; in a third period after the second period, placing the fourth switch in an on state; in a fourth period subsequent to the third period, placing the fourth switch in an off state; and determining a third value based on the pixel voltage in the second period and the pixel voltage in the fourth period.

In the image pickup apparatus and the image pickup method according to the embodiment of the present disclosure, in the first period, the second switch and the third switch are placed in the on state, and the first switch, the fourth switch, and the fifth switch are placed in the off state. In a second period after the first period, the third switch is placed in an off state, and the fifth switch is placed in an on state. In a third period after the second period, the fourth switch is placed in an on state, and in a fourth period after the third period, the fourth switch is placed in an off state. Then, a third value is determined based on the pixel voltage in the second period and the pixel voltage in the fourth period. Then, a pixel value is generated based on the first value, the second value, the third value, and the fourth value.

According to the image pickup apparatus and the image pickup method of the embodiment of the present disclosure, in the first period, the second switch and the third switch are placed in the on state, and the first switch, the fourth switch, and the fifth switch are placed in the off state; in a second period after the first period, the third switch is placed in an off state, and the fifth switch is placed in an on state; in a third period after the second period, the fourth switch is placed in an on state; and in a fourth period after the third period, the fourth switch is placed in an off state, and the third value is determined based on the pixel voltage in the second period and the pixel voltage in the fourth period. This makes it possible to improve the image quality of the captured image. It should be noted that the effect described herein is not restrictive, but may be any effect described in the present disclosure.

Drawings

Fig. 1 is a configuration diagram showing a configuration example of an image pickup apparatus according to an embodiment of the present disclosure.

Fig. 2 is a block diagram showing a configuration example of the readout section shown in fig. 1.

Fig. 3 is a timing waveform diagram showing an operation example of the image pickup apparatus shown in fig. 1.

Fig. 4A is another timing waveform diagram showing an operation example of the image pickup apparatus shown in fig. 1.

Fig. 4B is another timing waveform diagram showing an operation example of the image pickup apparatus shown in fig. 1.

Fig. 5A is a circuit diagram showing an operation state of the image pickup pixel shown in fig. 1.

Fig. 5B is a circuit diagram showing another operation state of the image pickup apparatus shown in fig. 1.

Fig. 5C is a circuit diagram showing another operation state of the image pickup apparatus shown in fig. 1.

Fig. 6 is an explanatory diagram showing an operation example of the image pickup apparatus shown in fig. 1.

Fig. 7 is a characteristic diagram showing a characteristic example of the image pickup apparatus shown in fig. 1.

Fig. 8 is a timing waveform diagram showing an operation example of the image pickup apparatus according to the comparative example.

Fig. 9A is another timing waveform diagram showing an operation example of the image pickup apparatus according to the comparative example.

Fig. 9B is another timing waveform diagram showing an operation example of the image pickup apparatus according to the comparative example.

Fig. 10 is an explanatory diagram showing an operation example of the image pickup apparatus according to the comparative example.

Fig. 11 is a characteristic diagram showing a characteristic example of the image pickup apparatus according to the comparative example.

Fig. 12 is a timing waveform diagram showing an operation example of the image pickup apparatus according to the modification.

Fig. 13 is an explanatory diagram showing an operation example of the image pickup apparatus according to the modification.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

< example >

[ construction example ]

Fig. 1 shows a configuration example of an image pickup apparatus (image pickup apparatus 1) according to an embodiment. The image pickup device 1 is a so-called CMOS image sensor manufactured by a process for manufacturing a CMOS (complementary metal oxide semiconductor) integrated circuit. It should be noted that the image capturing method according to the embodiment of the present disclosure is implemented by the present embodiment, and will therefore be described together. The image pickup apparatus 1 includes a pixel array 11, a scanner 12, a readout section 20, a signal processor 14, and a controller 15.

The pixel array 11 includes a plurality of image pickup pixels 10 arranged in a matrix form. The pixel array 11 includes a plurality of control lines TGLL, a plurality of control lines FDGL, a plurality of control lines RSTL, a plurality of control lines FCGL, a plurality of control lines TGSL, a plurality of control lines SELL, and a plurality of signal lines SGL. The control line TGLL extends in the horizontal direction (the lateral direction in fig. 1), and the signal STGL is applied to the control line TGLL via the scanner 12. The control line FDGL extends in the horizontal direction, and the signal SFDG is applied to the control line FDGL via the scanner 12. The control line RSTL extends in the horizontal direction, and the signal SRST is applied to the control line RSTL via the scanner 12. The control line FCGL extends in the horizontal direction, and the signal SFCG is applied to the control line FCGL through the scanner 12. The control line TGSL extends in the horizontal direction, and the signal STGS is applied to the control line TGSL via the scanner 12. The control line SELL extends in the horizontal direction, and a signal SSEL is applied to the control line SELL via the scanner 12. The signal line SGL extends in the vertical direction (the longitudinal direction in fig. 1) and is coupled to the readout section 20.

Each image pickup pixel 10 includes a photodiode PD1, a transistor TGL, a photodiode PD2, a transistor TGS, a capacitor FC, transistors FCG, RST, and FDG, a floating diffusion FD, and transistors AMP and SEL. In this example, the transistors TGL, TGS, FCG, RST, FDG, AMP, and SEL are N-type MOS transistors.

The photodiode PD1 is a photoelectric converter that generates and accumulates electric charges having an amount corresponding to the amount of received light. The light receiving area capable of receiving light of the photodiode PD1 is larger than that of the photodiode PD 2. The anode of photodiode PD1 is connected to ground and the cathode is coupled to the source of transistor TGL.

The transistor TGL has a gate coupled to a control line TGLL, a source coupled to the cathode of the photodiode PD1, and a drain coupled to the floating diffusion FD.

The photodiode PD2 is a photoelectric converter that generates and accumulates electric charges having an amount corresponding to the amount of received light. The light receiving area capable of receiving light of the photodiode PD2 is smaller than that of the photodiode PD 1. The anode of photodiode PD2 is connected to ground and the cathode is coupled to the source of transistor TGS.

The transistor TGS has a gate coupled to the control line TGSL, a source coupled to the cathode of the photodiode PD2, and a drain coupled to one end of the capacitor FC and the source of the transistor FCG.

One end of the capacitor FC is coupled to the drain of the transistor TGS and the source of the transistor FCG, and the other end is supplied with the power supply voltage VDD.

The transistor FCG has a gate coupled to the control line FCGL, a source coupled to one end of the capacitor FC and a drain of the transistor TGS, and a drain coupled to a source of the transistor RST and a drain of the transistor FDG.

The gate of the transistor RST is coupled to the control line RSTL, the drain is supplied with the power supply voltage VDD, and the source is coupled to the drains of the transistors FCG and FDG.

The gate of the transistor FDG is coupled to a control line FDGL, the drain is coupled to the source of the transistor RST and the drain of the transistor FCG, and the source is coupled to the floating diffusion.

The floating diffusion portion FD accumulates charges supplied from the photodiodes PD1 and PD2, and is configured by using, for example, a diffusion layer formed on the surface of a semiconductor substrate. Fig. 1 shows a floating diffusion FD using a capacitor symbol.

The transistor AMP has a gate coupled to the floating diffusion FD, a drain supplied with the power supply voltage VDD, and a source coupled to a drain of the transistor SEL.

The transistor SEL has a gate coupled to the control line SELL, a drain coupled to the source of the transistor AMP, and a source coupled to the signal line SGL.

With the configuration, in the image pickup pixel 10, the transistor SEL is placed in an on state based on the signal SSEL applied to the control line SELL, thereby electrically coupling the image pickup pixel 10 to the signal line SGL. Therefore, the transistor AMP is coupled to a current source 23 (described later) of the readout section 20, and functions as a so-called source follower. Then, the image pickup pixel 10 outputs a pixel voltage VP corresponding to the voltage in the floating diffusion FD to a signal line SGL as a signal SIG. Specifically, as described below, the image pickup pixel 10 sequentially outputs seven pixel voltages VP (VP to VP7) in seven periods (conversion periods P1 to P7) within a so-called horizontal period H.

The scanner 12 sequentially drives the plurality of image pickup pixels 10 in units of a single row of the image pickup pixels 10 based on an instruction from the controller 15, and is configured by using a shift register, for example. It should be noted that this is not limiting and, for example, an address decoder may be used instead. The scanner 12 applies a signal STGL to a plurality of control lines TGLL, a signal SFDG to a plurality of control lines FDGL, a signal SRST to a plurality of control lines RSTL, a signal SFCG to a plurality of control lines FCGL, a signal STGS to a plurality of control lines TGSL, and a signal SSEL to a plurality of control lines SELL, thereby driving the image pickup pixels 10 of one row.

The readout section 20 performs AD (analog-digital) conversion based on a signal SIG supplied from the pixel array 11 through the signal line SGL to generate a digital value (count value CNT).

Fig. 2 shows a configuration example of the readout part 20. It should be noted that fig. 2 shows the controller 15 and the signal processor 14 in addition to the readout section 20.

The readout section 20 includes a readout controller 28, a reference signal generator 29, and a plurality of AD (analog-digital) converters ADC.

The readout controller 28 controls the readout operation in the readout section 20 based on an instruction from the controller 15. Specifically, the readout controller 28 supplies a control signal to the reference signal generator 29, thereby causing the reference signal generator 29 to generate a reference signal REF (described below). Further, the readout controller 28 supplies the clock signal CLK and the control signal CC to the plurality of AD converters ADC, thereby controlling the a/D conversion operation in the plurality of AD converters ADC.

The reference signal generator 29 generates a reference signal REF based on an instruction from the readout controller 28. As described below, the reference signal REF has a so-called ramp wave (ramp wave) in which the voltage level gradually decreases with time in seven periods (transition periods P1 to P7).

Each AD converter ADC performs AD conversion to convert the pixel voltage VP into a digital value (count value CNT) based on a signal SIG supplied from the pixel array 11 through the signal line SGL. A plurality of AD converters ADC corresponding to the plurality of signal lines SGL of the pixel array 11 are provided.

Each AD converter ADC has

capacitors

21 and 22, a current source 23, a comparator 24, and a counter 25. One end of the capacitor 21 is provided with a reference signal REF, and the other end is coupled to a positive input terminal of the comparator 24. Capacitor 22 has one end coupled to signal line SGL and the other end coupled to the negative input terminal of comparator 24. The current source 23 allows a current having a predetermined current value to flow from the signal line SGL to the ground. A positive input terminal of the comparator 24 is supplied with the reference signal REF through the capacitor 21, and a negative input terminal is supplied with the signal SIG through the capacitor 22. Subsequently, the comparator 24 compares the input voltage at the positive input terminal and the input voltage at the negative input terminal, and outputs the comparison result as a signal CMP. The counter 25 performs a counting operation based on the signal CMP, the clock signal CLK, and the control signal CC. Specifically, the readout controller 28 starts generating the clock signal CLK, thereby causing the counter 25 to start counting of clock pulses in the clock signal CLK and increment the count value CNT. Then, the counter 25 terminates the counting operation based on the signal CMP supplied from the comparator 24. Further, the counter 25 resets the count value CNT based on the control signal CC.

With the configuration, in the readout section 20, each AD converter ADC performs AD conversion based on the signal SIG and outputs the count value CNT. Specifically, each AD converter ADC performs AD conversion based on seven pixel voltages VP1 to VP7 included in the signal SIG in seven conversion periods P1 to P7, and outputs seven count values CNT (count values CNT1 to CNT 7).

The signal processor 14 performs predetermined signal processing based on the count value CNT supplied from the readout section 20, and outputs the signal processing result as the image signal DATA. Specifically, the signal processor 14 generates four images PIC (images PIC1, PIC2, PIC3, and PIC4) based on seven count values CNT1 to CNT7 supplied from the readout section 20. Then, the signal processor 14 synthesizes the four images PIC to generate one captured image PICA. Subsequently, the signal processor 14 outputs the captured image PICA as the image signal DATA. Therefore, in the imaging apparatus 1, the dynamic range can be expanded as follows.

The controller 15 supplies control signals to the scanner 12, the readout section 20, and the signal processor 14, and controls the operations of these circuits, thereby controlling the operation of the image pickup apparatus 1.

Here, the photodiode PD1 corresponds to a specific example of "first light receiving device" of the present disclosure. The photodiode PD2 corresponds to a specific example of "second light receiving device" of the present disclosure. The floating diffusion FD corresponds to a specific example of the "first charge accumulating section" of the present disclosure. The capacitor FC corresponds to a specific example of the "second charge accumulating section" of the present disclosure. The transistor TGL corresponds to a specific example of the "first switch" of the present disclosure. The transistor FDG corresponds to a specific example of the "second switch" of the present disclosure. The transistor RST corresponds to a specific example of the "third switch" of the present disclosure. The transistor TGS corresponds to a specific example of the "fourth switch" of the present disclosure. The transistor FCG corresponds to a specific example of the "fifth switch" of the present disclosure. The transistors AMP and SEL correspond to a specific example of the "output section" of the present disclosure. The scanner 12 corresponds to a specific example of the "driving section" of the present disclosure. The readout section 20 and the signal processor 14 correspond to a specific example of "processor" of the present disclosure.

[ operation and running ]

Next, the operation and the operation of the image pickup apparatus 1 according to the present embodiment will be explained.

(general operation overview)

First, an overall operation overview of the image pickup apparatus 1 is explained with reference to fig. 1 and 2. The scanner 12 sequentially drives the plurality of image pickup pixels 10 in a unit of a single row. The image pickup pixel 10 sequentially outputs seven pixel voltages VP1 to VP7 in seven conversion periods P1 to P7 in the horizontal period H. The AD converter ADC of the readout section 20 performs AD conversion based on the seven pixel voltages VP1 to VP7, and outputs the corresponding seven count values CNT1 to CNT 7. The signal processor 14 generates four images PIC (images PIC1, PIC2, PIC3, and PIC4) based on the seven count values CNT1 to CNT7 supplied from the readout section 20. Then, the signal processor 14 synthesizes the four images PIC to generate one captured image PICA.

(detailed operation)

In the image pickup apparatus 1, the plurality of image pickup pixels 10 output a pixel voltage VP as a signal SIG. Then, the AD converter ADC of the readout section 20 generates a digital value (count value CNT) based on the signal SIG. The operation of the specific target image sensing pixel 10A will be described in detail below.

Fig. 3, 4A, and 4B show an operation example of the image pickup apparatus 1, in which (a) represents a waveform of a horizontal synchronization signal HSYNC, (B) represents a waveform of a signal SSEL supplied to the image pickup pixel 10A, (C) represents a waveform of a signal SFDG supplied to the image pickup pixel 10A, (D) represents a waveform of a signal STGL supplied to the image pickup pixel 10A, (E) represents a waveform of a signal SRST supplied to the image pickup pixel 10A, (F) represents a waveform of a signal SFCG supplied to the image pickup pixel 10A, (G) represents a waveform of a signal STGS supplied to the image pickup pixel 10A, (H) represents a waveform of a reference signal REF, (I) represents a waveform of a signal SIG output from the image pickup pixel 10A, and (J) represents an operation of a counter 25 in an AD converter ADC coupled to the image pickup pixel 10A. Fig. 4A shows a first half of the operation shown in fig. 3, and fig. 4B shows a second half of the operation shown in fig. 3. In fig. 3 (H) and (I), fig. 4A (H) and (I), and fig. 4B (H) and (I), the waveforms of the respective signals are plotted on the same voltage axis. In addition, in fig. 3 (J), fig. 4A (J), and fig. 4B (J), the slashed line indicates that the counter 25 is performing the counting operation.

Fig. 5A to 5C show the state of the image pickup pixel 10A. In the fig. 5A to 5C, the transistors TGL, RST, FDG, TGS, FCG, and SEL are shown by using switches corresponding to the operation states of the transistors.

First, in the image pickup apparatus 1, in a certain horizontal period H, the scanner 12 selects one row of image pickup pixels 10 including the target image pickup pixel 10A from among the plurality of image pickup pixels 10 in the pixel array 11 by using the signal SSEL, and electrically couples the image pickup pixels 10A to the signal lines SGL corresponding to the image pickup pixels 10A. Then, the scanner 12 controls the operation of the image pickup pixel 10A by using the signals SFDG, STGL, SRST, SFCG and STGS, and the image pickup pixel 10A sequentially outputs seven pixel voltages VP1 to VP7 in seven conversion periods P1 to P7. Then, the AD converter ADC of the readout section 20 performs AD conversion based on the seven pixel voltages VP1 to VP7 and outputs seven count values CNT1 to CNT 7. This operation will be described in detail below.

First, at a time t1, the horizontal period H starts, and then at a time t2, the scanner 12 changes the voltage of the signal SSEL from the low level to the high level ((B) of fig. 4A). This causes the transistor SEL in the image pickup pixel 10A to be placed in an on state, thereby electrically coupling the image pickup pixel 10A to the signal line SGL.

(operation from time t11 to time t 16)

Next, at time t11, the scanner 12 changes the voltage of the signal SFDG from the low level to the high level, and changes the voltage of the signal SRST from the low level to the high level ((C) and (E) of fig. 4A). Therefore, in the image pickup pixel 10A, the transistors FDG and RST are both placed in an on state, the voltage of the floating diffusion FD is set to the power supply voltage VDD and the floating diffusion FD is reset. In addition, at this time t11, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ((H) of fig. 4A).

Next, at time t12, the scanner 12 changes the voltage of the signal SFDG from the high level to the low level, and changes the voltage of the signal SRST from the high level to the low level ((C) and (E) of fig. 4A). This causes both the transistors FDG and RST in the image pickup pixel 10A to be placed in an off state.

Next, at time t13, the scanner 12 changes the voltage of the signal SFDG from the low level to the high level ((C) of fig. 4A). This causes transistor FDG to be placed in the on state.

Therefore, as shown in fig. 5A, in the image pickup pixel 10A, the transistors FDG and SEL are placed in an on state, and all the other transistors are placed in an off state. The transistor FDG is in an on state, so that the floating diffusion FD and the transistor FDG constitute a combined capacitance. The combined capacitance functions as a conversion capacitance that converts the charge in the image pickup pixel 10A into a voltage. As described above, in the image pickup pixel 10A, the transistor FDG is in an on state, and therefore the conversion capacitance of the image pickup pixel 10A has a large capacitance value. Therefore, the charge-to-voltage conversion efficiency is low. This conversion capacitance holds the charge in the case where the reset floating diffusion FD is reset in the period from the time t11 to the time t 12. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP1) corresponding to the voltage in the floating diffusion FD.

Next, in a period from time t14 to time t16 (conversion period P1), the AD converter ADC performs AD conversion based on the pixel voltage VP 1. Specifically, at time t14, the readout controller 28 starts generating the clock signal CLK. At the same time, the reference signal generator 29 starts to lower the voltage of the reference signal REF from the voltage V1 by a predetermined change degree ((H) of fig. 4A). Accordingly, the counter 25 of the AD converter ADC starts the counting operation ((J) of fig. 4A).

Thereafter, at time t15, the voltage of the reference signal REF decreases below the voltage of the signal SIG (pixel voltage VP1) ((H) and (I) of fig. 4A). Accordingly, the comparator 24 of the AD converter ADC changes the voltage of the signal CMP. Accordingly, the counter 25 stops the counting operation ((J) of fig. 4A). At this time, the count value CNT of the counter 25 is the count value CNT 1. After that, the readout section 20 supplies the count value CNT1 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

Then, at time t16, at the end of the conversion period P1, the readout controller 28 stops generating the clock signal CLK, and the reference signal generator 29 stops changing the voltage of the reference signal REF ((H) of fig. 4A).

(operation from time t21 to time t 24)

Next, at time t21, the scanner 12 changes the voltage of the signal SFDG from the high level to the low level ((C) of fig. 4A). This causes the transistor FDG in the image pickup pixel 10A to be placed in an off state. In addition, at this time t21, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ((H) of fig. 4A).

Therefore, as shown in fig. 5B, in the image pickup pixel 10A, the transistor SEL is placed in an on state, and all the other transistors are placed in an off state. As described above, the transistor FDG is in the off state in the image pickup pixel 10A, and therefore the conversion capacitance of the image pickup pixel 10A has a small capacitance value. Therefore, the charge-to-voltage conversion efficiency is high. This conversion capacitance holds the charge in the case where the reset floating diffusion FD is reset in the period from the time t11 to the time t 12. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP2) corresponding to the voltage in the floating diffusion FD.

Next, in a period from time t22 to time t24 (conversion period P2), the AD converter ADC performs AD conversion based on the pixel voltage VP 2. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP2 to obtain a count value CNT2 ((J) of fig. 4A). After that, the readout section 20 supplies the count value CNT2 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

(operation from time t31 to time t 35)

Next, at time t31, the scanner 12 changes the voltage of the signal STGL from the low level to the high level ((D) of fig. 4A). This causes the transistor TGL in the image pickup pixel 10A to be placed in an on state. Accordingly, the electric charges generated in the photodiode PD1 are transferred to the floating diffusion FD. In addition, at this time t31, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ((H) of fig. 4A).

Next, at time t32, the scanner 12 changes the voltage of the signal STGL from the high level to the low level ((D) of fig. 4A). This causes the transistor TGL in the image pickup pixel 10A to be placed in an off state.

Therefore, as shown in fig. 5B, in the image pickup pixel 10A, the transistor FDG is in an off state; therefore, the conversion capacitance in the image pickup pixel 10A has a small capacitance value. Therefore, the charge-to-voltage conversion efficiency is high. In the period from the time t31 to the time t32, the conversion capacitance holds the charge transferred from the photodiode PD 1. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP3) corresponding to the voltage in the floating diffusion FD.

Next, in a period from time t33 to time t35 (conversion period P3), the AD converter ADC performs AD conversion based on the pixel voltage VP 3. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP3 to obtain a count value CNT3 ((J) of fig. 4A). This count value CNT3 corresponds to a count value CNT2 similarly obtained in the case of high conversion efficiency (in the conversion period P2). After that, the readout section 20 supplies the count value CNT3 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

(operation from time t41 to time t 44)

Next, at time t41, the scanner 12 changes the voltage of the signal SFDG from the low level to the high level ((C) of fig. 4A). This causes the transistor FDG in the image pickup pixel 10A to be placed in an on state. In addition, at this time t41, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ((H) of fig. 4A).

Therefore, as shown in fig. 5A, in the image pickup pixel 10A, the transistor FDG is in an on state, which causes the floating diffusion FD and the transistor FDG to constitute a combined capacitance (conversion capacitance). Therefore, the conversion capacitance of the imaging pixel 10A has a large capacitance value; therefore, the conversion efficiency of the charge into the voltage is low. The conversion capacitance holds the charge transferred from the photodiode PD1 in the period from the time t31 to the time t 32. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP4) corresponding to the voltage in the floating diffusion FD.

Next, in a period from time t42 to time t44 (conversion period P4), the AD converter ADC performs AD conversion based on the pixel voltage VP 4. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP4 to obtain a count value CNT4 ((J) of fig. 4A). This count value CNT4 corresponds to a count value CNT1 similarly obtained in the case of low conversion efficiency (in the conversion period P1). After that, the readout section 20 supplies the count value CNT4 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

(operation from time t51 to time t 56)

Next, at time t51, the scanner 12 changes the voltage of the signal SRST from the low level to the high level ((E) of fig. 4B). This causes the transistor RST in the image pickup pixel 10A to be placed in an on state. The transistor FDG is in an on state, so that the floating diffusion FD is set to the power supply voltage VDD, and the floating diffusion FD is reset. In addition, at this time t51, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ((H) of fig. 4B).

Next, at time t52, the scanner 12 changes the voltage of the signal SRST from the high level to the low level ((E) of fig. 4B). This causes the transistor RST in the image pickup pixel 10A to be placed in an off state.

Next, at time t53, the scanner 12 changes the voltage of the signal SFCG from the low level to the high level ((F) of fig. 4B). This causes the transistor FCG in the image pickup pixel 10A to be placed in an on state.

Therefore, as shown in fig. 5C, the transistors FDG, FCG, and SEL are placed in the on state, and all the other transistors are placed in the off state in the image pickup pixel 10A. The transistors FDG and FCG are both in an on state, so that the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance (conversion capacitance). This conversion capacitance holds the charge that was generated in the photodiode PD2 before the time t53 and accumulated in the capacitor FC through the transistor TGS. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP5) corresponding to the voltage in the floating diffusion FD.

Next, in a period from time t54 to time t56 (conversion period P5), the AD converter ADC performs AD conversion based on the pixel voltage VP 5. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP5 to obtain a count value CNT5 ((J) of fig. 4B). After that, the readout section 20 supplies the count value CNT5 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

(operation from time t61 to time t 65)

Next, at time t61, the scanner 12 changes the voltage of the signal STGS from the low level to the high level ((G) of fig. 4B). This causes the transistor TGS in the image pickup pixel 10A to be placed in an on state. In addition, at this time t61, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ((H) of fig. 4B).

Next, at time t62, the scanner 12 changes the voltage of the signal STGS from the high level to the low level ((G) of fig. 4B). This causes the transistor TGS in the image pickup pixel 10A to be placed in an off state.

Therefore, as shown in fig. 5C, in the image pickup pixel 10A, the transistors FDG and FCG are both in an on state, so that the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance (conversion capacitance). This conversion capacitance holds the electric charge transferred from the photodiode PD2 in the period from time t61 to time t62, in addition to the electric charge generated in the photodiode PD2 before time t53 and accumulated in the capacitor FC by the transistor TGS. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP6) corresponding to the voltage in the floating diffusion FD.

Next, in a period from time t63 to time t65 (conversion period P6), the AD converter ADC performs AD conversion based on the pixel voltage VP 6. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP6 to obtain a count value CNT6 ((J) of fig. 4B). This count value CNT6 corresponds to a count value CNT5 obtained in a case where the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance. After that, the readout section 20 supplies the count value CNT6 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

(operation from time t71 to time t 77)

Next, at time t71, the scanner 12 changes the voltage of the signal SRST from the low level to the high level ((E) of fig. 4B). This causes the transistor RST in the image pickup pixel 10A to be placed in an on state. The transistors FDG and FCG are in an on state, so that the voltage of the floating diffusion FD and the voltage of the capacitor FC are set to the power supply voltage VDD, and the floating diffusion FD and the capacitor FC are reset. In addition, at this time t71, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ((H) of fig. 4B).

Next, at time t72, the scanner 12 changes the voltage of the signal SFCG from the high level to the low level ((F) of fig. 4B). This causes the transistor FCG in the image pickup pixel 10A to be placed in an off state.

Next, at time t73, the scanner 12 changes the voltage of the signal SRST from the high level to the low level ((E) of fig. 4B). This causes the transistor RST in the image pickup pixel 10A to be placed in an off state.

Next, at time t74, the scanner 12 changes the voltage of the signal SFCG from the low level to the high level ((F) of fig. 4B). This causes the transistor FCG in the image pickup pixel 10A to be placed in an on state.

Therefore, as shown in fig. 5C, in the image pickup pixel 10A, the transistors FDG and FCG are both in an on state, so that the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance (conversion capacitance). This conversion capacitance holds the charge in the case where the reset floating diffusion FD and the capacitor FC are reset in the period from the time t71 to the time t 72. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP7) corresponding to the voltage in the floating diffusion FD.

Next, in a period from time t75 to time t77 (conversion period P7), the AD converter ADC performs AD conversion based on the pixel voltage VP 7. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP7 to obtain a count value CNT7 ((J) of fig. 4B). This count value CNT7 corresponds to a count value CNT5 obtained in a case where the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance. After that, the readout section 20 supplies the count value CNT7 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

Next, at time t7, the scanner 12 changes the voltage of the signal SFDG from the high level to the low level, and changes the voltage of the signal SFCG from the high level to the low level ((C) and (F) of fig. 4B). This causes the transistors FDG and FCG in the image pickup pixel 10A to be placed in an off state. In addition, at this time t7, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V2 ((H) of fig. 4B).

Then, at time t8, the scanner 12 changes the voltage of the signal SSEL from the high level to the low level ((B) of fig. 4B). Therefore, in the image pickup pixel 10A, the transistor SEL is placed in an off state, and the image pickup pixel 10A is electrically separated from the signal line SGL.

Next, the operation of the signal processor 14 is explained. The signal processor 14 generates four images PIC (images PIC1, PIC2, PIC3, and PIC4) based on the count value CNT supplied from the readout section 20. Then, the signal processor 14 synthesizes these four images PIC to generate one captured image PICA.

Fig. 6 schematically shows the operation of the signal processor 14. The waveforms shown in (a) to (G) of fig. 6 are similar to those shown in (a) to (G) of fig. 3.

As described with reference to fig. 3, 4A, and 4B, the readout section 20 generates the count value CNT1 based on an operation in a period from time t11 to time t21, generates the count value CNT2 based on an operation in a period from time t21 to time t31, generates the count value CNT3 based on an operation in a period from time t31 to time t41, generates the count value CNT4 based on an operation in a period from time t41 to time t51, generates the count value CNT5 based on an operation in a period from time t51 to time t61, generates the count value CNT6 based on an operation in a period from time t61 to time t71, and generates the count value CNT7 based on an operation in a period from time t71 to time t 7.

The signal processor 14 generates a pixel value VAL1 based on the count value CNT2 and the count value CNT 3. Specifically, the signal processor 14 calculates a pixel value VAL1(CNT3-CNT2) by subtracting the count value CNT2 from the count value CNT 3. That is, the image pickup apparatus 1 calculates the pixel value VAL1 by using the count value CNT2 corresponding to the P-phase (precharge phase) data and the count value CNT3 corresponding to the D-phase (data phase) data using the so-called Correlation Double Sampling (CDS) principle.

Similarly, the signal processor 14 generates a pixel value VAL2 based on the count value CNT1 and the count value CNT 4. Specifically, the signal processor 14 calculates a pixel value VAL2(CNT4-CNT1) by subtracting the count value CNT1 from the count value CNT 4. That is, the image pickup apparatus 1 calculates the pixel value VAL2 by using the count value CNT1 corresponding to the P-phase data and the count value CNT4 corresponding to the D-phase data using the correlated double sampling principle.

Similarly, the signal processor 14 generates a pixel value VAL3 based on the count value CNT5 and the count value CNT 6. Specifically, the signal processor 14 calculates a pixel value VAL3(CNT6-CNT5) by subtracting the count value CNT5 from the count value CNT 6. That is, the image pickup apparatus 1 calculates the pixel value VAL3 by using the count value CNT5 corresponding to the P-phase data and the count value CNT6 corresponding to the D-phase data using the correlated double sampling principle.

Then, the signal processor 14 generates a pixel value VAL4 based on the count value CNT5 and the count value CNT 7. Specifically, the signal processor 14 calculates a pixel value VAL4(CNT5-CNT7) by subtracting the count value CNT7 from the count value CNT 5. That is, the image pickup apparatus 1 calculates the pixel value VAL4 by using the count value CNT7 after resetting the floating diffusion FD and the capacitor FC and the count value CNT5 after resetting the floating diffusion FD using the so-called correlated double sampling principle.

Here, the pixel value VAL1 corresponds to a specific example of "first value" of the present disclosure. The pixel value VAL2 corresponds to a specific example of the "second value" of the present disclosure. The pixel value VAL3 corresponds to a specific example of "third value" of the present disclosure. The pixel value VAL4 corresponds to a specific example of "fourth value" of the present disclosure.

Then, the signal processor 14 generates an image PIC1 based on the pixel values VAL1 of all the image pickup pixels 10 in the pixel array 11, generates an image PIC2 based on the pixel values VAL2 of all the image pickup pixels 10 in the pixel array 11, generates an image PIC3 based on the pixel values VAL3 of all the image pickup pixels 10 in the pixel array 11, and generates an image PIC4 based on the pixel values VAL4 of all the image pickup pixels 10 in the pixel array 11. Then, the signal processor 14 synthesizes the images PIC1 to PIC4 to generate a captured image PICA.

Fig. 7 shows an example of the signal-to-noise ratio (S/N ratio) in the captured image PICA synthesized by the image pickup apparatus 1. In fig. 7, the horizontal axis represents illuminance, and the vertical axis represents an S/N ratio.

In the case of synthesizing four images PIC1 to PIC4, the signal processor 14 increases the number of used images PIC1 to PIC4 with an increase in illuminance. Specifically, in the case where the illuminance at the target pixel is lower than the illuminance value L1, the signal processor 14 generates a pixel value at the target pixel in the captured image PICA based on the pixel value VAL1 at the target pixel in the image PIC 1. Further, in the case where the illuminance at the target pixel is higher than the illuminance value L1 and lower than the illuminance value L2, the signal processor 14 generates a pixel value at the target pixel in the captured image PICA based on the pixel values VAL1 and VAL2 at the target pixel in the two images PIC1 and PIC 2. Further, in the case where the illuminance at the target pixel is higher than the illuminance value L2 and lower than the illuminance value L3, the signal processor 14 generates the pixel value at the target pixel in the captured image PICA based on the pixel values VAL1 to VAL3 at the target pixel in the three images PIC1 to PIC 3. Further, in the case where the illuminance is higher than the illuminance value L3, the signal processor 14 generates a pixel value at a target pixel in the captured image PICA based on the pixel values VAL1 to VAL4 at the target pixel in the four images PIC1 to PIC 4.

As shown in fig. 7, in the case where the illuminance exceeds the illuminance value L2 (portion W1), the S/N ratio decreases, and in the case where the illuminance exceeds the illuminance value L3 (portion W3), the S/N ratio further decreases. That is, in the section W1, the S/N ratio is reduced due to the addition of the image PIC3 to the image for synthesis, and in the section W2, the S/N ratio is reduced due to the addition of the image PIC4 to the image for synthesis.

As described above, in the image pickup apparatus 1, the pixel value VAL3 included in the image PIC3 is determined by correlated double sampling. This makes it possible to reduce noise included in the image PIC3 in the image pickup apparatus 1; therefore, as described below, a decrease in the S/N ratio in the illuminance value L2 shown in fig. 7 can be suppressed as compared with the comparative example.

Comparative example

Next, the effects of the image pickup apparatus 1 according to the present embodiment will be described by comparing the image pickup apparatus according to the comparative example. The image pickup apparatus of the comparative example includes a scanner, a readout section, a signal processor, and a controller. In the image pickup apparatus of this comparative example, the image pickup pixel 10 sequentially outputs six pixel voltages VP1 to VP4, VP16, and VP7 in six conversion periods P1 to P6 in the horizontal period H. Each AD converter ADC of the readout section performs AD conversion based on the six pixel voltages VP1 to VP4, VP16, and VP7, and outputs six count values CNT1 to CNT4, CNT16, and CNT 7. The signal processor generates three images PIC (images PIC1, PIC2, and PIC13) based on the count values CNT1 to CNT4, CNT16, and CNT7 supplied from the readout section. Then, the signal processor synthesizes the three images PIC to generate one captured image PICR.

Fig. 8, 9A, and 9B show an operation example of a specific target image pickup pixel 10A in the image pickup apparatus of the comparative example. Fig. 9A shows the first half of the operation shown in fig. 8, and fig. 9B shows the second half of the operation shown in fig. 8. The operation before the time t51 and the operation from the time t71 are similar to the operation of the image pickup apparatus 1 according to the present embodiment (fig. 3, 4A, and 4B). The operation from time t51 to time t71 will be explained below.

At time t51, the scanner changes the voltage of the signal SRST from the low level to the high level ((E) of fig. 9B). This causes the transistor RST in the image pickup pixel 10A to be placed in an on state. The transistor FDG is in an on state, so that the floating diffusion FD is set to the power supply voltage VDD, and the floating diffusion FD is reset. In addition, at this time t51, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ((H) of fig. 9B).

Next, at time t52, the scanner changes the voltage of the signal SRST from the high level to the low level ((E) of fig. 9B). This causes the transistor RST in the image pickup pixel 10A to be placed in an off state.

Next, at time t53, the scanner changes the voltage of the signal SFCG from the low level to the high level ((F) of fig. 9B). This causes the transistor FCG in the image pickup pixel 10A to be placed in an on state.

Next, at time t58, the scanner changes the voltage of the signal STGS from the low level to the high level ((G) of fig. 9B). This causes the transistor TGS in the image pickup pixel 10A to be placed in an on state.

Next, at time t59, the scanner changes the voltage of the signal STGS from the high level to the low level ((G) of fig. 8B). This causes the transistor TGS in the image pickup pixel 10A to be placed in an off state.

Therefore, as shown in fig. 5C, the transistors FDG and FCG are both in an on state in the image pickup pixel 10A, so that the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance (conversion capacitance). This conversion capacitance holds the electric charge transferred from the photodiode PD2 in the period from time t58 to time t59, in addition to the electric charge generated in the photodiode PD2 before time t53 and accumulated in the capacitor FC by the transistor TGS. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP16) corresponding to the voltage in the floating diffusion FD.

Next, in a period from time t63 to time t65 (conversion period P16), the AD converter ADC performs AD conversion based on the pixel voltage VP 16. The operation is similar to that in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP16 to obtain a count value CNT16 ((J) of fig. 9B). After that, the readout section supplies the count value CNT16 to the signal processor, and thereafter resets the count value CNT of the counter 25.

Fig. 10 schematically shows the operation of the signal processor of the comparative example. The waveforms shown in (a) to (G) of fig. 10 are similar to those shown in (a) to (G) of fig. 8.

As described with reference to fig. 8, 9A, and 9B, the readout section of the comparative example generates the count value CNT16 based on the operation in the period from time t51 to time t71, and generates the count value CNT7 based on the operation in the period from time t71 to time t 7.

The signal processor of the comparative example generates the pixel value VAL13 based on the count value CNT16 and the count value CNT 7. Specifically, the signal processor calculates a pixel value VAL13 by subtracting the count value CNT7(CNT16-CNT7) from the count value CNT16 using a Double Data Sampling (DDS) principle.

Then, the signal processor of the comparative example generates an image PIC1 based on the pixel values VAL1 in all the image pickup pixels 10 in the pixel array 11, generates an image PIC2 based on the pixel values VAL2 in all the image pickup pixels 10 in the pixel array 11, and generates an image PIC13 based on the pixel values VAL13 in all the image pickup pixels 10 in the pixel array 11. Then, the signal processor of the comparative example synthesizes the images PIC1, PIC2, and PIC13 to generate a captured image PICR.

Fig. 11 shows an example of the signal-to-noise ratio (S/N ratio) in the captured image PICR synthesized by the image capturing apparatus of the comparative example.

As described in the signal processor 14 according to the present embodiment, in the case of synthesizing three images PIC, the signal processor of the comparative example increases the number of used images PIC among the images PIC1, PIC2, and PIC13 with an increase in illuminance. Specifically, in the case where the illuminance at the target pixel is lower than the illuminance value L11, the signal processor of the comparative example generates a pixel value at the target pixel in the captured image PICA based on the pixel value VAL1 at the target pixel in the image PIC 1. Further, in the case where the illuminance at the target pixel is higher than the illuminance value L11 and lower than the illuminance value L12, the signal processor of the comparative example generates the pixel value at the target pixel in the captured image PICA based on the pixel values VAL1 and VAL2 at the target pixel in the two images PIC1 and PIC 2. Further, in the case where the illuminance at the target pixel is higher than the illuminance value L12, the signal processor of the comparative example generates the pixel value at the target pixel in the captured image PICA based on the pixel values VAL1, VAL2, VAL3 at the target pixel in the three images PIC1, PIC2, PIC 13.

As shown in fig. 11, when the illuminance exceeds the illuminance value L12 (portion W3), the S/N ratio decreases. That is, in the section W3, the S/N ratio is lowered due to the addition of the image PIC13 to the image for synthesis. That is, the image PIC13 is generated by Double Data Sampling (DDS); therefore, it is not possible to sufficiently remove noise as the correlated double sampling. Therefore, in the image pickup apparatus of the comparative example, the S/N ratio in the portion W3 significantly decreases.

In contrast to this, in the image pickup apparatus 1 according to the present embodiment, the image PIC3 is generated by correlated double sampling. That is, in fig. 6, signal processor 14 generates image PIC3 by: the count value CNT5 generated based on the operation in the period from the time t51 to the time t61 is used as the P-phase data, and the count value CNT6 generated based on the operation in the period from the time t61 to the time t71 is used as the D-phase data. This makes it possible to remove, for example, a dark current component and reset noise of the photodiode PD2 in the image pickup apparatus 1, so that as shown in fig. 7, a decrease in the S/N ratio can be suppressed with the addition of the image PIC 3. Therefore, in the image pickup apparatus 1, the image quality of the captured image PICA can be improved.

[ Effect ]

As described above, in the present embodiment, the third image PIC3 is generated by correlated double sampling and the photographed image is generated by using this image PIC3, so that the image quality can be improved.

[ first modification ]

In the above-described embodiment, seven conversion periods P1 to P7 are provided as shown in fig. 3, but this is not limitative. For example, eight conversion periods P1 to P8 may be set in the image pickup apparatus 1B as shown in fig. 12 and 13. In this image pickup apparatus 1B, a period including the conversion period P15 is added between the period from the time t51 to the time t61 and the period from the time t61 to the time t71 in the image pickup apparatus 1 according to the above-described embodiment (fig. 3).

In the image pickup apparatus 1B, the ADC converter ADC generates a count value CNT (count value CNT5) based on the pixel voltage VP (VP5) output from the image pickup pixel 10A in the conversion period P5. Then, in the image pickup apparatus 1B, while holding the signals SSEL, SFDG, STGL, SRST, SFCG and STGS, the ADC converter ADC subsequently generates a count value CNT (count value CNT15) based on the pixel voltage VP output from the image pickup pixel 10A in a conversion period P15.

Then, the signal processor 14 generates a pixel value VAL3 based on the count value CNT15 and the count value CNT 6. Specifically, the signal processor 14 calculates a pixel value VAL3 by subtracting the count value CNT15(CNT6-CNT15) from the count value CNT 6. That is, the image pickup apparatus 1B calculates the pixel value VAL3 by using the count value CNT15 corresponding to the P-phase data and the count value CNT6 corresponding to the D-phase data using the correlated double sampling principle. In addition, as in the above-described embodiment, the signal processor 14 generates the pixel value VAL4 based on the count value CNT5 and the count value CNT 7.

Then, the signal processor 14 generates an image PIC1 based on the pixel values VAL1 in all the image pickup pixels 10 in the pixel array 11, an image PIC2 based on the pixel values VAL2 in all the image pickup pixels 10 in the pixel array 11, an image PIC3 based on the pixel values VAL3 in all the image pickup pixels 10 in the pixel array 11, and an image PIC4 based on the pixel values VAL4 in all the image pickup pixels 10 in the pixel array 11. Then, the signal processor 14 synthesizes the images PIC1 to PIC4 to generate a captured image PICA.

Although the present technology has been described above with reference to the embodiments and the modifications, the present technology is not limited to the embodiments and the like and may be modified in various ways.

For example, the waveforms and the transition timings of the signals SSEL, SFDG, STGL, SRST, SFCG, and STGS in the above-described embodiments and the like are exemplary, and may be appropriately changed.

It should be noted that the effects described herein are merely exemplary and not restrictive, and that other effects may be provided.

Note that the present technology may have any of the following configurations.

(1) An image pickup apparatus, comprising:

a first light receiving device and a second light receiving device;

a first charge accumulation section and a second charge accumulation section;

a first switch that couples the first light receiving device and the first charge accumulating portion to each other by being placed in an on state;

a second switch that couples a predetermined node and the first charge accumulating portion to each other by being placed in an on state;

a third switch that applies a predetermined voltage to the predetermined node by being placed in an on state;

a fourth switch that couples the second light receiving device and the second charge accumulating portion to each other by being placed in an on state;

a fifth switch that couples the second charge accumulation section and the predetermined node to each other by being placed in an on state;

an output section that outputs a pixel voltage corresponding to the voltage in the first charge accumulation section;

a driving section that drives each of the switches; and

a processor that determines a first value, a second value, a third value, and a fourth value based on the pixel voltage, and generates a pixel value based on these values,

in a first period, the driving part places the second switch and the third switch in an on state and places the first switch, the fourth switch, and the fifth switch in an off state,

in a second period after the first period, the driving section places the third switch in an off state and places the fifth switch in an on state,

in a third period subsequent to the second period, the driving section places the fourth switch in an on state,

in a fourth period after the third period, the driving section places the fourth switch in an off state, and

the processor determines the third value based on the pixel voltage in the second period and the pixel voltage in the fourth period.

(2) The image pickup apparatus according to (1), wherein the processor generates a first digital value by performing AD conversion based on the pixel voltage in the second period while generating a second digital value by performing AD conversion based on the pixel voltage in the fourth period, and determines the third value based on the first digital value and the second digital value.

(3) The image pickup apparatus according to (1) or (2), wherein,

in a fifth period after the fourth period, the driving part places the third switch and the fifth switch in an on state,

in a sixth period after the fifth period, the driving part places the third switch and the fifth switch in an off state,

in a seventh period after the sixth period, the driving section places the third switch in an off state and places the fifth switch in an on state, and

the processor determines the fourth value based on the pixel voltage in the second period and the pixel voltage in the seventh period.

(4) The image pickup apparatus according to (1) or (2), wherein,

in a seventh period after the sixth period, the driving section places the third switch in an off state and places the fifth switch in an on state,

the second period includes a first sub-period and a second sub-period subsequent to the first sub-period,

the processor determines the third value based on the pixel voltage in the second sub-period of the second period and the pixel voltage in the fourth period, and

the processor determines the fourth value based on the pixel voltage in the first sub-period and the pixel voltage in the seventh period of the second period.

(5) The image pickup apparatus according to any one of (1) to (4),

in an eighth period, the driving section places the second switch and the third switch in an on state and places the first switch, the fourth switch, and the fifth switch in an off state,

in a ninth period subsequent to the eighth period, the driving section places the second switch in an on state and places the third switch in an off state,

in a tenth period after the ninth period, the driving part places the second switch in an off state,

in an eleventh period after the tenth period, the driving part places the first switch in an on state,

in a twelfth period after the eleventh period, the driving part places the first switch in an off state,

in a thirteenth period after the twelfth period and before the first period, the driving part places the second switch in an on state,

the processor determines the first value based on the pixel voltage in the tenth period and the pixel voltage in the twelfth period,

the processor determines the second value based on the pixel voltage in the ninth period and the pixel voltage in the thirteenth period.

(6) The image pickup apparatus according to any one of (1) to (5),

in the event that the illumination is lower than a first illumination value, the processor generates the pixel value based on the first value,

the processor generates the pixel value based on the first value and the second value if the illumination is higher than the first illumination value and lower than a second illumination value,

in a case where the illuminance is higher than the second illuminance value and lower than a third illuminance value, the processor generates the pixel value based on the first value, the second value, and the third value, and

in a case that the illumination is higher than the third illumination value, the processor generates the pixel value based on the first value, the second value, the third value, and the fourth value.

(7) The image pickup apparatus according to any one of (1) to (6), wherein a light receiving area of the first light receiving device is larger than a light receiving area of the second light receiving device.

(8) The image pickup apparatus according to any one of (1) to (7), wherein the first charge accumulating portion includes a diffusion layer.

(9) The image pickup apparatus according to any one of (1) to (8), wherein the processor includes:

a reference signal generator that generates a reference signal whose voltage level varies,

a comparison section generating a comparison signal by comparing the pixel voltage with the reference signal, an

A counter that generates a digital value by performing a counting operation based on the comparison signal.

(10) An image pickup method, comprising:

driving respective switches of an image pickup pixel including first and second light receiving devices, first and second charge accumulating sections, a first switch coupling the first light receiving device and the first charge accumulating section to each other by being placed in an on state, a second switch coupling a predetermined node and the first charge accumulating section to each other by being placed in an on state, a third switch applying a predetermined voltage to the predetermined node by being placed in an on state, a fourth switch coupling the second light receiving device and the second charge accumulating section to each other by being placed in an on state, a fifth switch coupling the second charge accumulating section and the predetermined node to each other by being placed in an on state, and an output section, and the output section outputs a pixel voltage corresponding to the voltage in the first charge accumulating section;

determining a first value, a second value, a third value and a fourth value based on the pixel voltage and generating a pixel value based on these values;

in a first period, placing the second switch and the third switch in an on state, and placing the first switch, the fourth switch, and the fifth switch in an off state;

in a second period after the first period, placing the third switch in an off state and placing the fifth switch in an on state;

in a third period after the second period, placing the fourth switch in an on state;

in a fourth period after the third period, placing the fourth switch in an off state; and is

Determining the third value based on the pixel voltage in the second period and the pixel voltage in the fourth period.

This application claims priority from japanese patent application JP2017-208118, filed in 2017, month 10, 27, to the office of the present patent, the entire content of which is incorporated herein by reference.

It will be understood by those skilled in the art that various modifications, combinations, sub-combinations and changes may be made in accordance with design requirements and other factors without departing from the scope of the appended claims or their equivalents.

Claims

1. An image pickup apparatus, comprising:

a first light receiving device and a second light receiving device;

a first charge accumulation section and a second charge accumulation section;

a driving section that drives each of the first to fifth switches; and

a processor that determines a first value, a second value, a third value, and a fourth value based on the pixel voltage, and generates a pixel value based on the first value through the fourth value,

in a third period after the second period, the driving section places the fourth switch in an on state,

the processor generates a first digital value by performing AD conversion based on the pixel voltage in the second period, simultaneously generates a second digital value by performing AD conversion based on the pixel voltage in the fourth period, and determines the third value by subtracting the first digital value from the second digital value.

2. The image pickup apparatus according to claim 1,

the processor generates a third digital value by performing AD conversion based on the pixel voltage in the seventh period, and determines the fourth value by subtracting the third digital value from the first digital value.

3. The image pickup apparatus according to claim 1,

the processor determines the third value by subtracting the first digital value from the second digital value, and

4. The image pickup apparatus according to claim 1,

in a ninth period after the eighth period, the driving section places the second switch in an on state and places the third switch in an off state,

the processor generates a fourth digital value by performing AD conversion based on the pixel voltage in the tenth period, generates a fifth digital value by performing AD conversion based on the pixel voltage in the twelfth period, and determines the first value by subtracting the fourth digital value from the fifth digital value,

the processor generates a sixth digital value by performing AD conversion based on the pixel voltage in the ninth period, generates a seventh digital value by performing AD conversion based on the pixel voltage in the twelfth period, and determines the second value by subtracting the sixth digital value from the seventh digital value,

wherein the eighth period to the thirteenth period precede the first period.

5. The image pickup apparatus according to any one of claims 1 to 4,

in a case that the illuminance is higher than the second illuminance value and lower than a third illuminance value, the processor generates the pixel value based on the first value, the second value, and the third value, and

6. The image pickup apparatus according to any one of claims 1 to 4, wherein a light receiving area of the first light receiving device is larger than a light receiving area of the second light receiving device.

7. The image pickup apparatus according to any one of claims 1 to 4, wherein the first charge accumulating portion includes a diffusion layer.

8. The image capture device of any one of claims 1 to 4, wherein the processor comprises:

9. An image pickup method, comprising:

determining a first value, a second value, a third value, and a fourth value based on the pixel voltage, and generating a pixel value based on the first value through the fourth value;

Generating a first digital value by performing AD conversion based on the pixel voltage in the second period, while generating a second digital value by performing AD conversion based on the pixel voltage in the fourth period, and determining the third value by subtracting the first digital value from the second digital value.