CN111158607B - Data erasing operation processing method, system, electronic equipment and storage medium - Google Patents

Data erasing operation processing method, system, electronic equipment and storage medium Download PDF

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Publication number
CN111158607B
CN111158607B CN201911418517.1A CN201911418517A CN111158607B CN 111158607 B CN111158607 B CN 111158607B CN 201911418517 A CN201911418517 A CN 201911418517A CN 111158607 B CN111158607 B CN 111158607B
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data
read
target address
erasing
target
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CN111158607A (en
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赵鲁荣
张雷波
钟永超
齐向超
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Weichai Power Co Ltd
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Weichai Power Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a processing method, a system, electronic equipment and a storage medium for data erasing operation, wherein a microprocessor responds to triggering to erase target data of a target address section of a chip and generates an erasing instruction according to obtained erasing operation configuration; the buffer is used for buffering the target address segment information in the erasing operation configuration under the control of the microprocessor; the microprocessor sends the erasing command to the chip, controls the buffer to send the target address information to the chip so that the chip can execute storage processing based on the erasing command and the target address information.

Description

Data erasing operation processing method, system, electronic equipment and storage medium
Technical Field
The present invention relates to the field of data processing, and in particular, to a method, a system, an electronic device, and a storage medium for processing data erasure operation.
Background
The EEPROM chip is an electrically erasable and programmable read-only memory (Electrically Erasable Programmable read only memory, abbreviated as EEPROM chip), which is a memory chip that is not lost after power failure, and is widely used for reading and writing data in various fields due to the repeated erasing and writing characteristics.
In the prior art, the EEPROM chip performs the storage operation on all the areas, that is, the EEPROM chip needs to directly erase all the areas on the storage area, no matter whether the purpose of the storage operation is to update data or delete data.
However, since the number of times of erasing of the EEPROM chip is limited, such an erasing manner will seriously shorten the chip life; meanwhile, as the operation time for erasing all data is long, once the process has the problems of abnormal power failure and the like, the damage risk of the chip can be increased.
Disclosure of Invention
In view of the above, the present invention provides a method, a system, an electronic device, and a storage medium for processing a data erasing operation.
In a first aspect, the present disclosure provides a method for processing a data erasure operation, the method being applicable to a processing system, the processing system including a microprocessor, a buffer, and a chip;
the processing method of the data erasing operation comprises the following steps:
the microprocessor responds to the triggering to carry out erasing operation on target data of a target address section of the chip, and generates an erasing instruction according to the obtained erasing operation configuration; the erasing operation configuration stores target address segment information including target address segments and target data, and the erasing instruction is used for storing the target address segment information, corresponding addressing identifiers and execution result identifiers;
the buffer is used for buffering the target address segment information in the erasing operation configuration under the control of the microprocessor;
the microprocessor sends the erasing command to the chip, and controls the buffer to send the target address segment information to the chip, so that the chip can execute storage processing based on the erasing command and the target address segment information.
Optionally, the processing method further includes:
the micro-processing responds to the triggered read operation of reading the data of the address segment to be read of the chip, and receives the erasing command stored currently by the chip;
The microprocessor controls the buffer to read the data of the address field to be read in the chip according to the target address field corresponding to the addressing mark in the erasing command to obtain read data;
the microprocessor judges whether the address segment to be read comprises the target address segment according to the target address segment corresponding to the addressing identifier;
when the microprocessor determines that the address field to be read comprises a target address field, performing assignment processing on target data corresponding to the target address field in read data according to an execution result identifier in the erasing instruction, and taking the assigned read data as data obtained by read operation.
Optionally, the processing method further includes:
when the microprocessor determines that the address field to be read does not include the target address field, the read data are data obtained by the read operation.
Optionally, the execution result identifier includes a first identifier bit for indicating whether the erase operation is performed, a second identifier bit for indicating whether the erase operation is effective, a third identifier bit for indicating whether the target address segment of the erase is effective, and a fourth identifier bit for indicating the erase effect;
correspondingly, the generating the erasing command comprises the following steps:
And setting the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the addressing identification according to the erasing operation configuration so as to obtain an erasing instruction formed by the addressing identification and the execution result identification.
Optionally, when the microprocessor determines that the address field to be read includes the target address field, the read data includes target data and non-target data; the target data are data obtained by reading a target address field in an address field to be read of the chip, and the non-target data are data obtained by reading other address fields except the target address field in the address field to be read of the chip;
performing assignment processing on target data corresponding to the target address segment in the read data according to the execution result identifier in the erasing instruction, and taking the assigned read data as data obtained by a read operation, wherein the assignment processing comprises the following steps:
determining the value of the assignment to the target data according to the fourth identification bit;
and assigning the target data in the read data as the assigned value, wherein the target data after being assigned with the value and the non-target data form the data obtained by the read operation.
Optionally, the microprocessor controls the buffer to read the data of the address field to be read in the chip according to the target address field corresponding to the addressing identifier in the erasing instruction to obtain the read data, and further includes:
determining whether a first identification bit, a second identification bit and a third identification bit in an erasing instruction all indicate that the erasing instruction is in a valid state;
if yes, executing the step that the microprocessor judges whether the address segment to be read comprises the target address segment according to the target address segment corresponding to the addressing identification;
if not, the step of taking the read data as the data obtained by the read operation is performed.
Optionally, after the buffer buffers the target data in the erasing operation configuration under the control of the microprocessor, the method further includes:
the microprocessor determines the block number of the corresponding target address segment of the target data in the chip;
correspondingly, the microprocessor judges whether the address field to be read includes the target address field according to the target address field corresponding to the addressing identifier, including:
and the microprocessor determines whether the target address segments of all the target address segments are judged to be read or not according to the number of the blocks.
In a second aspect, the present disclosure provides a processing system for data erasure operations, comprising: a microprocessor, a buffer and a chip;
the microprocessor responds to the triggering to erase and write the target data of the target address section of the chip, and generates an erasing instruction according to the obtained erasing operation configuration; the erasing operation configuration stores target address segment information including target address segments and target data, and the erasing instruction is used for storing the target address segment information, corresponding addressing identifiers and execution result identifiers;
the buffer is used for buffering the target address segment information in the erasing operation configuration under the control of the microprocessor;
the microprocessor sends the erasing command to the chip, and controls the buffer to send the target address segment information to the chip, so that the chip can execute storage processing based on the erasing command and the target address information.
Optionally, the microprocessor responds to the triggered read operation of reading the data of the address segment to be read of the chip, and receives the erasing command currently stored by the chip;
the microprocessor controls the buffer to read the data of the address field to be read in the chip according to the target address field corresponding to the addressing mark in the erasing command to obtain read data;
The microprocessor judges whether the address segment to be read comprises the target address segment according to the target address segment corresponding to the addressing identifier;
when the microprocessor determines that the address field to be read comprises a target address field, performing assignment processing on target data corresponding to the target address field in read data according to an execution result identifier in an erasing instruction, and taking the assigned read data as data obtained by read operation;
when the microprocessor determines that the address field to be read does not include the target address field, the read data are data obtained by the read operation.
In a third aspect, the present disclosure provides an electronic device comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing computer-executable instructions stored in the memory causes the at least one processor to implement the method of any one of the preceding claims.
In a fourth aspect, the present disclosure provides a readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement a method as described in any preceding claim.
The invention provides a processing method, a system, electronic equipment and a storage medium for data erasing operation, wherein a microprocessor responds to triggering to erase target data of a target address section of a chip and generates an erasing instruction according to obtained erasing operation configuration; the erasing operation configuration stores target address segment information including target address segments and target data, and the erasing instruction is used for storing the target address segment information, corresponding addressing identifiers and execution result identifiers; the buffer is used for buffering the target address segment information in the erasing operation configuration under the control of the microprocessor; the microprocessor sends the erasing command to the chip, controls the buffer to send the target address information to the chip so that the chip can execute storage processing based on the erasing command and the target address information.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic diagram of a network architecture upon which the present disclosure is based;
fig. 2 is a flowchart illustrating a method for processing a data erasing operation according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a structure of an erasing command in a processing method of a data erasing operation according to an embodiment of the disclosure;
FIG. 4 is a flowchart illustrating another method for processing a data erasure operation according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a read operation process flow in another method for processing a data erasure operation according to an embodiment of the present disclosure;
FIG. 6 is a flowchart illustrating another method for processing a data erasure operation according to an embodiment of the present disclosure;
FIG. 7 is a block diagram of a processing system for data erasure operations provided by an embodiment of the present disclosure;
fig. 8 is a schematic hardware structure of an electronic device according to an embodiment of the disclosure.
Specific embodiments of the present disclosure have been shown by way of the above drawings and will be described in more detail below. These drawings and the written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the disclosed concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
The EEPROM chip is an electrically erasable and programmable read-only memory (Electrically Erasable Programmable read only memory, abbreviated as EEPROM chip), which is a memory chip that is not lost after power failure, and is widely used for reading and writing data in various fields due to the repeated erasing and writing characteristics.
In the prior art, the EEPROM chip performs the storage operation on all the areas, that is, the EEPROM chip needs to directly erase all the areas on the storage area, no matter whether the purpose of the storage operation is to update data or delete data.
However, since the number of times of erasing of the EEPROM chip is limited, such an erasing manner will seriously shorten the chip life; meanwhile, due to the fact that the operation time for erasing all data is long, once the process has the problems of abnormal power failure and the like, the risk of unsuccessful erasing is increased, and once the process is erased, data recovery cannot be carried out.
In view of the above problems, in the process of erasing and writing data on a chip provided by the present disclosure, the chip will only erase and write the target address segment and the target data therein according to the received erasing and writing instruction, so that the data in the chip need not to be actually erased, and meanwhile, the operation area is reduced, which is beneficial to improving the service life and the processing speed of the chip.
The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a schematic diagram of a network architecture on which the disclosure is based, as shown in fig. 1, a processing system 1 for data erasing operation may be installed on an operation platform 2, and the processing system for data erasing operation may implement erasing operation processing on data in the operation platform 2 based on a processing method for data erasing operation provided below.
The operation platform 2 may correspond to different platform devices based on different application scenarios. For example, the operation platform 2 may be a driving platform of a vehicle, and the processing system 1 for data erasing operation may be installed or integrated on an electronic control unit, such as a central control computer, of the driving platform 2; the operation platform 2 may also be a control platform of other devices, such as engineering devices, and the corresponding processing system 1 for data erasing operation may also be integrated in a central processing unit of the engineering device.
In a first aspect, referring to fig. 2, fig. 2 is a flow chart of a processing method of a data erasing operation according to an embodiment of the disclosure. The method provided by the embodiment of the disclosure comprises the following steps:
step 101, the microprocessor responds to the triggering to erase and write the target data of the target address section of the chip, and generates an erasing instruction according to the obtained erasing operation configuration; and the erasing operation configuration stores target address segment information including target address segments and target data, and the erasing instruction is used for storing the target address segment information, the corresponding addressing identifier and the execution result identifier.
Step 102, the buffer caches the target address field information in the erasing operation configuration under the control of the microprocessor.
Step 103, the microprocessor sends the erasing command to the chip, and controls the buffer to send the target address information to the chip, so that the chip can execute the storage processing based on the erasing command and the target address information.
In the processing method for data erasing operation provided by the disclosure, in order to avoid the problems of reduced service life of a chip, slow processing efficiency and the like caused by erasing processing on all area data in the chip. Compared with the prior art, the method and the device convert the erasing operation of the data in the chip into the storage operation of the data, and the storage operation is only carried out on the data needing a partial area or a partial address field. Therefore, compared with the prior art, the processing efficiency of the embodiment is higher, and the reduction of the service life of the chip caused by repeatedly erasing the data of the chip is avoided.
Specifically, first, the microprocessor responds to the trigger to erase and write the target data of the target address segment of the chip, wherein the erase and write operation is triggered by the user, and when the trigger is triggered, the microprocessor synchronously obtains the erase and write operation configuration, wherein the erase and write operation configuration includes the target address segment information of the current erase and write operation, the target erase and write effect and the like. And the microprocessor determines the addressing identification and the execution result identification of the target address field required by the current processing through the information recorded in the erasing operation configuration, and generates an erasing instruction based on the two identifications.
The execution result identifier comprises a first identification bit used for indicating whether the erasure operation is performed, a second identification bit used for indicating whether the erasure operation is effective, a third identification bit used for indicating whether the target address segment of erasure is effective, and a fourth identification bit used for indicating the erasure effect.
Correspondingly, generating the erasing command comprises the following steps: and setting the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the addressing identification according to the erasing operation configuration so as to obtain an erasing instruction formed by the addressing identification and the execution result identification.
Further, fig. 3 is a schematic diagram of a structure of an erasing command in a processing method of a data erasing operation according to an embodiment of the disclosure.
Specifically, to ensure the validity of the erasing operation, the data format of the erasing instruction may be set to be one data that is identified by addressing and combined with the execution result bits including the first identification bit, the second identification bit, the third identification bit, and the fourth identification bit. Wherein the high 16-bit addressing identifier is a count of the number of address segments or BLOCKs (which can be automatically calculated by software) that identify the need for erasure; the lower 16 bits then identify: the fourth identification bit is mainly used for erasing the fourth identification bit to be 0 or F when the fourth identification bit is required to be special; the third identification bit is used for preventing an error preventing mechanism for preventing address field information from being written into invalidity; the second identification bit is a real erasing operation mark, and is expressed by four bits to prevent the writing error of the mark bit; the first identification bit is used for checking during reading, namely, error-proof checking effective for the previous erasing operation, and other operations are only performed when the erasing operation is effective.
A buffer is a memory device provided in the microprocessor that can be used to buffer data. The microprocessor controls the buffer to extract the target address field information in the erasing operation configuration for buffering.
And then, the microprocessor sends the erasing command to the chip, and controls the buffer to send the target data to the chip so that the chip can execute storage processing based on the erasing command and the target data. The chip executes the storage of the information of the target address segment according to the addressing identification of the target address segment in the erasing instruction and the execution result identification.
In the data erasing operation process performed on the chip provided by the embodiment, the chip only erases the target address segment and the target data according to the received erasing instruction, so that the data in the chip is not required to be truly erased, and meanwhile, the operation area is reduced, so that the service life of the chip and the processing speed of the chip are improved.
Fig. 4 is a flowchart of another method for processing a data erasing operation according to an embodiment of the disclosure, where, on the basis of the foregoing embodiment, as shown in fig. 4, the method for processing a data erasing operation includes:
Step 201, the microprocessor responds to the triggered erasing operation on the target data of the target address section of the chip, and generates an erasing instruction according to the obtained erasing operation configuration; and the erasing operation configuration stores target address segment information including target address segments and target data, and the erasing instruction is used for storing the target address segment information, the corresponding addressing identifier and the execution result identifier.
Step 202, the buffer caches the target address field information in the configuration of the erasing operation under the control of the microprocessor.
Step 203, the microprocessor sends the erasing command to the chip, and controls the buffer to send the target address segment information to the chip, so that the chip can execute the storage processing based on the erasing command and the target address segment information.
And 204, the microprocessor responds to the triggered read operation of reading the data of the address segment to be read of the chip, and receives the erasing instruction currently stored by the chip.
Step 205, the microprocessor controls the buffer to read the data of the address field to be read in the chip according to the target address field corresponding to the addressing identification in the erasing command, and obtains the read data.
And 206, the microprocessor judges whether the address field to be read comprises the target address field according to the target address field corresponding to the addressing identification.
And 207, when the microprocessor determines that the address field to be read comprises a target address field, performing assignment processing on target data corresponding to the target address field in the read data according to the execution result identifier in the erasing instruction, and taking the assigned read data as data obtained by the read operation.
Step 208, when the microprocessor determines that the address field to be read does not include the target address field, the read data is data obtained by a read operation.
Steps 201 to 203 are similar to the foregoing embodiments, and are not repeated, unlike the foregoing embodiments, this embodiment further includes a process of performing a read operation on the chip, and by using the identifier in the erasing command, the read data stored on the chip is implemented and the assignment process is performed on the read data, so that the data obtained by performing the storage and the read process on the chip is equivalent to the data obtained by performing the erasing process on the chip and the read data.
And the microprocessor responds to the triggered read operation of reading the data of the address segment to be read of the chip, and receives the erasing command currently stored by the chip. And then, the microprocessor can control the buffer to read the data of the address field to be read in the chip according to the target address field corresponding to the addressing identification in the erasing instruction, so as to obtain the read data.
It should be noted that, the address field to be read related to the read operation may include the target address field, or may not include the target address field, and the processing manners of the data of the two address fields are different.
Specifically, firstly, the microprocessor determines a target address segment according to the addressing identifier, and judges whether the target address segment is included in the address segment to be read. When the address section to be read and the target address section have the repeated address section, the target address section can be determined to be included in the address section to be read, and when the address section to be read and the target address section do not have the repeated address section, the target address section can be determined not to be included in the address section to be read.
In an alternative embodiment, when the address segment to be read includes a target address segment, according to the execution result identifier in the erasing instruction, performing assignment processing on target data corresponding to the target address segment in the read data, and taking the assigned read data as data obtained by the read operation.
Further, the read data includes target data and non-target data; the target data are data obtained by reading a target address field in an address field to be read of the chip, and the non-target data are data obtained by reading other address fields except the target address field in the address field to be read of the chip;
Therefore, according to the execution result identifier in the erasing instruction, performing assignment processing on target data corresponding to the target address segment in the read data, and taking the assigned read data as data obtained by the read operation, the following method can be specifically adopted: determining the value of the assignment to the target data according to the fourth identification bit; and assigning the target data in the read data as the assigned value, wherein the target data after being assigned with the value and the non-target data form the data obtained by the read operation.
Of course, in other alternative embodiments, the read data is data obtained directly for the read operation when the microprocessor determines that the target address field is not included in the address field to be read.
On the basis of the above embodiment, in order to further ensure the effectiveness of the erasing operation, the method further includes: the microprocessor controls the buffer to read the data of the address segment to be read in the chip according to the target address segment corresponding to the addressing mark in the erasing instruction, and when the read data is obtained, the microprocessor can also determine whether the first mark bit, the second mark bit and the third mark bit in the erasing instruction all indicate that the erasing instruction is in an effective state; if yes, executing the step that the microprocessor judges whether the address segment to be read comprises the target address segment according to the target address segment corresponding to the addressing identification; if not, the step of taking the read data as the data obtained by the read operation is performed.
In an optional embodiment, in order to ensure that the data is not lost during the read-write process, after the buffer buffers the target data in the erasing operation configuration under the control of the microprocessor, the method further includes: the microprocessor determines the block number of the corresponding target address segment of the target data in the chip; correspondingly, the microprocessor judges whether the address field to be read includes the target address field according to the target address field corresponding to the addressing identifier, including: and the microprocessor determines whether the target address segments of all the target address segments are judged to be read or not according to the number of the blocks.
FIG. 5 is a schematic diagram of a read operation processing flow in another processing method for erasing and writing data provided in an embodiment of the present disclosure, as shown in FIG. 5, firstly, determining validity of a flag bit based on a first flag bit, a second flag bit and a third flag bit, if invalid, proving that the erasing and writing operation before a chip is unsuccessful, and at this time, directly reading data stored in the chip to be read; if the data of the address field to be read is valid, the data of the address field to be read is required to be continuously read until all the data corresponding to the address field to be read are obtained, then whether the data of the address field to be read comprises the target address field or not is required to be determined, if the data of the address field to be read comprises the target address field, assignment processing is required to be executed, and if the data of the address field to be read does not comprise the target address field, the data obtained through reading can be directly used as the read data.
In this embodiment, compared with the processing manner of erasing global data, storing new data and reading new data in the chip in the prior art, the chip in this embodiment directly stores an erasing instruction, so that when the microprocessor reads data from the chip, the microprocessor can read the data and the erasing instruction currently stored in the chip, and assign a value to a target address segment corresponding to the erasing instruction in the read data based on the erasing instruction, that is, assign the data of the target address segment to the target data. In other words, the data obtained by the memory and read processing performed by the chip is equivalent to the data obtained by the erasing processing performed on the chip and read.
Fig. 6 is a flowchart of another method for processing a data erasing operation according to an embodiment of the disclosure, where, as shown in fig. 6, the method for processing a data erasing operation includes:
step 301, the microprocessor responds to the triggered erasing operation to the target data of the target address segment of the chip.
Step 302, updating the accumulated times of the erasing operation of the chip, and judging whether the updated accumulated times are larger than the allowable times of the allowable erasing operation of the chip preset by the equipment;
If not, go to step 304; if yes, go to step 303;
step 303, initiating alarm information to a user;
and continuing to execute the step 304 or ending the flow according to the confirmation information sent by the user.
Step 304, generating an erasing command according to the erasing operation configuration; the erasing instruction is used for storing an addressing identifier of the target address segment and an execution result identifier.
Step 305, the buffer caches the target address field information in the configuration of the erasing operation under the control of the microprocessor.
Step 306, the microprocessor sends the erasing command to the chip, and controls the buffer to send the target address segment information to the chip, so that the chip can execute the storage processing based on the erasing command and the target address segment information.
Unlike the foregoing embodiment, the present embodiment further includes: and the processor responds to the step of triggering the erasing operation on the target data of the target address section of the chip, updates the accumulated times of the erasing operation of the chip, judges whether the updated accumulated times are larger than the allowable times of the erasing operation of the chip or not, and can be matched with a driver to eliminate the erroneous writing if the erroneous writing condition of the erasing flag bit occurs in the market in actual use. The operation can be performed according to the initial value of the ECU within a certain count for allowing the erasing operation, and when the range of the erasing operation is exceeded, an alarm prompt is given, and at the moment, data recovery can be performed or the data of the driving cycle can be directly stored in EE when power is turned off.
The invention provides a processing method of data erasing operation, which comprises the steps of responding to triggering target data of a target address section of a chip through a microprocessor to carry out erasing operation, and generating an erasing instruction according to erasing operation configuration; the erasing instruction is used for storing an addressing identifier of the target address segment and an execution result identifier; the buffer is used for buffering the target address segment information in the erasing operation configuration under the control of the microprocessor; the microprocessor sends the erasing instruction to the chip, controls the buffer to send the target data to the chip so that the chip can execute storage processing based on the erasing instruction and the target address section information.
Fig. 7 is a block diagram of a data erasing operation processing system according to an embodiment of the present disclosure. For ease of illustration, only portions relevant to embodiments of the present disclosure are shown. Referring to fig. 7, the present disclosure provides a processing system for a data erasure operation, comprising: microprocessor 10, buffer 20 and chip 30;
The microprocessor 10 responds to the triggering to erase and write the target data of the target address section of the chip, and generates an erasing instruction according to the obtained erasing operation configuration; the erasing operation configuration stores target address segment information including target address segments and target data, and the erasing instruction is used for storing the target address segment information, corresponding addressing identifiers and execution result identifiers;
the buffer 20 is controlled by the microprocessor 10 to buffer the target address field information in the erasing operation configuration;
the microprocessor 10 sends an erasing instruction to the chip 30, and controls the buffer 20 to send target address information to the chip 30, so that the chip 30 performs a storage process based on the erasing instruction and the target address information.
Optionally, the microprocessor responds to the triggered read operation of reading the data of the address segment to be read of the chip 30, and receives the erasing command currently stored by the chip 30;
the microprocessor 10 controls the buffer 20 to read the data of the address field to be read in the chip 30 according to the target address field corresponding to the addressing mark in the erasing command to obtain read data;
The microprocessor 10 judges whether the address segment to be read comprises the target address segment according to the target address segment corresponding to the addressing identifier;
when the microprocessor 10 determines that the address field to be read comprises a target address field, performing assignment processing on target data corresponding to the target address field in read data according to an execution result identifier in the erasing instruction, and taking the assigned read data as data obtained by read operation;
when the microprocessor 10 determines that the address field to be read does not include the target address field, the read data is data obtained by a read operation.
Optionally, the execution result identifier includes a first identifier bit for indicating whether the erase operation is performed, a second identifier bit for indicating whether the erase operation is effective, a third identifier bit for indicating whether the target address segment of the erase is effective, and a fourth identifier bit for indicating the erase effect;
correspondingly, the generating the erasing command comprises the following steps:
and setting the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the addressing identification according to the erasing operation configuration so as to obtain an erasing instruction formed by the addressing identification and the execution result identification.
Optionally, when the microprocessor 10 determines that the address field to be read includes the target address field, the read data includes target data and non-target data; wherein the target data is data obtained by reading a target address field in address fields to be read of the chip 30, and the non-target data is data obtained by reading other address fields except the target address field in the address fields to be read of the chip 30;
performing assignment processing on target data corresponding to the target address segment in the read data according to the execution result identifier in the erasing instruction, and taking the assigned read data as data obtained by a read operation, wherein the assignment processing comprises the following steps:
determining the value of the assignment to the target data according to the fourth identification bit;
and assigning the target data in the read data as the assigned value, wherein the target data after being assigned with the value and the non-target data form the data obtained by the read operation.
Optionally, the microprocessor 10 controls the buffer 20 to read the data of the address segment to be read in the chip 30 according to the target address segment corresponding to the address identifier in the erasing command, so as to obtain read data, and further includes:
Determining whether a first identification bit, a second identification bit and a third identification bit in an erasing instruction all indicate that the erasing instruction is in a valid state;
if yes, executing the step that the microprocessor 10 judges whether the address segment to be read includes the target address segment according to the target address segment corresponding to the addressing identifier;
if not, the step of taking the read data as the data obtained by the read operation is performed.
Optionally, after the buffer 20 buffers the target data in the erasing configuration under the control of the microprocessor 10, the method further includes:
microprocessor 10 determines the number of blocks of the target data corresponding to the target address segment in chip 30;
correspondingly, the microprocessor 10 judges whether the address segment to be read includes the target address segment according to the target address segment corresponding to the address identifier, including:
the microprocessor 10 determines whether the judgment of whether the target address segment of all the target address segments is included in the address segment to be read is completed or not according to the number of blocks.
The invention provides a processing system for data erasing operation, which is used for carrying out the erasing operation on target data of a target address section of a chip by a microprocessor in response to triggering, and generating an erasing instruction according to the erasing operation configuration; the erasing instruction is used for storing an addressing identifier of the target address segment and an execution result identifier; the buffer is used for buffering the target data in the erasing operation configuration under the control of the microprocessor; the microprocessor sends the erasing command to the chip, and controls the buffer to send the target data to the chip for the chip to execute the storage processing based on the erasing command and the target data.
The electronic device provided in this embodiment may be used to execute the technical solution of the foregoing method embodiment, and its implementation principle and technical effects are similar, and this embodiment will not be described herein again.
Referring to fig. 8, a schematic diagram of a structure of an electronic device, which may be a terminal device or a server, suitable for use in implementing embodiments of the present disclosure is shown. The terminal device may include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a personal digital assistant (Personal Digital Assistant, PDA for short), a tablet (Portable Android Device, PAD for short), a portable multimedia player (Portable Media Player, PMP for short), an in-vehicle terminal (e.g., an in-vehicle navigation terminal), and the like, and a fixed terminal such as a digital TV, a desktop computer, and the like. The electronic device shown in fig. 8 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.
As shown in fig. 8, the electronic apparatus may include a processing device (e.g., a central processor, a graphics processor, or the like) 901, which may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 902 or a program loaded from a storage device 908 into a random access Memory (Random Access Memory, RAM) 903. In the RAM 903, various programs and data required for the operation of the electronic device are also stored. The processing device 901, the ROM 902, and the RAM 903 are connected to each other through a bus 904. An input/output (I/O) interface 905 is also connected to the bus 904.
In general, the following devices may be connected to the I/O interface 905: input devices 906 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 907 including, for example, a liquid crystal display (Liquid Crystal Display, LCD for short), a speaker, a vibrator, and the like; storage 908 including, for example, magnetic tape, hard disk, etc.; and a communication device 909. Communication means 909 may allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. While fig. 8 shows an electronic device having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via the communication device 909, or installed from the storage device 908, or installed from the ROM 902. When executed by the processing device 901, performs the above-described functions defined in the methods of the embodiments of the present disclosure.
It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
The computer-readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to perform the methods shown in the above-described embodiments.
Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (Local Area Network, LAN for short) or a wide area network (Wide Area Network, WAN for short), or it may be connected to an external computer (e.g., connected via the internet using an internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. The name of the unit does not in any way constitute a limitation of the unit itself, for example the first acquisition unit may also be described as "unit acquiring at least two internet protocol addresses".
The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Claims (10)

1. The processing method for the data erasing operation is characterized by being suitable for a processing system, wherein the processing system comprises a microprocessor, a buffer and a chip;
the processing method of the data erasing operation comprises the following steps:
the microprocessor responds to the triggering to carry out erasing operation on target data of a target address section of the chip, and generates an erasing instruction according to the obtained erasing operation configuration; the erasing operation configuration stores target address segment information including target address segments and target data, and the erasing instruction is used for storing the target address segment information, corresponding addressing identifiers and execution result identifiers; wherein the addressing identifier is used for identifying the number of address segments or BLOCKs to be erased;
the buffer is used for buffering the target address segment information in the erasing operation configuration under the control of the microprocessor;
the microprocessor sends the erasing command to the chip, and controls the buffer to send the target address information to the chip so that the chip can execute storage processing based on the erasing command and the target address information;
the execution result identifier comprises a first identifier bit used for indicating whether the erasure operation is performed, a second identifier bit used for indicating whether the erasure operation is effective, a third identifier bit used for indicating whether the target address segment of erasure is effective, and a fourth identifier bit used for indicating the erasure effect;
Correspondingly, the generating the erasing command comprises the following steps:
and setting the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the addressing identification according to the erasing operation configuration so as to obtain an erasing instruction formed by the addressing identification and the execution result identification.
2. The method of processing according to claim 1, further comprising:
the micro-processing responds to the triggered read operation of reading the data of the address segment to be read of the chip, and receives the erasing command stored currently by the chip;
the microprocessor controls the buffer to read the data of the address field to be read in the chip according to the target address field corresponding to the addressing mark in the erasing command to obtain read data;
the microprocessor judges whether the address segment to be read comprises the target address segment according to the target address segment corresponding to the addressing identifier;
when the microprocessor determines that the address field to be read comprises a target address field, performing assignment processing on target data corresponding to the target address field in read data according to an execution result identifier in the erasing instruction, and taking the assigned read data as data obtained by read operation.
3. The processing method according to claim 2, characterized by further comprising:
when the microprocessor determines that the address field to be read does not include the target address field, the read data are data obtained by the read operation.
4. A processing method according to claim 2 or 3, wherein when the microprocessor determines that the address field to be read includes the target address field, the read data includes target data and non-target data; the target data are data obtained by reading a target address field in an address field to be read of the chip, and the non-target data are data obtained by reading other address fields except the target address field in the address field to be read of the chip;
performing assignment processing on target data corresponding to the target address segment in the read data according to the execution result identifier in the erasing instruction, and taking the assigned read data as data obtained by a read operation, wherein the assignment processing comprises the following steps:
determining the value of the assignment to the target data according to the fourth identification bit;
and assigning the target data in the read data as the assigned value, wherein the target data after being assigned with the value and the non-target data form the data obtained by the read operation.
5. The processing method according to claim 2, wherein the microprocessor controls the buffer to read the data of the address field to be read in the chip according to the target address field corresponding to the address identifier in the erasing command, so as to obtain the read data, and further comprising:
determining whether a first identification bit, a second identification bit and a third identification bit in an erasing instruction all indicate that the erasing instruction is in a valid state;
if yes, executing the step that the microprocessor judges whether the address segment to be read comprises the target address segment according to the target address segment corresponding to the addressing identification;
if not, the step of taking the read data as the data obtained by the read operation is performed.
6. A processing method according to claim 2 or 3, wherein the buffer, under the control of the microprocessor, after buffering the target data in the erasure operation configuration, further comprises:
the microprocessor determines the block number of the corresponding target address segment of the target data in the chip;
correspondingly, the microprocessor judges whether the address field to be read includes the target address field according to the target address field corresponding to the addressing identifier, including:
And the microprocessor determines whether the target address segments of all the target address segments are judged to be read or not according to the number of the blocks.
7. A processing system for data erasure operations, comprising: a microprocessor, a buffer and a chip;
the microprocessor responds to the triggering to erase and write the target data of the target address section of the chip, and generates an erasing instruction according to the obtained erasing operation configuration; the erasing operation configuration stores target address segment information including target address segments and target data, and the erasing instruction is used for storing the target address segment information, corresponding addressing identifiers and execution result identifiers; wherein the addressing identifier is used for identifying the number of address segments or BLOCKs to be erased;
the buffer is used for buffering the target address segment information in the erasing operation configuration under the control of the microprocessor;
the microprocessor sends the erasing command to the chip, and controls the buffer to send the target address segment information to the chip so that the chip can execute storage processing based on the erasing command and the target address segment information;
The execution result identifier comprises a first identifier bit used for indicating whether the erasure operation is performed, a second identifier bit used for indicating whether the erasure operation is effective, a third identifier bit used for indicating whether the target address segment of erasure is effective, and a fourth identifier bit used for indicating the erasure effect;
correspondingly, the generating the erasing command comprises the following steps:
and setting the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the addressing identification according to the erasing operation configuration so as to obtain an erasing instruction formed by the addressing identification and the execution result identification.
8. The processing system of claim 7, wherein the processing system further comprises a processor configured to,
the micro-processing responds to the triggered read operation of reading the data of the address segment to be read of the chip, and receives the erasing command stored currently by the chip;
the microprocessor controls the buffer to read the data of the address field to be read in the chip according to the target address field corresponding to the addressing mark in the erasing command to obtain read data;
the microprocessor judges whether the address segment to be read comprises the target address segment according to the target address segment corresponding to the addressing identifier;
When the microprocessor determines that the address field to be read comprises a target address field, performing assignment processing on target data corresponding to the target address field in read data according to an execution result identifier in an erasing instruction, and taking the assigned read data as data obtained by read operation;
when the microprocessor determines that the address field to be read does not include the target address field, the read data are data obtained by the read operation.
9. An electronic device, comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing computer-executable instructions stored in the memory causes the at least one processor to perform the method of any one of claims 1 to 6.
10. A readable storage medium having stored therein computer executable instructions which, when executed by a processor, implement the method of any one of claims 1 to 6.
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