CN111158456A - Low-energy-consumption management system and management method for large-scale hard disk group - Google Patents
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Abstract
The invention discloses a low-energy-consumption management system and a management method of a large-scale hard disk group, wherein the management system comprises a central control unit, a communication unit, a plurality of shift register extension units and a plurality of hard disk switch execution units; the communication unit is used for receiving the data transmitted by the upper computer and transmitting the data to the central control unit; the central control unit is used for processing the data of the upper computer, analyzing the on-off control requirement of the hard disk power supply to be controlled, generating a control instruction for the hard disk switch execution unit according to the analyzed control requirement and storing the control instruction into the corresponding shift register extension unit; the shift register extension unit sends the control instruction stored by the central control unit to the corresponding hard disk switch execution unit under the control of the central control unit; and the hard disk switch execution unit controls the on-off state of the corresponding hard disk power supply according to the received control instruction.
Description
Technical Field
The invention belongs to the technical field of data storage and energy conservation, and particularly relates to a low-energy-consumption management system and a management method for a large-scale hard disk group.
Background
With the continuous development of global modern information technology, the rise of big data and cloud computing and the continuous improvement of social productivity level, the data generated by human production and life are continuously increased and the increasing speed is faster and faster. The scholars indicate that under the current environment, newly generated data every 18 months is equal to the sum of data volumes generated by the past, and a plurality of large-scale enterprise-level applications oriented to mass data appear. Statistics show that the global data volume reaches 1.8ZB (1.8 trillion GB) only in 2011, and the data is rapidly increasing, and by 2015, the global data storage volume reaches 8.61ZB, and the data is only increasing rapidly. The large-scale data storage requirement makes the scale of the storage system larger and larger, the scale of the storage nodes in the modern data center is hundreds of thousands, and the scale of the storage nodes is smaller and reaches tens of thousands.
With the increasing scale of storage, the problems faced by storage systems are increasing. Through years of research and development, efficiency and reliability of data storage systems are greatly improved, but energy consumption for storing data is not sufficiently concerned. However, in certain specific scenarios, the problem of energy consumption of storage will be a key point of the overall storage system, and energy conservation has become a factor that must be considered in various designs. A contradiction exists between large-scale storage and low energy consumption, a large number of hard disks are necessarily needed for large-scale storage, and the power is increased due to the fact that a large number of hard disks are started, so that energy consumption is increased. The design aims at solving the contradiction, so that the large-scale hard disk can meet the requirement of mass data storage, and the on-off of the hard disk can be artificially controlled to reduce the energy consumption of a storage system.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a low-energy-consumption management method and device for a large-scale hard disk group storage system. The storage capacity of information can be greatly improved, the hard disk resources are reasonably utilized, and meanwhile, according to actual needs, a large amount of unnecessary energy consumption caused by the hard disk during working is reduced through control over the hard disk, so that the energy is saved. The invention is particularly suitable for the areas with limited energy sources or areas with higher requirements on energy sources.
The invention is realized by the following technical scheme:
a low energy consumption management method of large-scale hard disk groups comprises a central control unit, a communication unit, a plurality of shift register extension units and a plurality of hard disk switch execution units;
the communication unit is used for receiving the data transmitted by the upper computer and transmitting the data to the central control unit;
the central control unit is used for processing the data of the upper computer, analyzing the on-off control requirement of the hard disk power supply to be controlled, generating a control instruction for the hard disk switch execution unit according to the analyzed control requirement and storing the control instruction into the corresponding shift register extension unit;
the shift register extension unit sends the control instruction stored by the central control unit to the corresponding hard disk switch execution unit under the control of the central control unit;
and the hard disk switch execution unit controls the on-off state of the corresponding hard disk power supply according to the received control instruction.
A low energy consumption management system of large-scale hard disk group comprises a central control unit, a communication unit, a shift register extension unit and a hard disk switch execution unit;
the communication unit is connected with the central control unit and used for receiving the data transmitted by the upper computer and transmitting the data to the central control unit;
the central control unit is connected with a plurality of shift register extension units, each shift register extension unit comprises four cascaded shift registers, and each shift register is connected with 4 hard disk switch execution units;
each hard disk switch execution unit comprises a driving chip, each driving chip is connected with 4 relays, and the 4 relays are respectively arranged on four power lines (a 12-volt positive power line, a 5-volt positive power line and two ground lines) of a single hard disk to control the on-off state of the lines.
In the above technical solution, the controller adopted by the central control unit is a domestic chip STC90C58RD +.
In the above technical solution, the communication mode adopted by the communication unit is USB communication, and the adopted USB communication master control chip is a CH372 USB bus chip designed and produced by nyuqin.
In the above technical solution, the model of the driving chip is SN 55451.
In the above technical solution, the model number of the shift register is 74HC 595.
In the above technical solution, the shift pulses and the data output pulses of all the shift registers respectively make the same pulse signal, that is, all the shift pulse signals occupy one output port of the central control unit, and all the data output pulse signals occupy one output port of the central control unit; and the data input ends of each shift register respectively occupy one output port of the central control unit one by one.
In the technical scheme, the central control unit and each shift register extension unit are connected by using a double-row horn base with ten pins, the ten pins are divided into five groups, two pins in each group are backup to each other, the ten pins are connected with five lines in total, and the ten pins are respectively provided with a power line, a ground line, a data input line, a shift pulse line and a data output pulse line.
The invention has the advantages and beneficial effects that:
in recent years, with the rise of big data technology, research on data storage is attracting more and more attention. However, current research is mainly focused on the reliability and efficiency of storage, and research on energy consumption for storing data is not focused sufficiently. However, in some specific scenarios, the problem of energy consumption of storage will be a key point of the whole storage system, and energy conservation has become one of the factors that must be considered in various designs. The invention is to research the energy control aspect of the storage system from the energy perspective and provides an effective and feasible energy control scheme.
In a large-scale hard disk group, not all hard disks are involved in each read-write operation, the invention can reduce the power of the system and save energy by detecting which hard disks need to be used, turning on the power of the part of hard disks and turning off the power of the hard disks which do not need to be used.
The hardware control system of the invention is logically mainly composed of four units: the system comprises a central control unit, a communication unit, a shift register extension unit and a hard disk switch execution unit, wherein the four units are independent and definite in division work, and effective data transmission is carried out among the four units. The communication unit is mainly responsible for receiving data transmitted by the upper computer and transmitting the data to the data processing part; the data processing part is mainly used for processing the data transmitted by the communication unit and sending the processed data to the shift register expansion unit, the shift register expansion unit is mainly used for expanding the output port of the control part so as to increase the number of the controlled hard disks, and the shift register expansion unit sends instructions of corresponding actions to the hard disk switch execution unit; the hard disk switch execution unit is responsible for receiving a command sent by the data processing part and finally switching on or off the power supply of the specified hard disk.
Drawings
Fig. 1.1 is an overall circuit diagram.
Fig. 1.2 is an overall circuit diagram.
Fig. 2 is a circuit diagram of a communication unit.
Fig. 3 is a circuit diagram of a shift register module.
Fig. 4 is a diagram of the interface definition for a ten pin double row bull's horn socket.
Fig. 5 is a circuit diagram of a hard disk switch execution unit.
For a person skilled in the art, other relevant figures can be obtained from the above figures without inventive effort.
Detailed Description
In order to make the technical solution of the present invention better understood, the technical solution of the present invention is further described below with reference to specific examples.
Example one
A low energy consumption management method of large-scale hard disk groups comprises a central control unit, a communication unit, a shift register extension unit and a hard disk switch execution unit;
the communication unit is used for receiving data (data for controlling which hard disk is required to be opened or closed) transmitted by the upper computer and transmitting the data to the central control unit;
the central control unit is used for processing the data of the upper computer, analyzing the on-off control requirement of the hard disk power supply to be controlled, generating a control instruction for the hard disk switch execution unit according to the analyzed control requirement and storing the control instruction into the corresponding shift register extension unit;
the shift register extension unit sends the control instruction stored by the central control unit to the corresponding hard disk switch execution unit under the control of the central control unit;
and the hard disk switch execution unit controls the on-off state of the corresponding hard disk power supply according to the received control instruction.
Example two
A low energy consumption management system of large-scale hard disk group comprises a central control unit, a communication unit, a shift register extension unit and a hard disk switch execution unit;
the communication unit is connected with the central control unit and used for receiving the data transmitted by the upper computer and transmitting the data to the central control unit;
the central control unit is connected with a plurality of shift register extension units, each shift register extension unit comprises four cascaded shift registers, and each shift register is connected with 4 hard disk switch execution units;
each hard disk switch execution unit comprises a driving chip, each driving chip is connected with 4 relays, and the 4 relays are respectively arranged on four power lines (a 12-volt positive power line, a 5-volt positive power line and two ground lines) of a single hard disk to control the on-off state of the lines.
The following describes specific circuit connection relationships among the units in detail with reference to the accompanying drawings:
referring to fig. 1.1-1.2, the controller adopted by the central control unit is a domestic chip STC90C58RD +, which is a domestic chip with relatively low price, the memory of 1280 bytes and the ROM of 32K, EEPROM K, wherein the RAM of 1280 bytes is divided into 256 bytes of on-chip RAM and 1024 bytes of extended RAM, the clock main frequency used by the system is 11.0592 megabytes, the chip has the characteristics of low price, low power consumption and strong anti-interference performance, and the instruction set of the chip is fully compatible with the instruction set of 8051 series, so as to meet the requirement of the design for data processing. As can be seen from the figure, 8 data lines of a P1 port of the STC90C58RD + are connected with a USB communication chip CH372 of the communication unit, the STC90C58RD + reads data from the P1 port and stores the data in the memory, and the data returned to the upper computer is also written out through the P1 port; p3.2, P3.4, P3.5 and P3.6 of P3 of STC90C58RD + are also respectively connected with INT, A0, WR and RD ports of the USB communication chip CH372 for controlling the action of the USB communication chip CH 372; a crystal oscillator with the frequency of 11.0592 Mm is connected between the XTAL1 and the XTAL2, and the two ends are grounded after passing through a capacitor with the frequency of 35pF, so that a stable and reliable clock signal is provided for the system; p2.1 and P2.2 of a P0 port and a P2 port of the STC90C58RD + are used for connecting a shift register in a switch part of the next stage, wherein eight ports of the P0 are respectively connected with data input pins of the shift register connected with eight interfaces and used for transmitting data to the shift register; the eight interfaces share one shift pulse signal and one output pulse signal, so that the occupation of an input/output port of the central control unit is saved, wherein a port P2.1 is used for connecting a shift pulse signal input port of the shift register, and a port P2.2 is used for connecting an input port of the shift register, which outputs the pulse signal; a pull-up resistor is added to each output line in the circuit diagram so as to guarantee driving capability and stability.
The communication unit is a hub connected with an upper computer and a lower computer (namely a central control unit) in the system and is a key part of data transmission. The communication mode specifically adopted by the communication unit is USB communication, the adopted USB communication main control chip is a CH372 USB bus chip designed and produced by Nanjing Qin constant electronics, the function is strong, a USB protocol is built in, the configuration and the use are very simple, and the performance is very good. The CH372 chip can operate in both the built-in mode and the external mode, in which the default endpoint of the CH372 chip is endpoint 0, which will automatically process all transactions from this endpoint, and therefore the communication program is also very concise and clear to write. Several important pins in the CH372 chip are data D0-D7, read RD, write WR, chip select CS, address a0, and interrupt INT, where CS is a strobe signal of the chip, and when CS is low, the chip is selected to start working, and when CS is high, the chip does not work; in the design, only one CH372 chip is used, so that selection among a plurality of chips is not needed, and the chip selection signal is directly connected to the ground end, namely the chip selection signal is always effective; a0 is used to indicate whether the central control unit is a command or data to transmit data of CH372, when a0 is low, it indicates that data is input, and when a0 bit is high, it indicates that a command is transmitted; RD and WR are used in combination, and read and write are not needed in the central control unit, and both are high level; when the central control unit needs to read data, it needs to first set a0 to low level, at the same time, RD to low level, WR to high level, then read out the data through 8-bit data lines and save them, and then restore RD to high level; when the central control unit needs to write data or a command, it is necessary to set the state of a0 first, a0 low represents write data, high represents write command, RD is high, WR is low, then the command or data is written through the 8-bit data line, and WR and a0 are restored to high. Referring to fig. 2, in the design of the present design, 8 data pins of the CH372 chip are connected to the P1 port of the central control unit for the central control unit to read and write data through USB; in addition, three pins of A0, WR and RD of the CH372 chip are respectively connected to three ports of P3.4, P3.5 and P3.6 of the central control unit and used for setting the state of the CH372 chip, and an INT pin of the CH372 chip is connected to an INT0(P3.2) port of the central control unit and used for triggering interrupt transmission; GND and CS of the CH372 chip are grounded together, so that the CH372 chip is always in a working state, and a Vin end (power supply positive electrode input end) is connected with a V5 end in a circuit diagram to provide a 5-volt power supply for the chip.
The shift register extension unit is used for realizing the output port extension of the central control unit so as to realize the appointed control of more hard disk switch execution units. The scheme is essentially a method for converting serial data into parallel data, and a shift register can set data in the shift register through three input ends of data, a shift pulse input end and an output pulse input end and outputs the data after the setting is finished. In our design, we finally use the output end of the shift register to control the hard disk switch execution unit, rather than directly controlling through the output port of the central control unit, or we can extend the output port of the register to the output port of the central control unit. Thus, three output ports of the central control unit are used for connecting three ports of data input, shift pulse input and data output pulse input of the register, and 8 output ports can be expanded. Therefore, three ports of the central control unit can be used for expanding a plurality of output ports, and 8 output ports can be expanded by one port of each cascade, but the number of stages of the cascade is generally not more than four to five due to driving capability and the like, so that the standard design is to cascade four shift registers, and the three output ports of the central control unit are expanded into 32 output ports (namely, four shift registers are cascaded, and each shift register has 8 output ports). According to the above scheme, if we need at least 256 outlets, it is necessary to design eight such interfaces (i.e. 8 × 32) in the control portion, and then the eight such interfaces need 24 outlets of the central control unit in total, which still exceeds the number of outlets that can be provided by the central control unit. In this regard, further optimization was performed: it is known through analysis that data at the data input end of each 74HC595 shift register chip is different, but signals at the shift pulse input end and the data output pulse input end of each 74HC595 chip are the same, so that the shift pulses and the data output pulses of all 74HC595 chips respectively make the same pulse signal, that is, all shift pulse signals occupy one output port of the central control unit, all data output pulse signals occupy one output port of the central control unit, and the data input ends of each shift register respectively occupy one output port of the central control unit one by one, so that eight interfaces connecting the shift registers (four cascaded shift registers, exactly 256 output ports) occupy only 10 output ports of the central control unit in total.
Furthermore, the QH' pin of the shift register is used to cascade the pin of the next stage shift register, and connect it with the data line pins (pin No. 3 and pin No. 4) of the output interface. An RC reset circuit is designed at an enabling end OE of the shift register, so that the OE of a chip is in a high level when the chip is powered on, an output pin of the shift register is in a high-impedance state, initialization operation is conducted on the shift register in the period of time (all positions of the shift register are set to be 1), 8 output ends of the shift register are divided into two groups which are adjacent to each other, the four groups are in total, and the four groups are respectively connected with four hard disk switch execution units (namely each group is respectively connected with one hard disk switch execution unit) to control the action of the execution units. Fig. 3 is a circuit diagram of a shift register module.
Furthermore, the central control unit and each shift register extension unit are connected by using a ten-pin double-row horn seat DIP10, the ten pins are divided into five groups, and two pins in each group are backup to each other, so that the reliability of data transmission is improved. The ten pins are connected with five lines in total, and are respectively provided with a power line, a ground line, a DATA input line, a shift pulse line and a DATA output pulse line, the specific distribution is shown in figure 4, in the figure, GND connected with pins No. 1 and No. 2 refers to the ground line, DATA connected with pins No. 3 and No. 4 refers to the DATA input line in the shift register, RCLK connected with pins No. 5 and No. 6 refers to the DATA output pulse line in the shift register, SRCLK connected with pins No. 7 and No. 8 refers to the shift pulse line in the shift register, VCC connected with pins No. 9 and No. 10 refers to the power line, and the two ends of the power line and the ground line are divided into columns to avoid the possibility of short circuit caused by no contact.
The hard disk switch execution unit is an execution mechanism of a switch instruction sent by the central control module. Because each hard disk has four power lines, namely a 12-volt positive power line, a 5-volt positive power line and two ground lines, to control the on-off of the hard disk power supply, the four lines should be simultaneously switched on or off, each hard disk switch execution unit needs to comprise four relays, and the four lines are controlled to be simultaneously switched on or switched off by the four relays; to make these four relays act simultaneously, the driving capability of the shift register is obviously insufficient, so that each hard disk switch execution unit is added with a driving chip SN55451, which is actually a two-way and gate chip, and one end (pin 1A and pin 2A) of the input of the and gate is connected with high level, so that the output of the chip can be controlled by connecting the other end with the data output port of the shift register, and when the input end is high, the output is high, and when the input end is low, the output is low. The SN55451 can flow current which reaches 300mA at most, and can completely drive four relays (the driving current required by each relay does not exceed 30mA at most). In addition, each hard disk interface is provided with two hard disk indicating lamps, one is called a status indicating lamp (an LED1 in fig. 5) for indicating the working status of the hard disk, and the status indicating lamp is connected with four relays in parallel and automatically turns on and off along with the switching status of the hard disk; the other is called a position indicator lamp (LED 2 in fig. 5) for indicating the position of the hard disk, the two indicator lamps are respectively connected to two paths of the driving chip SN55451 and respectively controlled by two adjacent shift register output ports, and fig. 5 is a circuit diagram of the hard disk switching power supply module.
The invention has been described in an illustrative manner, and it is to be understood that any simple variations, modifications or other equivalent changes which can be made by one skilled in the art without departing from the spirit of the invention fall within the scope of the invention.
Claims (8)
1. A low-energy-consumption management method for large-scale hard disk groups is characterized by comprising the following steps: the system comprises a central control unit, a communication unit, a plurality of shift register extension units and a plurality of hard disk switch execution units;
the communication unit is used for receiving the data transmitted by the upper computer and transmitting the data to the central control unit;
the central control unit is used for processing the data of the upper computer, analyzing the on-off control requirement of the hard disk power supply to be controlled, generating a control instruction for the hard disk switch execution unit according to the analyzed control requirement and storing the control instruction into the corresponding shift register extension unit;
the shift register extension unit sends the control instruction stored by the central control unit to the corresponding hard disk switch execution unit under the control of the central control unit;
and the hard disk switch execution unit controls the on-off state of the corresponding hard disk power supply according to the received control instruction.
2. A low energy consumption management system of large-scale hard disk group, its characterized in that: the system comprises a central control unit, a communication unit, a shift register extension unit and a hard disk switch execution unit;
the communication unit is connected with the central control unit and used for receiving the data transmitted by the upper computer and transmitting the data to the central control unit;
the central control unit is connected with a plurality of shift register extension units, each shift register extension unit comprises four cascaded shift registers, and each shift register is connected with 4 hard disk switch execution units;
each hard disk switch execution unit comprises a driving chip, each driving chip is connected with 4 relays, and the 4 relays are respectively arranged on four power lines of a single hard disk to control the on-off state of the lines.
3. The system of claim 2, wherein the system comprises: the controller adopted by the central control unit is a domestic chip STC90C58RD +.
4. The system of claim 2, wherein the system comprises: the communication mode adopted by the communication unit is USB communication, and the adopted USB communication main control chip is a CH372 USB bus chip designed and produced by Nanjing Qin constant electronics.
5. The system of claim 2, wherein the system comprises: the model of the driving chip is SN 55451.
6. The system of claim 2, wherein the system comprises: the model of the shift register is 74HC 595.
7. The system of claim 2, wherein the system comprises: the shift pulses and the data output pulses of all the shift registers respectively enable the same pulse signal, namely all the shift pulse signals occupy one output port of the central control unit, and all the data output pulse signals occupy one output port of the central control unit; and the data input ends of each shift register respectively occupy one output port of the central control unit one by one.
8. The system of claim 2, wherein the system comprises: the central control unit and each shift register extension unit are connected by using a ten-pin double-row horn base, the ten pins are divided into five groups, two pins in each group are backup to each other, the ten pins are connected with five lines in total and respectively provided with a power line, a ground line, a data input line, a shift pulse line and a data output pulse line.
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Application publication date: 20200515 |