CN111149232B

CN111149232B - Fabrication of carbon nanotube thin film transistor backplane and display integration thereof

Info

Publication number: CN111149232B
Application number: CN201780092111.1A
Authority: CN
Inventors: 李华平
Original assignee: ATOM NANOELECTRONICS Inc
Current assignee: ATOM NANOELECTRONICS Inc
Priority date: 2017-05-08
Filing date: 2017-05-08
Publication date: 2024-05-14
Anticipated expiration: 2037-05-08
Also published as: KR20200024771A; CN111149232A; WO2018208284A1; KR102366816B1; KR102511414B1; KR20220025950A

Abstract

Methods for producing single-walled carbon nanotubes (SWCNTs) and integrating them into existing TFT backplane manufacturing lines are provided. SWCNT TFT backplanes exhibit equivalent or better quality factors such as high field emission mobility, low temperature fabrication, good stability, uniformity, scalability, flexibility, transparency, mechanical deformability, low voltage and power consumption, bendability, and low cost compared to LTPS and oxide TFT backplanes. Methods and processes for integrating SWCNTs into existing TFT backplane manufacturing lines are also provided that can begin preliminary experiments and mass production without additional capital requirements.

Description

Fabrication of carbon nanotube thin film transistor backplane and display integration thereof

Technical Field

A method for fabricating and integrating carbon nanotube thin film transistor backplanes into displays.

Background

Flat Panel Displays (FPDs) are penetrating consumer electronics integrated with display functions. In existing FPDs, thin Film Transistor (TFT) -Liquid Crystal Displays (LCDs) occupy the current display market, with 97.5% market share in 2013, although there are some limitations in terms of color, contrast and response time. Recently, display capital expenditures have rapidly shifted from TFT-LCDs to AMOLEDs, not only because of the excellent display quality of AMOLEDs in terms of color, contrast and response time, but also the cost advantages of large AMOLEDs manufactured in 8 generations or larger over TFT-LCDs. In order to be able to fabricate AMOLED of greater than Gen 8 size, there are several technical challenges including limitations in conventional active matrix Thin Film Transistor (TFT) backplanes. (see, e.g., G.Gu and S.R.Forrest, IEEE Journal of Selected Topics in Quantum Electronics, vol.4, pp.83-99,1998, the disclosures of which are incorporated herein by reference.)

The current active matrix TFT backplane for driving AM-LCD pixels is generally made of amorphous silicon (a-Si) having low mobility (-1 cm ²V^-1s^-1) and poor stability, and thus is not suitable for AMOLED pixels. (see M.J.Powell, IEEE Transactions on Electron Devices, vol.36, pp.2753-2763,1989, the disclosure of which is incorporated herein by reference.) due to these drawbacks, current AMOELD displays are driven by low temperature polysilicon (poly-Si) TFTs, which suffer from high manufacturing costs and time, as well as device size, orientation and non-uniformity limitations, all of which present serious challenges to increasing display size and product yield. ( See, e.g., c. -p.chang and y. -c.s.wu, IEEE electronics DEVICE LETTERS, vol.30, pp.130-132,2009; y. -J.park, M. -H.Jung, S. -H.park and O.Kim, japanese Journal of APPLIED PHYSICS, vol.49, pp.03CD01,2010; and p. -s.lin and t. -s.li, IEEE electronics DEVICE LETTERS, vol.15, pp.138-139,1994, each of which disclosures are incorporated herein by reference. )

Although Low Temperature Polysilicon (LTPS) backplanes are in mass production up to 5.5 generations, LTPS fabrication techniques including Excimer Laser Annealing (ELA) and Advanced Solid Phase Crystallization (ASPC) create substantial obstacles to the scale-up of >8 generations. For example, both ELA and ASPC waferworks have very slow overall average cycle times that is more than twice as long as the typical 60 seconds of a-Si. This doubles the capital cost of the a-Si array process. Furthermore, the scaling up of ELA may lead to non-uniformity and array failure. The high temperature of the ASPC process (about 600 ℃) requires expensive glass to avoid glass warpage and shrinkage. (b. Young, information Display, vol.10, pp.24,2010, the disclosures of which are incorporated herein by reference.) the higher processing temperatures and more complex photomasks required to fabricate LTPS increase capital expenditure and difficulty in achieving high yields. This makes a 5"LTPS TFT-LCD (1920×1080 pixels) 14% more expensive than an a-Si TFT-LCD of the same size.

Therefore, there is a need for manufacturing techniques that allow for the production of cheaper TFT backplanes.

Disclosure of Invention

Methods for fabricating and integrating carbon nanotube thin film transistor backplanes into displays are provided.

Many embodiments are directed to a method for fabricating a single-walled carbon nanotube thin film transistor backplane, the method comprising:

Providing a substrate;

depositing an insulator comprising a thin film layer of single-walled carbon nanotubes atop the substrate; and

Patterning at least the drain and source electrodes, the dielectric, one or more top gate electrodes, and one or more pixel electrodes atop the insulator using a photomask and photolithographic process.

In other embodiments, the insulator is deposited by a spray technique selected from the group consisting of aerosol spray, air spray, and ultrasonic spray.

In some such embodiments, the single-walled carbon nanotube aerosol is formed by a technique selected from the group consisting of: ultrasonic atomization at a voltage in the range of 20V to 48V and pneumatic atomization with an atomizer flow rate of about 600 cubic centimeters per minute to generate aerosols having diameters of about 1 μm to 5 μm; and wherein the aerosol is carried to the spray head by a carrier gas flow rate of about 10 to 20 cubic centimeters per minute.

In yet other such embodiments, the single-walled carbon nanotube aerosol is formed from an aqueous solution of single-walled carbon nanotubes that are sonicated in an ultrasound nozzle and emitted at a carrier gas flow rate of about 10 to 20 cubic centimeters per minute.

In still other embodiments, the insulator is printed atop the substrate using aerosol jet printing as a single-walled carbon nanotube aerosol.

In some such embodiments, the single-walled carbon nanotube aerosol is formed by a technique selected from the group consisting of: ultrasonic atomization at a voltage in the range of 20V to 48V with an atomizer flow rate of about 600 cubic centimeters per minute to produce pneumatic atomization of aerosols having diameters of 1 μm to 5 μm; and wherein the aerosol is carried by a carrier gas flow of 10 to 20 cubic centimeters per minute to a fine nozzle of less than 100 μm and is concentrated by a sheath gas flow of 25 to 50 ccm.

In other such embodiments, the line width deposited is less than 10 μm with an alignment accuracy of <2 μm.

In yet other embodiments, the single-walled carbon nanotubes are high purity single-chiral single-walled carbon nanotubes.

In some such embodiments, the single-walled carbon nanotubes have an index selected from the group consisting of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2), and mixtures thereof.

In yet other embodiments, the single-walled carbon nanotube film is formed from a plurality of discrete films.

In some such embodiments, a single-walled carbon nanotube film is patterned separately using a photomask lithography process.

In still other embodiments, the method further comprises treating the single-walled carbon nanotube film with an acid gas.

In some such embodiments, the acid gas is deposited via aerosol spray coating.

In yet other such embodiments, the method further comprises cleaning the treated single-walled carbon nanotube film with isopropyl alcohol.

In yet other such embodiments, the method further comprises sintering the single-walled carbon nanotube film at a temperature from about 100 ℃ to 200 ℃.

In yet other embodiments, forming a thin film with sub-threshold leakage current includes:

spin-coating a photoresist on the single-walled carbon nanotube film;

Defining a pattern on top of the photoresist by lithography to create defined photoresist and areas of undefined photoresist;

solution developing the defined pattern to form a developed photoresist; and

Plasma or wet etching of the single-walled carbon nanotube film using the developed photoresist to form a patterned single-walled carbon nanotube film.

In yet other embodiments, the method includes integrating a single-walled carbon nanotube thin film transistor backplane into a display device.

Various other embodiments are directed to systems configured to deposit single-walled carbon nanotube thin film transistor backplanes, the systems comprising:

a plurality of printheads mounted in association with the mobile station;

the plurality of printheads being in fluid communication with a solution of an aqueous solution of single-walled carbon nanotubes for depositing a thin film of single-walled carbon nanotubes atop a substrate deposited on a moving stage; and

Wherein the print head is integrated with a photomask and a photolithographic process for patterning and forming at least drain and source electrodes, a dielectric, one or more top gate electrodes and one or more pixel electrodes on top of the deposited thin film.

Additional embodiments and features are set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the specification or may be learned by practice of the invention. A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings which form a part of this disclosure.

Drawings

The present specification will be more fully understood with reference to the following drawings and data graphs, which are presented as exemplary embodiments of the invention and should not be construed as a complete description of the scope of the invention, wherein:

Fig. 1a and 1b provide data graphs showing absorption spectra and electrical properties of single-walled carbon nanotubes according to embodiments of the present invention.

Fig. 2a and 2b provide schematic illustrations of an exemplary vertical luminescence transistor according to an embodiment of the present invention.

Fig. 3 a-3 k provide schematic illustrations of a method of forming an etch stop vertical luminescence transistor according to an embodiment.

Fig. 4 a-4 f provide schematic illustrations of a method of forming a vertical luminescence transistor according to an embodiment.

Fig. 5a to 5c provide schematic illustrations showing: a) a plurality of spray heads for a solution spray apparatus in a mobile station, b) a spray gun for ultrasonic spraying, and c) an aerosol spray system, each in accordance with an embodiment of the present invention.

Fig. 6 provides an image of a spray gun sprayed carbon nanotube film according to an embodiment of the present invention.

Fig. 7 provides an image of an aerosol-sprayed carbon nanotube film according to an embodiment of the present invention.

Fig. 8 is an Atomic Force Microscope (AFM) image of a spray gun sprayed single wall carbon nanotube film according to an embodiment of the present invention.

Fig. 9 is an Atomic Force Microscope (AFM) image of an aerosol-sprayed single-walled carbon nanotube film according to an embodiment of the present invention.

Fig. 10 provides a flowchart illustrating a manufacturing process for manufacturing a top gate carbon nanotube TFT backplane according to an embodiment of the present invention.

Fig. 11 provides an image of an aerosol printer for printing a carbon nanotube pattern on drain/source marks according to an embodiment of the present invention.

Fig. 12 provides photographs and optical images of drain/source marks prior to aerosol printing of single-walled carbon nanotube patterned films in accordance with an embodiment of the present invention.

Fig. 13 provides photographs and optical images of aerosol printed single-walled carbon nanotube patterned films on drain/source marks according to embodiments of the present invention.

Fig. 14 provides an optical image of an aerosol jet printed carbon nanotube film according to an embodiment of the present invention, and wherein the inset is an SEM image.

Fig. 15a provides an optical image of an aerosol jet printed carbon nanotube film on a lithographically patterned electrode, and wherein fig. 15b and 15c are IV curves of such carbon nanotube film showing pure semiconductor properties, in accordance with an embodiment of the present invention.

Fig. 16 provides a photographic image of an apparatus having multiple aerosol jet printer heads mounted on a roll-to-roll table in accordance with an embodiment of the present invention.

Fig. 17 provides a flowchart illustrating a manufacturing process for manufacturing a standard bottom gate a-Si TFT backplane according to the prior art.

Fig. 18 provides a flowchart illustrating a manufacturing process for manufacturing a top gate carbon nanotube TFT backplane according to an embodiment of the present invention.

Fig. 19 provides a flowchart illustrating a manufacturing process for manufacturing a top gate printed carbon nanotube TFT backplane according to an embodiment of the present invention.

Fig. 20 provides a cross-sectional view of a single-walled carbon nanotube thin film transistor in accordance with an embodiment of the present invention.

Detailed Description

Turning to the drawings, apparatus, materials and methods for producing and integrating single-walled carbon nanotubes (SWCNTs) into existing TFT backplane manufacturing lines. In particular, SWCNT TFT backplanes exhibit equivalent or better quality factors, such as high field emission mobility, low temperature fabrication, good stability, uniformity, scalability, flexibility, transparency, mechanical deformability, low voltage and power, flexibility, and low cost, as compared to LTPS and oxide TFT backplanes. Accordingly, many embodiments are directed to methods and processes for integrating SWCNT technology into existing TFT backplane manufacturing lines that can begin preliminary experiments and mass production without additional capital expenditure. Further, other embodiments are directed to methods and processes for integrating such SWCNT TFT backplanes into video displays, which in various embodiments include high-end glass-free 3-D and ultra-clear panel displays such as head-mounted displays (HMDs). Hereinafter, carbon nanotubes refer to single-walled carbon nanotubes, including high purity single-chiral SWCNTs, such as SWCNTs having an index of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2), and mixtures thereof.

Active Matrix Organic Light Emitting Displays (AMOLED) are attractive due to their power saving, ultra high definition and wide viewing angle. In particular, by directly modulating the charge carriers of the light emitting material, advances in Organic Light Emitting Transistors (OLET) exhibit improved external efficiency over Organic Light Emitting Diodes (OLEDs). In addition, by providing a short channel length, a vertical structure is introduced in the OLET to avoid the inherently low mobility of the organic material, so that high conductivity can be achieved at low power and low voltage, thus enhancing the energy conversion efficiency, lifetime and stability of the organic material. Moreover, combining Thin Film Transistor (TFT) switches with OLED light emitting properties in a single device results in simplified manufacturing processes and reduced costs. However, the technical challenges of forming the underlying TFT backplane in these devices limit display size variations and cost reduction. As will be described below, the use of novel SWCNT materials and fabrication combinations, such as highly transparent porous conductive SWCNT electrodes, enables the formation of SWCNT TFTs that can be incorporated into fabrication lines for TFT backplanes, overcoming the limitations of display backplanes fabricated with amorphous silicon/single crystal silicon/polysilicon, metal oxides, and organic materials, and will be suitable for a variety of needs.

Accordingly, various embodiments are directed to methods of integrating printed SWCNT technology into an a-Si TFT-LCD manufacturing line. Using such SWCNT backplanes, higher mobility enables LTPS TFT backplanes with higher pixel density, lower power consumption, and integration with driving circuitry on a glass substrate.

SWCNT selection/purification techniques

With the advent of separation technology, ultrapure single-walled carbon nanotubes having a purity of greater than 95% can be produced and scaled up for a large number of operations. Using these processes, high purity single chiral SWCNTs with various indices can be produced. In many embodiments, high purity single chiral SWCNTs and mixtures comprising SWCNTs having an index of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2) are formed. The NIR-Vis absorption spectra of the (6, 5) SWCNTs are presented in FIG. 1a to show the main S11 and S22 peaks at 978nm and 562 nm. Their electrical properties are characterized as the characteristics of a pure semiconductor with negligible off-current (I-V curve is provided in fig. 1 b). Thus, using such techniques, the purity of these materials can be ensured via conventional spectroscopy, and their electrical properties determined for selection.

TFT backplane fabrication

Embodiments are directed to methods and processes for replacing amorphous silicon layers with ultra-pure semiconductor single-walled carbon nanotubes in an industrial TFT backplane manufacturing line. In particular, as shown in fig. 2a and 2b, CNT layers according to embodiments may be implemented in bottom gate etch stop CNT TFTs (e.g., fig. 2 a) and bottom gate backside channel etch CNT TFTs (e.g., fig. 2 b), among others. However, while the method and process will be described with reference to a particular TFT backplane configuration, it should be understood that any TFT backplane design in which a CNT layer may be substituted for a silicon layer may be implemented according to embodiments, including, for example, coplanar TFTs, short channel TFTs, staggered TFTs, planar TFTs, and self-aligned TFTs.

While many processes may be used to form such CNF TFTs, including certain bottom gate etch stop CNT TFTs, many such embodiments use processes as outlined in fig. 3 a-3 k and described below. As shown, the method requires multiple process steps into which the CNT layer is integrated. The steps include:

prepare the substrate and form a patterned gate electrode on top of the substrate (fig. 3 a).

A gate electrode dielectric is deposited on top of the gate electrode layer (fig. 3 b).

Deposit CNT thin film backside layer on top of dielectric layer (fig. 3 c).

Deposit CNT protective layer on top of CNT thin film backside layer (fig. 3 d).

Patterning the CNT protective layer to expose portions of the CNT backside layer over the gate electrode, leaving at least the edges of the CNT film covered by the CNT protective layer (fig. 3 e).

Depositing an etch stop dielectric layer on top of the exposed portion of the CNT thin film and the remaining CNT protective layer (fig. 3 f).

Patterning and etching the etch stop dielectric layer to selectively deposit a second dielectric layer atop the portion of the CNT thin film above the gate electrode (fig. 3 g).

Remove the remaining CNT protection layer to expose the CNT thin film on the edges of the gate electrode channel (fig. 3 h).

Depositing an n+ doped layer on top of the CNT thin film and etch stop dielectric layer (fig. 3 i).

Depositing a drain/source electrode layer on top of the n+ doped layer (fig. 3 j).

Patterning and etching of drain/source electrodes (fig. 3 k).

Such an Etch Stop (ES) CNT TFT process requires some additional deposition steps, but may be advantageous in some aspects because it has an etch stop layer that protects the backside channel, so the intrinsic layer may remain thin (e.g., less than about 200 nm). Although described above, it should be appreciated that the CNT backside channel layer may also be combined with other structures and techniques including, for example, backside Channel Etch (BCE) TFTs. An exemplary process of such a BCE TFT is provided in fig. 4a to 4f and described below. The steps include:

prepare the substrate and form a patterned gate electrode on top of the substrate (fig. 4 a).

A gate electrode dielectric is deposited on top of the gate electrode layer (fig. 4 b).

Both the drain/source electrode and the n+ doped layer are deposited on top of the dielectric layer (fig. 4 c).

Patterning and etching of the drain/source electrode and the n+ layer (fig. 4 d).

Deposit CNT thin film backside layer on top of n+ layer (fig. 4 e).

A passivation layer is deposited on top of the CNT thin film backside layer (fig. 4 f).

While the above-described methods are described in fig. 3 and 4 with respect to a particular deposition technique, it should be understood that many alternative embodiments and techniques may be used in conjunction with CNT backside layers according to embodiments.

For example, in some such embodiments, as shown in fig. 3a and 4a, a substrate having a gate electrode formed thereon is provided. Although the substrates in the figures are listed as being glass, it should be understood that any material that has sufficient optical transmission (e.g., about 80% or greater in many embodiments) and is resistant to degradation at industry standard processing temperatures (e.g., 100 ℃ and higher) may be used. Exemplary substrate materials may include glass, polyethylene terephthalate (PET), polyethersulfone (PES), polyacrylate (PAR), and Polycarbonate (PA), among others. Similarly, the gate electrode itself may be made of any suitable metal, such as Cu, al, ag, mo, cr, nd, ni, mn, ti, ta or W, or an alloy of two or more of these metals. The gate metal layer may be a single-layer structure or a multi-layer structure, and the multi-layer structure may be, for example, cu\mo, ti\cu\ti, mo\al\mo, or the like. As shown in fig. 3a and 4a, the thickness of the gate electrode may be any suitable size, such as from 10nm to greater than 100 μm, and in some embodiments is about 400nm.

Likewise, while the process for depositing the gate electrode is listed as including sputtering and patterning steps, it should be understood that many suitable and standard industrial processes may be used to pattern and deposit the gate electrode atop the substrate. Sputtering (or physical vapor deposition) may include, among other things, one or a combination of electron, potential, etching, and chemical sputtering, for example. Deposition techniques may alternatively include, for example, chemical (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), thermal evaporation, and/or the like.

Similarly, the patterning of the underlying gate electrode may comprise any suitable photolithography process, such as wet etching or dry etching, including the use of any suitable photoresist and etch chemistry. In many such embodiments, the gate electrode layer may be coated with a suitable photoresist layer, and the photoresist may then be exposed and developed through a mask plate to form photoresist unreserved regions and photoresist reserved regions, respectively. In many such embodiments, the photoresist-reserved areas correspond to areas where gate electrodes are arranged, and the photoresist-unreserved areas correspond to other areas. In such embodiments, the gate metal layer of the photoresist unreserved region may be completely etched away by an etching process and the remaining photoresist is removed, thereby forming a gate electrode.

Once the gate electrode is formed, a suitable dielectric layer is formed atop the substrate and gate electrode layer, as shown in fig. 3b and 4 b. Furthermore, while a PECVD process and a SiN dielectric material are specified in the figures, it should be appreciated that any suitable dielectric material and deposition process may be combined with the method. For example, in many embodiments, the dielectric layer may be made of inorganic and organic materials, oxides, nitrides, or oxynitrides, such as SiNx, siOx, taOx, alOx or Si (ON) x, for example. Also, the dielectric layer may be a single layer structure, a double layer structure, or a multilayer structure. The thickness of such a structure may take any size suitable for providing a dielectric function. In addition, the dielectric layer may be formed atop the substrate and gate electrode by any suitable film forming process including, for example, magnetron sputtering, thermal evaporation, CVD (remote plasma, photo-catalytic, etc.), PECVD, spin-coating, liquid phase growth, etc. In various such embodiments, as shown in fig. 3b and 4b, the CNT TFT comprises a SiNx/SiO ₂ layer deposited via PECVD to a thickness of about 200 nm. Finally, if desired, various source gas molecules can be fabricated in combination with such dielectric materials (including SiHx, NHx, N ₂ and hydrogen radicals and ions). Similar techniques and materials may be used for other passivation layers, including those etch stop layers formed in fig. 3f and passivation layers shown in fig. 4 f. In these steps, the deposition temperature and thickness of the passivation material may be selected as desired.

Regardless of whether the TFTs are ES TFTs or BEC TFTs, all TFTs also require the deposition of n+ and drain/source layers, as shown in FIGS. 3i and 3j and FIG. 4 c. While a sputter deposition of a Mo drain/source layer of about 400nm is illustrated and a PECVD deposition of a thin (about 10 nm) n+ doped layer, it should be appreciated that any suitable combination of deposition techniques and materials may be utilized. For example, the drain/source electrode layer may be made of any suitable metal, such as Cu, al, ag, mo, cr, nd, ni, mn, ti, ta or W, or an alloy of two or more of these metals. The gate metal layer may be a single-layer structure or a multi-layer structure, and the multi-layer structure may be, for example, cu\mo, ti\cu\ti, mo\al\mo, or the like. As shown in the figures, the thickness of the gate electrode may similarly be any suitable dimension, such as from 10nm to greater than 100 μm, and in some embodiments about 400nm. Likewise, while the process for depositing the electrode is listed as including sputtering and patterning steps, it should be understood that many suitable and standard industrial processes may be used to pattern and deposit the gate electrode atop the substrate. Sputtering (or physical vapor deposition) may include, among other things, one or a combination of electron, potential, etching, and chemical sputtering, for example. Deposition techniques may alternatively include, for example, chemical (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), thermal evaporation, and/or the like.

Similarly, any suitable n+ material may be incorporated into the TFT, including, for example, n+ doped amorphous Si or other suitable semiconductors (including gallium arsenides and phosphides and cadmium telluride and sulfides), according to embodiments. Likewise, suitable plasma and/or n-type doping materials may be used with such semiconductors, including, for example, phosphorus, arsenic, antimony, bismuth, lithium, beryllium, zinc, chromium, germanium, magnesium, tin, lithium, and sodium. Also, as described above, any suitable deposition technique (including thermal, physical, plasma, and chemical vapor deposition techniques) may be utilized to deposit these materials. Some suitable techniques include, for example, aerosol assisted CVD, direct liquid injection CVD, microwave plasma assisted CVD, atomic layer CVD, combustion chemical vapor deposition, hot filament CVD, hybrid physical chemical vapor deposition, rapid thermal CVD, vapor phase epitaxy, and photo-induced CVD. Alternatively, atomic layer deposition may replace CVD for thinner and more accurate layers.

Many of these processes also require patterning and etching of materials (see, e.g., 3e, 3h, 3k, and 4 d). In such a process, any suitable patterning and etching techniques may be incorporated with the embodiments. In particular, many steps include a patterning process by which a passivation layer is deposited and patterned through the passivation layer. In particular, in many embodiments, the passivation layer may be coated with any suitable photoresist layer. In such embodiments, the photoresist may be exposed and developed through a mask plate to form photoresist unreserved regions and photoresist reserved regions, respectively. For example, in various embodiments, the photoresist of the unreserved region may correspond to a region of the via hole where the passivation layer is disposed.

Any suitable optical lithography technique may be used including, for example, immersion lithography, bi-tone resist and multiple patterned electron beam lithography, X-ray lithography, extreme ultraviolet lithography, ion projection lithography, extreme ultraviolet lithography, nanoimprint lithography, immersion nanolithography, chemical lithography, soft lithography, and magnetic lithography, among others.

Regardless of the particular technique and light source used, such lithographic techniques typically involve several steps. In many embodiments, the layer to be patterned is first coated with a photoresist, such as by spin coating. In such techniques, a viscous liquid solution of photoresist is dispensed onto the wafer and the wafer is rapidly rotated to produce a uniformly thick layer. Spin coating is typically run at 1200 to 4800rpm for 30 to 60 seconds and produces a layer 0.5 to 2.5 microns thick. Spin coating processes produce a uniform thin layer, typically with a uniformity of 5 to 10 nanometers or more. In various embodiments, the photoresist-coated material may then be pre-baked (typically at 90 to 100 ℃ for 30 to 60 seconds on a hot plate) to drive off excess photoresist solvent. After etching the unmasked portions of the layer by a liquid ("wet") or plasma ("dry") chemistry, the uppermost layer of the substrate in the areas not protected by the photoresist is removed. After the photoresist is no longer needed, the photoresist is then removed from the substrate. The photoresist may be removed chemically or by plasma or by heating.

Although specific deposition and patterning methods are disclosed, as well as specific materials for substrates, electrodes, dielectrics, passivation layers, etc., and specific conditions including thickness, temperature, etc., it should be understood that any of these parameters may be adjusted as desired for specific TFT configurations and operating parameters without fundamentally altering the principles of embodiments incorporating CNTs as disclosed herein.

SWCNT deposition technique

Turning to embodiments of methods for depositing CNT layers in TFTs, in many embodiments, various techniques including various deposition and spray methods may be used.

In many embodiments, the single-walled carbon nanotube film is solution coated using a spray technique such as air, aerosol, or ultrasonic spray in conjunction with a mobile station fabrication line, as described with respect to fig. 5 a-5 c. As shown in fig. 5a, in many embodiments, a mobile station is provided on which the substrate is loaded, and the carbon nanotube solution may be sprayed (e.g., by aerosol or air spraying) onto a substrate of a suitable size (e.g., 4 "-100") while heating the mobile station and the carbon nanotube solution at a desired process temperature (e.g., from 60-200 ℃, or any temperature allowed by the underlying material and CNT material itself). In such embodiments, the speed of movement of the stage may be controlled to maintain film thickness and uniformity (e.g., 1mm/s-1000 mm/s).

In other embodiments, ultrasonic spraying may be used. In such an embodiment, as shown in fig. 5b, the compressed air stream passes through an aspirator that causes a localized reduction in air pressure to allow the carbon nanotube solution to be withdrawn from the container at normal atmospheric pressure. During processing, the ultrasonic nozzle atomizes the carbon nanotube solution into very small droplets, for example, from a few μm to about 1000 μm in diameter. The tiny droplets are then deposited onto the substrate at a suitable processing temperature (e.g., up to 400 ℃) such that the droplets immediately dry to mitigate O-ring polymerization. In various embodiments, a temperature of 100 ℃ may be used. While any suitable air pressure may be used (depending on the viscosity of the material), in many embodiments, the compressed air pressure may be in the range of 20psi (1.38 bar) to 100psi (6.8 bar), depending on the solution viscosity and the size of aspirator required for deposition.

In embodiments incorporating aerosol spraying (as shown in fig. 5 c), the carbon nanotube solution may be atomized using high pressure gas (e.g., 200-1000 standard cubic centimeters per minute (sccm)) or ultrasonic treatment (e.g., 20V-48V,10-100 watts) to produce aerosols of 1-5 microns, which are carried to the spray head by a carrier gas (e.g., 10sccm-30 sccm). It should be understood that these processing parameters are merely exemplary and that other deposition properties may be used depending on the type of material, the desired aerosol properties, and the thickness of the coating to be formed.

Fig. 6 and 7 show images of thin films of SWCNTs sprayed onto a substrate using a spray gun technique (fig. 6) and using an aerosol technique (fig. 7), according to an embodiment. In many embodiments, the carbon nanotube film thus formed is treated with acetic acid gas generated by spray gun spraying or aerosol spraying, and then washed with isopropyl alcohol to obtain a clean carbon nanotube surface. The clean carbon nanotube surface was characterized using Atomic Force Microscopy (AFM). Because of the high insulation of glass substrates, these samples cannot be characterized using scanning electron microscopy on such substrates. As shown, fig. 8 provides an AFM image of a spray gun sprayed SWCNT film, and fig. 9 provides an AFM image of an aerosol sprayed SWCNT film. This image provides proof of the robust nature of the deposition process, as well as the ability to deposit high quality thin film coatings of SWCNTs.

In an embodiment, as described above with respect to fig. 3 and 4, a carbon nanotube film formed according to such a spray coating process is used to replace amorphous silicon in a 4-photomask lithography process to pattern drain/source electrodes, dielectrics, top gate electrodes, and pixel electrodes according to industry standard methods of manufacture.

While the embodiments shown in fig. 3 and 4 are shown as extending beyond the channel in order to reduce subthreshold current leakage, other embodiments may employ at least one additional photomask to pattern the active carbon nanotube thin layer using photolithography. In such embodiments, the CNT layer outside the transistor channel may be removed by a suitable etching technique such as, for example, O ₂ plasma or wet etching. In various such embodiments, the clean, uniform carbon nanotube film may be coated with a Photoresist (PR) and exposed to light and then developed with a solution. On these developed areas, the carbon nanotube film is etched using, for example, an O ₂ plasma or wet chemical etch (such as buffered HF solution). The undeveloped PR is then stripped to leave the patterned carbon nanotube film. A flowchart providing one embodiment of such a method is provided in fig. 10. It should be understood that any of the steps and techniques listed in the flowcharts may be replaced with alternative options as described in detail above.

In still other embodiments, to reduce the use of additional photomasks to pattern the active carbon nanotubes and reduce the consumption of carbon nanotube solution, SWCNT films may be printed atop the substrate. In many such embodiments, an aerosol jet printer may be used to print active carbon nanotube films using small nozzle sizes (e.g., < 100 μm). The aerosol jet printer can deposit line widths of <10 μm with an alignment accuracy of <2 μm. To this end, an aerosol jet printer prints carbon nanotubes on the patterned drain/source marks. An image of such an aerosol printing device is provided in fig. 11. Fig. 12 shows photographs and optical images of exemplary drain/source marks prior to printing SWCNT films. Fig. 13 provides photographic and optical images of SWCNT films printed on drain/source marks. As described above, the aerosol spray-printed carbon nanotubes may be treated with an aerosol spray or gun spray of acetic acid gas and then washed with isopropyl alcohol. These clean carbon nanotube films can then be characterized using SEM. According to an embodiment, SEM images (fig. 14) show clean carbon nanotube films on drain/source labels. As shown in fig. 15 a-15 c, clean carbon nanotube films have been characterized by the Keithly 4200 semiconductor characterization system to show semiconductor properties.

In order to further take advantage of low cost, low environmental impact, and large area manufacturing due to the small number of process steps, limited material volume, and high manufacturing volume, embodiments propose the above-described aerosol jet printing method (including its high accuracy: 1 μm-2 μm alignment accuracy) with a high speed processing roll-to-roll system. With such a roll-to-roll aerosol jet printer, SWCNT ink can be printed in a rapid manner for mass production in an a-Si TFT backplane manufacturing line. In addition, full-printed SWCNT TFT backplanes can be fabricated in large quantities using a roll-to-roll system. To match the industrial speed, embodiments disclose a plurality of aerosol jet printer heads mounted on a mobile station, such as shown in fig. 16, which can be used to print carbon nanotube films at high speeds. Such multiple aerosol jet printer heads can print a large number of carbon nanotube patterns on a mobile station.

Exemplary embodiments of the invention

Additional embodiments and features are set forth in part in the exemplary embodiments which follow and in part will become apparent to those having ordinary skill in the art upon examination of the specification or may be learned from practice of the invention. The specific embodiments are not intended to limit the scope of the remainder of the specification and drawings, and they are provided as examples of the apparatus, methods, and materials disclosed herein. In particular, although specific constructions and specific combinations of materials are enumerated, it should be understood that these are provided as examples only and that any suitable alternative architecture and materials may be substituted.

Example 1: comparison of conventional a-Si TFT and CNT TFT technologies

A flowchart of an exemplary method for fabricating an amorphous silicon TFT backplane on a manufacturing line is provided in fig. 17. As shown in this method, amorphous silicon is deposited over a large area by plasma enhanced chemical vapor deposition and then other devices are fabricated according to other conventional fabrication steps. In an embodiment, CNT may be substituted for amorphous silicon. Such CNT films may be deposited and/or printed according to the techniques described previously. With such clean carbon nanotube films according to embodiments, the drain/source electrodes, dielectrics, top gate electrodes, and pixel electrodes may be further patterned using standard industry fabrication methods, as described in fig. 18 and/or 19.

Example 3: SWCNT TFT

Using the techniques described above, single-walled carbon nanotube thin film transistors can be formed, for example, as shown in fig. 20.

Example 2: display device

Finally, while the above exemplary embodiments and discussion focus on methods, architectures, and structures for separate devices and backplanes, it will be appreciated that the same architectures and structures may be combined as pixels into a display device. In such embodiments, multiple SWCNT TFTs as described herein may be combined and interconnected, such as by electrically coupling the device into addressing electrode lines to form TFT backplanes for displays such as AMOLED displays, as known to those skilled in the art.

Principle of equivalence

Having described several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. In addition, many well known processes and principles have not been described in order to avoid unnecessarily obscuring the present invention. Accordingly, the above description should not be taken as limiting the scope of the invention.

Those skilled in the art will appreciate that the presently disclosed embodiments are taught by way of example and not limitation. Accordingly, what has been included in the foregoing description or shown in the accompanying drawings is to be understood as illustrative and not in a limiting sense. The following claims are intended to cover all of the generic and specific features described herein, and all statements of the scope of the present method and system, which, as a matter of language, might be said to fall therebetween.

Claims

1. A method for fabricating a single-walled carbon nanotube thin film transistor backplane, comprising:

providing a substrate;

Patterning a gate electrode on a substrate to form a channel;

depositing a dielectric layer over the gate electrode;

depositing a backing layer comprising a thin film layer of single-walled carbon nanotubes on the dielectric layer, wherein the backing layer is deposited by a spray technique selected from the group consisting of aerosol spray, air spray, and ultrasonic spray;

depositing an n+ doped layer on the back layer;

depositing drain and source electrode layers on the n+ doped layer; and

At least the n+ doped layer and the drain and source layer electrodes on the back layer are patterned using a photomask and a photolithographic process such that portions of the back layer overlapping the channel are exposed, wherein the back layer completely overlaps the n+ doped layer and the drain and source electrodes.

2. The method of claim 1, wherein the single-walled carbon nanotube aerosol is formed from an aqueous solution of single-walled carbon nanotubes that are sonicated in an ultrasonic nozzle and emitted at a carrier gas flow rate.

3. The method of claim 1, wherein the backing layer is printed atop the substrate using aerosol jet printing as a single-walled carbon nanotube aerosol.

4. A method according to claim 3, wherein the single-walled carbon nanotube aerosol is formed by a technique selected from ultrasonic atomization and pneumatic atomization.

5. The method of claim 4, wherein the deposited line width is less than 10 μm with an alignment accuracy of <2 μm.

6. The method of claim 4, wherein the aerosol is carried to the spray head by a carrier gas flow of 10 to 20 cubic centimeters per minute.

7. The method of claim 1, wherein the single-walled carbon nanotubes are high purity single-chiral single-walled carbon nanotubes.

8. The method of claim 7, wherein the single-walled carbon nanotubes have an index selected from the group consisting of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2), and mixtures thereof.

9. The method of claim 1 wherein the single-walled carbon nanotube film is formed from a plurality of discrete films.

10. The method of claim 1, further comprising depositing and patterning an etch stop layer atop the back layer such that the etch stop overlaps the channel.

11. The method of claim 1, further comprising treating the single-walled carbon nanotube film with an acid gas.

12. The method of claim 11, wherein the acid gas is deposited via aerosol spray.

13. The method of claim 11, further comprising cleaning the treated single-walled carbon nanotube film.

14. The method of claim 13, further comprising sintering the single-walled carbon nanotube film at a temperature of 100 ℃ to 200 ℃.

15. The method of claim 1, wherein forming a thin film having a subthreshold leakage current comprises:

spin-coating a photoresist on the single-walled carbon nanotube film;

Defining a pattern atop the photoresist by photolithography to create defined photoresist and undefined regions of photoresist;

solution developing the defined pattern to form a developed photoresist; and

16. A method for fabricating a single-walled carbon nanotube thin film transistor backplane, comprising:

providing a substrate;

patterning the gate electrode and the dielectric layer on the substrate to form a channel;

Depositing drain electrode layers and source electrode layers on the dielectric layer;

Depositing an n+ doped layer on the drain and source electrode layers;

Patterning at least the n+ doped layer and the drain and source electrode layers on the dielectric layer using a photomask and a photolithography process such that portions of the dielectric overlapping the channel are exposed;

depositing a back layer comprising a thin film layer of single-walled carbon nanotubes on the n+ doped layer, the drain and source electrode layers, and the dielectric layer, wherein the back layer completely overlaps the n+ doped layer and the drain and source electrodes; and

A passivation layer is deposited on the back layer.

17. The method of claim 16, wherein the backing layer is deposited by a spray technique selected from the group consisting of aerosol spray, air spray, and ultrasonic spray.

18. The method of claim 16, wherein the backing layer is printed atop the substrate using aerosol jet printing as a single-walled carbon nanotube aerosol.

19. The method of claim 16 wherein the single-walled carbon nanotubes are high purity single-chiral single-walled carbon nanotubes.

20. The method of claim 19, wherein the single-walled carbon nanotubes have an index selected from the group consisting of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2), and mixtures thereof.

21. The method of claim 1 or 16, further comprising integrating the single-walled carbon nanotube thin film transistor backplane into a display device.