KR20220025950A - Manufacturing of carbon nanotube thin film transistor backplanes and display integration thereof - Google Patents

Abstract

Methods for producing and integrating single-walled carbon nanotubes (SWCNTs) into an existing TFT backplane manufacturing line are provided. Unlike LTPS and oxide TFT backplanes, SWCNT TFT backplanes have the same or equal or higher field emission mobility, low temperature fabrication, good stability, uniformity, scalability, flexibility, transparency, mechanical deformability, low voltage and low power, bendability, and low cost. It exhibits better figures of merit. Methods and processes are also provided for integrating SWCNTs technologies into existing TFT backplane manufacturing lines, pilot testing, and mass production, which can start without additional capital investment requirements.

Description

Manufacturing of carbon nanotube thin film transistor backplane and display integration

A method for manufacturing a carbon nanotube thin film transistor backplane and their integration into a display.

Flat panel displays (FPDs) have entered consumer electronics integrated with display functions. Among the existing FPDs, thin film transistor (TFT)-liquid crystal displays (LCDs) dominate the current display market with a market share of 97.5% in 2013, although there are certain limitations on color, contrast, and response time. More recently, display capital expenditures (CAPEX) have increased in TFT-LCDs as large AMOLEDs have a cost advantage over TFT-LCDs in 8G+ manufacturing, as well as display quality of superior color, contrast, and response time. There has been a rapid shift towards AMOLEDs. To be able to fabricate AMOLEDs larger than the 8th generation size, there are several technical challenges, including limitations of conventional active matrix thin film transistor (TFT) backplanes (e.g., G. Gu and SR Forrest, IEEE Journal of Quantum Electronics). of Selected Topics, Vol. 4, pp. 83-99, 1998, the disclosure of which is incorporated herein by reference).

Current active matrix TFT backplanes used to drive AM-LCD pixels are generally made of amorphous silicon (a-Si), have low mobility (-1 cm ² V ^-1 s ^-1 ) and poor stability, so AMOLED Not suitable for pixels (see MJ Powell, IEEE Transactions on Electron Devices, Vol. 36, pp. 2753-2763, 1989, the disclosure of which is incorporated herein by reference). As a result of these deficiencies, current AMOELD displays are driven by low-temperature poly-Si TFTs, which have high manufacturing cost and time, device size, orientation, and non-uniformity limitations, all of which display size and serious challenges in increasing production yield (e.g., CP Chang and YCS Wu, IEEE electron device letters, vol. 30, pp. 130-132, 2009; YJ Park, MH Jung, SH Park and O. Kim). , Japanese Journal of Applied Physics, Vol. 49, pp. 03CD01, 2010 and PS Lin and TS Li, IEEE electron device letters, vol.15, pp. 138-139, 1994, the disclosures of each of these incorporated herein by reference).

Although low-temperature polycrystalline silicon (LTPS) backplanes have been mass-produced up to the 5.5th generation, LTPS fabrication techniques, including excimer laser annealing (ELA) and advanced solid-phase crystallization (ASPC), create significant obstacles to scale-up beyond Gen 8 generation. For example, ELA and ASPC fabs have very slow total average cycle times, more than double that of 60 seconds for a-Si. This doubles the capital cost of the array process of a-Si. Additionally, scaling up of ELA can introduce non-uniformity and array errors. The high temperatures of the ASPC process (up to 600 degrees Celsius) require expensive glass to avoid glass warping and shrinkage (B. Young, Information Display, vol.10, pp.24, 2010, the disclosure of which is incorporated herein by reference). included as). The higher process temperatures and more complex photomasks required to fabricate LTPS increase capital investment and difficulty in achieving high yields. Because of this, a 5-inch 0LTPS TFT-LCD (1920 Х 1080 pixels) is 14% more expensive than an a-Si TFT-LCD of the same size.

Accordingly, there is a need for fabrication techniques that enable the fabrication of cheaper TFT backplanes.

Methods for manufacturing carbon nanotube thin film transistor backplanes and their integration into displays are provided.

Many embodiments relate to methods of manufacturing a single-walled carbon nanotube thin film transistor backplane,

providing a substrate;

stacking an insulator composed of a thin film layer of single-walled carbon nanotubes on a substrate; And

and patterning at least one drain and source electrode, a dielectric, one or more top gated electrodes, and one or more pixel electrodes over the insulator using a photomask and a photolithography process.

In other embodiments, the insulator is deposited by a spray technique selected from the group consisting of aerosol spray, air spray and ultrasonic spray.

In some such embodiments, the single-walled carbon nanotube aerosol is about 1 to 5 μm in diameter by ultrasonic atomization at a voltage in the range of 20 to 48 V, and pneumatic atomization with an atomizer flow of about 600 cm ² /min. is formed by ^a technology that generates an aerosol in

In still other such embodiments, a single-walled carbon nanotube aerosol is formed from an aqueous solution of single-walled carbon nanotubes that is sonicated in an ultrasonic nozzle and discharged with a carrier gas flow of about 10-20 cm ² /min.

In still other embodiments, the insulator is printed onto the substrate using aerosol jet printing as a single-walled carbon nanotube aerosol.

In some such embodiments, the single-walled carbon nanotube aerosol is formed by a technique selected from ultrasonic atomization at a voltage in the range of 20 to 48 V, and pneumatic atomization with a nebulizer flow of less than 600 cm ² /min, thereby generating the aerosol by 1 to 5 μm in diameter, the aerosol is made into a fine nozzle of less than 100 μm by a carrier gas flow of 10 to 20 cm ² /min, and is concentrated with a sheath gas flow of 25 to 50 ccm .

In other such embodiments, the stacked linewidth is less than 10 μm with a registration accuracy of less than 2 μm.

In still other embodiments, the single-walled carbon nanotubes are high-purity single chirality single-walled carbon nanotubes.

In some such embodiments, single-walled carbon nanotubes are (6,4), (9,1), (8,3), (6,5), (7,3), (7,5), ( 10,2), (8,4), (7,6), (9,2), and mixtures thereof.

In still other embodiments, the single-walled carbon nanotube thin film is formed of a plurality of individual thin films.

In some such embodiments, individual single-walled carbon nanotube thin films are patterned using a single photomask photolithography process.

In still other embodiments, the method further comprises treating the single-walled carbon nanotube thin film with an acid gas.

In some such embodiments, the acid gas is deposited via aerosol spray.

In still other such embodiments, the method further comprises washing the treated single-walled carbon nanotube thin film with isopropanol.

In still other such embodiments, the method further comprises sintering the single-walled carbon nanotube thin film at a temperature of about 100 to 200 °C.

In still other embodiments, the thin films are formed with a subthreshold leakage current,

spin coating a photoresist on a single-walled carbon nanotube thin film;

defining a pattern over the photoresist by photolithography to create regions of defined photoresist and undefined photoresist;

solution developing the defined pattern to form a developed photoresist; And

Plasma or wet etching the single-walled carbon nanotube thin film using a developed photoresist to form a patterned single-walled carbon nanotube thin film.

In still other embodiments, the method includes integrating a single-walled carbon nanotube thin film transistor backplane into a display device.

Various other embodiments relate to a system configured to stack single-walled carbon nanotube thin film transistor backplanes,

a plurality of print heads mounted in association with a moving station;

a plurality of printer heads in fluid communication with a solution of an aqueous solution of single-walled carbon nanotubes to deposit a thin film of single-walled carbon nanotubes on a substrate positioned on the mobile station; And

The printer heads are integrated into a photomask and photolithography process for patterning and forming at least one drain and source electrode, dielectric, one or more top gated electrodes, and one or more pixel electrodes over the laminated thin film.

Additional embodiments and features are set forth in part in the description that follows, and will become apparent to those skilled in the art upon review of the specification or may be learned by practice of the invention. A further understanding of the nature and advantages of the present invention may be realized by reference to the remainder of the specification and drawings, which form the remainder of this specification.

The description will be more fully understood with reference to the following drawings and data graphs, which are presented as exemplary embodiments of the invention and should not be construed as fully reciting the scope of the invention.
1 provides a data graph showing an absorption spectrum of single-walled carbon nanotubes according to embodiments of the present invention.
2A and 2B provide schematic diagrams of exemplary vertical light emitting transistors in accordance with embodiments of the present invention.
3A-3K provide schematic diagrams of a method of forming etch-stop vertical light emitting transistors in accordance with embodiments.
4A-4F provide schematic diagrams of methods of forming a vertical light emitting transistor in accordance with embodiments.
Figures 5a-5c according to respective embodiments of the present invention. It provides schematic illustrations showing a) a plurality of spray heads for solution spraying devices at mobile stations, b) an airbrush for ultrasonic spraying, and c) an aerosol spray system.
6 provides an image of a carbon nanotube thin film sprayed with an airbrush according to embodiments of the present invention.
7 provides an image of an aerosol atomized carbon nanotube thin film according to embodiments of the present invention.
8 is an atomic force microscope (AFM) image of an airbrush sprayed single-walled carbon nanotube thin film according to embodiments of the present invention.
9 is an atomic force microscope (AFM) image of the aerosol sprayed single-walled carbon nanotube thin film according to embodiments of the present invention.
10 provides a flowchart illustrating a manufacturing process for manufacturing a top gate type carbon nanotube TFT backplane according to embodiments of the present invention.
11 provides an image of an aerosol printer for printing a carbon nanotube pattern on drain/source marks according to embodiments of the present invention.
12 provides photographic and optical images of drain/source marks prior to aerosol printing of single-walled carbon nanotube patterned films in accordance with embodiments of the present invention.
13 provides photographic and optical images of single-walled carbon nanotube patterned films aerosol printed on drain/source marks in accordance with embodiments of the present invention.
14 provides an optical image of aerosol jet printed carbon nanotube films according to embodiments of the present invention, and the inset is an SEM image.
15 provides an optical image of aerosol jet printed carbon nanotube films on photolithographic patterned electrodes, inset IV of such carbon nanotube films exhibiting pure semiconducting properties, in accordance with embodiments of the present invention. It is a curve.
16 provides a photographic image of a device having multiple aerosol jet printer heads mounted in a roll-to-roll station in accordance with embodiments of the present invention.
17 provides a flow chart showing a manufacturing process for manufacturing a standard bottom gate type a-Si TFT backplane according to the prior art.
18 provides a flowchart illustrating a manufacturing process for manufacturing top-gate type carbon nanotube TFT backplanes according to embodiments of the present invention.
19 provides a flowchart illustrating a manufacturing process for manufacturing top gate type printed carbon nanotube TFT backplanes according to embodiments of the present invention.
20 provides a cross-sectional view of a single-walled carbon nanotube thin film transistor according to embodiments of the present invention.

Referring to the drawings, there are devices, materials, and methods for producing and integrating single-walled carbon nanotubes (SWCNTs) into an existing TFT backplane manufacturing line. In particular, unlike LTPS and oxide TFT backplanes, SWCNT TFT backplanes have high field emission mobility, low temperature fabrication, excellent stability, uniformity, scalability, flexibility, transparency, mechanical deformability, low voltage and low power, bendability, and low cost. same or better figures of merit. Accordingly, many embodiments relate to methods and processes for integrating SWCNTs technologies into existing TFT backplane manufacturing lines, pilot testing, and mass production, which can be started without additional capital investment requirements. Moreover, other embodiments relate to methods and processes for incorporating such SWCNT TFT backplanes into a video display, in various embodiments high-end autostereoscopic 3-D and UD (such as Helmet-Mounted Display) (HMD) ultra-definition) panel displays. In the following text, carbon nanotubes are (6,4), (9,1), (8,3), (6,5), (7,3), (7,5), (10,2), Refers to single-walled carbon nanotubes containing high-purity single chiral SWCNTs, such as SWCNTs having indices of (8,4), (7,6), (9,2), and mixtures thereof.

Active matrix organic light emitting displays (AMOLEDs) are very attractive because of their power saving, ultra-high definition (UHD), and wide viewing angles. In particular, advances in organic light emitting transistors (OLETs) represent improved external efficiency compared to organic light emitting diodes (OLEDs) by directly modulating the charge carriers of the light emitting materials. In addition, inducing vertical structure in OLETs avoids the inherent low mobility of organic materials by providing a short channel length, thus achieving high conductivity at low power and low voltage, thus improving energy conversion efficiency, lifetime, and The stability of organic substances is improved. In addition, combining thin film transistor (TFT) switching and OLED light emitting characteristics into a single device simplifies the manufacturing process and reduces costs. However, the technical challenges in forming basic TFT backplanes in these devices limit display size change and cost savings. As described below, the use of novel SWCNT materials, and fabrication combinations such as highly transparent porous conductive SWCNT electrodes, overcomes the limitations of display backplanes made of amorphous/crystalline/polysilicon, metal oxide, and organic materials for TFT It enables the formation of SWCNT TFTs that can be included in manufacturing lines of backplanes, and will suit a variety of needs.

Accordingly, various embodiments relate to methods of integrating printed SWCNT technologies into an a-Si TFT-LCD manufacturing line. Using these SWCNT backplanes enables LTPS TFT backplanes to have high pixel density, low power consumption, and integration with driver circuits on a glass substrate.

SWCNT selection/purification techniques

With the advent of separation technology, ultrapure single-walled carbon nanotubes with a purity greater than 95% can be produced and scaled up for mass manipulation. Using these processes, high purity single chiral SWCNTs with a wide range of indices can be produced. In many embodiments, high purity single chiral SWCNTs and (6,4), (9,1), (8,3), (6,5), (7,3), (7,5), (10 Mixtures comprising SWCNTs with indices of ,2), (8,4), (7,6), (9,2) are formed. (6,5) The NIR-Vis absorption spectrum of SWCNTs is presented in Fig. 1, showing predominant S11 and S22 peaks at 978 nm and 562 nm. Their electrical properties are characterized as those of a pure semiconductor with negligible off current (I-V curves are provided as insets in FIG. 1 ). Accordingly, these techniques can be used to ensure the purity of these materials through conventional spectroscopy and to determine their electrical properties for selection.

TFT backplane manufacturing

Embodiments relate to methods and processes for using ultra-pure semiconductor single-walled carbon nanotubes to replace an amorphous silicon layer in industrial TFT backplane manufacturing lines. In particular, as shown in FIGS. 2A and 2B , the layers of CNTs according to embodiments are, among other things, bottom gated etch stop CNT TFTs (eg, FIG. 2A ) and bottom gated back-channel (back-channel). ) can be implemented in etched CNT TFTs (eg, FIG. 2B ). However, while methods and processes will be described with reference to specific TFT backplane configurations, any TFT backplane design in which a CNT layer may be substituted for a silicon layer, for example coplanar TFTs, short channel It will be appreciated that it may be implemented according to embodiments including -channeled TFTs, staggered TFTs, planar TFTs, and self-aligned TFTs.

Although many processes can be used to form such CNF TFTs, particularly including bottom gate etch stop CNT TFTs, many such embodiments use the process summarized in FIGS. 3A-3K and described below. As shown, this method requires multiple process steps in which the CNT layers are integrated. These steps include:

Provision of a substrate and formation of a patterned gate electrode over the substrate (FIG. 3A).

Lamination of the gate electrode dielectric over the gate electrode layer (FIG. 3B).

Lamination of the CNT thin film back layer over the dielectric layer (Fig. 3c).

Lamination of a CNT protective layer on the CNT thin film backside layer (Fig. 3d).

The CNT protective layer was patterned to expose a portion of the CNT back layer over the gate electrode, leaving at least the edges of the CNT thin film covered by the CNT protective layer (Fig. 3e).

Lamination of an etch stopper dielectric layer over the exposed portion of the CNT thin film and the remaining CNT protective layer (Fig. 3f).

An etch stopper dielectric layer was patterned and etched to selectively deposit a second dielectric layer over a portion of the CNT thin film over the gate electrode (FIG. 3G).

The remaining CNT protective layer was removed, exposing the CNT thin film on the edges of the gate electrode channel (Fig. 3h).

Lamination of an n+ doped layer over the CNT thin film and etch stop dielectric layer (Fig. 3i).

Lamination of the drain/source electrode layer over the n+ doped layer (FIG. 3J).

Patterning and etching of drain/source electrodes (FIG. 3K).

The process of such an etch stop (ES) CNT TFT requires several additional stacking steps, but in part because it has an etch stop layer that protects the back channel so that the intrinsic layer can be kept thin (e.g., less than 200 nm). It can be advantageous in aspects. Notwithstanding the foregoing, it will be appreciated that CNT back channel layers may also be combined with other structures and techniques including, for example, back channel etch (BCE) TFTs. An exemplary process for such a BCE TFT is provided in Figures 4A-4F, and is described below. These steps include:

Provision of a substrate and formation of a patterned gate electrode over the substrate (FIG. 4A).

Lamination of the gate electrode dielectric over the gate electrode layer (FIG. 4B).

Lamination of both the drain/source electrode and n+ doped layers over the dielectric layer (FIG. 4C).

Patterning and etching of drain/source electrodes and n+ layer (FIG. 4D).

Lamination of the CNT thin film backside layer on the N+ layer (Fig. 4e).

Lamination of a protective layer on the CNT thin film backing layer (Fig. 4f).

Although the above methods are described in FIGS. 3 and 4 with respect to specific deposition techniques, it should be understood that many alternative embodiments and techniques may be used in connection with CNT backlayers in accordance with embodiments. .

이상)에서 열화에 저항할 수 있는 임의의 재료가 사용될 수 있음이 이해되어야 한다. 예시적인 기판 재료는 다른 것들 중에서 유리, 폴리에틸렌테레프탈레이트(PET), 폴리에테르설폰(PES), 폴리아릴레이트(PAR), 그리고 폴리카보네이트(PA)를 포함할 수 있다. 유사하게, 게이트 전극 자체는 Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, 또는 W와 같은 임의의 적합한 금속, 또는 이러한 금속들 중 둘 이상의 합금으로 이루어질 수 있다. 게이트 금속층은 단일층 구조 또는 다층 구조일 수 있으며, 다층 구조는 예를 들어 Cu/Mo, Ti/Cu/Ti, Mo/Al/Mo 등일 수 있다. 도 3a 및 4a 에 도시된 것처럼, 게이트 전극의 두께는, 예를 들어 10 nm 부터 100 μm 이상까지, 일부 실시예들에서는 약 400 nm이 임의의 적합한 크기일 수 있다.For example, in some such embodiments, as shown in FIGS. 3A and 4A , a substrate having a gate electrode formed thereon is provided. Although the substrate is described as being glass in the figures, it has sufficient light transmission (eg, on the order of 80% or greater in many embodiments) and has industry standard process temperatures (eg, 100

It should be understood that any material capable of resisting degradation in (above) may be used. Exemplary substrate materials may include glass, polyethylene terephthalate (PET), polyethersulfone (PES), polyarylate (PAR), and polycarbonate (PA), among others. Similarly, the gate electrode itself may be made of any suitable metal, such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, or W, or an alloy of two or more of these metals. The gate metal layer may have a single-layer structure or a multi-layer structure, and the multi-layer structure may be, for example, Cu/Mo, Ti/Cu/Ti, Mo/Al/Mo, or the like. As shown in FIGS. 3A and 4A , the thickness of the gate electrode may be of any suitable size, for example, from 10 nm to 100 μm or more, and in some embodiments about 400 nm.

Likewise, although a process for depositing a gate electrode is listed as including sputtering and patterning steps, it should be understood that many suitable standard industrial processes may be used for patterning and depositing gate electrodes over a substrate. For example, sputtering (or physical vapor deposition) may include one or a combination of electron, potential, etching, and chemical sputtering, among others. The deposition techniques may alternatively include, for example, chemical (CVD), plasma enhanced vapor deposition (PECVD), and/or thermal evaporation, and the like.

Similarly, patterning of the bottom gate electrode may include any suitable photoengraving process, such as wet or dry etching, including the use of any suitable photoresist and etch chemistries. In many such embodiments, the gate electrode layer may be coated with a layer of a suitable photoresist, which may be exposed and developed by a mask plate to form non-photoresist and photoresist holding regions, respectively. In many such embodiments, the photoresist holding region corresponds to the region where the gate electrode is disposed, and the photoresist non-retaining region corresponds to other regions. In such embodiments, the gate metal layer of the non-photoresist region may be completely etched away by an etching process, and the remaining photoresist is removed to form a gate electrode.

Once the gate electrode is formed, a suitable dielectric layer is formed over the substrate and the gate electrode layer, as shown in Figures 3B and 4B. Also, although a PECVD process and a SiN dielectric material are specified in the figures, it should be understood that any suitable dielectric material and deposition process may be incorporated with the methods. For example, in many embodiments, the dielectric layer may be made of oxide, nitride, or nitrogen oxide, inorganic and organic materials such as, for example, SiNx, SiOx, TaOx, AlOx or Si(ON)x. Further, the dielectric layer may have a single-layer structure, a double-layer structure, or a multi-layer structure. The thickness of these structures can be of any size suitable to provide a dielectric function. Further, the dielectric layer can be formed over the substrate and gate electrode by any suitable filming process including, for example, magnetron sputtering, thermal evaporation, CVD (remote plasma, photocatalytic, etc.), PECVD, spin coating, and liquid phase growth, etc. can 3B and 4B, in various such embodiments, the CNT TFTs include SiNx/SiO ₂ layers deposited via PECVD to a thickness of about 200 nm. Finally, various feedstock gas molecules can be prepared with these dielectric materials including SiHx, NHx, N ₂ , and hydrogen free radicals and ions, if desired. Similar techniques and materials may be used for other passivation layers, including the etch-stop layers formed in FIG. 3F, and the passivation layer shown in FIG. 4F. In these steps, the deposition temperatures and thicknesses of the protective materials can be selected as needed.

Regardless of whether the TFT is an ES or BEC TFT, all TFTs also require lamination of n+ and drain/source layers as shown in Figs. 3i and 3j. Although the figures show sputter deposition of an approximately 400 nm Mo drain/source layer, and PECVD deposition of a thin (less than 10 nm) n+ doped layer, it should be understood that any suitable combination of deposition techniques and materials may be used. do. For example, the drain/source electrode layer may be made of any suitable metal, such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, or W, or an alloy of two or more of these metals. . The gate metal layer may have a single-layer structure or a multi-layer structure, and the multi-layer structure may be, for example, Cu/Mo, Ti/Cu/Ti, Mo/Al/Mo, or the like. The thickness of the gate electrode can likewise be of any suitable size, for example from 10 nm to 100 μm or more as shown in the figures, and in some embodiments about 400 nm. Likewise, although a process for depositing an electrode is listed as including sputtering and patterning steps, it should be understood that many suitable standard industrial processes may be used for patterning and depositing a gate electrode over a substrate. For example, sputtering (or physical vapor deposition) may include one or a combination of electron, potential, etching, and chemical sputtering. Deposition techniques may alternatively include, for example, chemical (CVD), plasma enhanced vapor deposition (PECVD), and/or thermal evaporation, and the like.

Similarly, any suitable n+ material may be incorporated into TFTs according to embodiments, for example n+ doped amorphous Si, or other including arsenic and phosphides of gallium, and telluride and sulfides of cadmium. suitable semiconductors. Likewise, suitable plasma and/or n-type doping materials may be used with semiconductors comprising, for example, phosphorus, arsenic, antimony, bismuth, lithium, beryllium, zinc, chromium, germanium, magnesium, tin, lithium, and sodium. can In addition, these materials may be deposited by any suitable deposition technique, including thermal, physical, plasma, and chemical vapor deposition techniques as described above. Some suitable techniques include, for example, aerosol assisted CVD, direct liquid injection CVD, microwave plasma assisted CVD, atomic layer CVD, combustion chemical vapor deposition, high temperature filament CVD, hybrid physical chemical vapor deposition, rapid thermal CVD, vapor phase epitaxy, and photovoltaic CVD. Including initiating CVD. Alternatively, atomic layer deposition can be replaced with CVD for thinner and more precise layers.

Multiple steps in these processes also require patterning and etching of materials (see, eg, 3e, 3h, 3k, and 4d). In these processes, any suitable patterning and etching technique may be incorporated with the embodiments. In particular, many of the steps include a patterning process in which a protective layer is deposited and a pattern is formed through the protective layer. Specifically, in many embodiments the protective layer may be coated with any suitable layer of photoresist. In such embodiments, the photoresist may be exposed and developed by a mask plate to form a photoresist non-retaining region and a photoresist retaining region, respectively. For example, the photoresist in the non-retained region may correspond to a region in which a via hole of the protective layer is disposed in various embodiments.

Any suitable optical photolithography technique may be, among others, for example, immersion lithography, dual-tone resist and multiple patterning electron beam lithography, X-ray lithography, extreme ultraviolet lithography, ion projection lithography, polar Ultraviolet lithography, nanoimprint lithography, dip-pen nanolithography, chemical lithography, soft lithography, magneto lithography, and the like may be used.

Regardless of the specific techniques and light source used, these lithographic techniques generally include several steps. In many embodiments, the layer to be patterned is first coated with a photoresist, for example by spin coating. In these techniques, a viscous, liquid solution of photoresist is dispensed onto a wafer, and the wafer is rotated rapidly to create a uniformly thick layer. Spin coating is typically operated at 1200 to 4800 rpm for 30 to 60 seconds and produces a layer 0.5 to 2.5 micrometers thick. The spin coating process generally produces a thin, uniform layer with a uniformity of 5 to 10 nanometers or better. In various embodiments, the photoresist-coated material may then be pre-baked on a hot plate at typically 90-100° C. for 30-60 seconds and to remove excess photoresist solvent. After being etched by a chemical agent, either liquid (“wet”) or plasma (“dry”), the top layer of the substrate is removed in areas where unmasked portions of the layer are not protected by the photoresist. When the photoresist is no longer needed, the photoresist is removed from the substrate. This photoresist may be removed chemically or by plasma or by heating.

Certain deposition and patterning methods are disclosed, as well as specific materials for the substrates, electrodes, dielectrics, protective layers, etc., and specific conditions including thicknesses, temperatures, etc., but any of these parameters It may be adjusted as needed for a particular TFT configuration and operating parameters without fundamentally changing the principles of embodiments comprising CNTs disclosed herein.

SWCNT stacking techniques

Referring to embodiments of methods for depositing CNT layers on TFTs, various techniques may be used in many embodiments, including various deposition and spraying methods.

In many embodiments, single-walled carbon nanotube thin films are solution coated, using atomizing techniques such as air, aerosol, or ultrasonic atomization, in connection with a mobile station manufacturing line as described with respect to FIGS. 5A-5C . . As shown in FIG. 5A , in many embodiments, a mobile station is provided on which substrates are loaded, and a desired processing temperature (eg, 60-200° C. or any other allowed by the underlying materials and the CNT materials themselves) is provided. While heating the substrates at a temperature of ), the carbon nanotube solution may be sprayed onto substrates of an appropriate size (eg, 4 inches to 100 inches) by, for example, aerosol or air spray coating. In such embodiments, the movement speed of the station may be controlled to maintain film thickness and uniformity (eg, 1 mm/s-1000 mm/s).

In other embodiments, ultrasonic spray coating may be used. As shown in Figure 5b, in these embodiments a stream of compressed air is passed through an aspirator, which locally reduces the pressure of the air, making it possible to draw the carbon nanotube solution from the vessel at normal atmospheric pressure. During the process, the ultrasonic nozzle atomizes the carbon nanotube solution into very small droplets having a diameter of, for example, several μm to about 1000 μm. Small droplets are then deposited onto the substrate at an appropriate processing temperature (eg, up to 400° C.) so that the droplets are immediately dried to mitigate O-ring aggregations. In various embodiments, A temperature of 100° C. may be used, although any suitable air pressure may be used (depending on the viscosity of the material), but in many embodiments the compressed air pressure will be 20 psi (1.38 bar) depending on the solution viscosity and the size of the aspirator required for lamination. ) to 100 psi (6.8 bar).

In embodiments comprising an aerosol spray coating (as shown in FIG. 5C ), the carbon nanotube solution is subjected to high pressure gas (e.g., 200-1000 standard cubic centimeters/minute (sccm)), or sonication (e.g., For example, 20 V-48 V, 10-100 watts) can be used to create a 1-5 micron aerosol that is brought to the spray head by a carrier gas (eg 10-30 sccm). It should be understood that these process parameters are exemplary only and that other lamination properties may be utilized depending on the type of material, the properties of the aerosol desired, and the thickness of the coating to be formed.

6 and 7 show images of thin films of SWCNT spray coated on substrates using an airbrush technique ( FIG. 6 ) and an aerosol technique ( FIG. 7 ) according to embodiments. In many embodiments, the carbon nanotube thin films thus formed are treated with acetic acid gas generated by airbrush spray or aerosol spray and then washed with isopropanol to achieve transparent carbon nanotube surfaces. Transparent carbon nanotube surfaces were characterized by atomic force microscopy (AFM). These samples could not be characterized on glass substrates using scanning electron microscopy due to the high insulating properties of these substrates. As shown, FIG. 8 provides an AFM image of an airbrush sprayed SWCNT thin film, and FIG. 9 provides an AFM image of an aerosol sprayed SWCNT thin film. These images make it possible to demonstrate the robust nature of the deposition process and the ability of SWCNTs to deposit high-quality thin film coatings.

In embodiments, carbon nanotube thin films formed according to these spray coating processes are used to replace amorphous silicon in 4-photomask photolithography processes, and as described above with reference to FIGS. 3 and 4 , an industrial manufacturing standard method The drain/source electrodes, the dielectrics, the upper gate-type electrodes, and the pixel electrodes are patterned according to the patterns.

Although the embodiments shown in FIGS. 3 and 4 are shown extending beyond the channel, to reduce sub-threshold current leakage, other embodiments use photolithography to pattern at least one activated carbon nanotube thin film. Additional photomasks are available. In such embodiments, the CNT layer outside of the transistor channels may be removed by an appropriate etching technique, such as, for example, O ₂ plasma or wet etching. In these various embodiments, the transparent uniform carbon nanotube thin film may be solution-developed after being coated with photoresist (PR) and exposed to light. In these developed regions, the carbon nanotube thin film is etched using, for example, O ₂ plasma or wet chemical etching, for example, a buffered HF solution. Then, the undeveloped PR is peeled off, leaving a patterned carbon nanotube thin film. A flow chart providing one embodiment of such a method is provided in FIG. 10 . It should be understood that any of the steps and techniques listed in the flowchart may be substituted for as described above.

In still other embodiments, to reduce the use of an extra photomask for patterning the activated carbon nanotubes and to reduce the consumption of the carbon nanotube solution, SWCNT thin films can be printed onto a substrate. In many of these embodiments, an aerosol jet printer can be used to print activated carbon nanotube thin films using small nozzle sizes (eg, less than 100 μm). Aerosol jet printers can deposit linewidths of less than 10 μm with a registration accuracy of 2 μm. To this end, an aerosol jet printer prints carbon nanotubes on the patterned drain/source marks. An image of this aerosol printing setup is provided in FIG. 11 . 12 shows photographic and optical images of exemplary drain/source marks prior to printing SWCNT films. 13 provides photographic and optical images of a thin film of SWCNT printed on the drain/source marks. As described above, the aerosol jet printed carbon nanotubes may be treated with an aerosol spray or airbrush spray acetic acid gas, and then washed with isopropanol. These transparent carbon nanotube thin films can be characterized by SEM. According to embodiments, the SEM image ( FIG. 14 ) displays transparent carbon nanotube films on drain/source markers. As shown in FIG. 15 , the transparent carbon nanotube films were characterized with the Keithly 4200 semiconductor characterization system to exhibit semiconductor properties.

Due to the small number of process steps, limited amount of material, and high throughput, to further take advantage of low cost, low environmental impact, and large area manufacturing, embodiments are described in conjunction with a roll-to-roll system with a high-speed process. The aforementioned aerosol jet printing methods (including high precision with registration accuracy of 1 to 2 μm) are proposed. With the use of these roll-to-roll aerosol jet printers, SWCNT inks can be printed in a fast manner that can be mass-produced on an a-Si TFT backplane manufacturing line. In addition, fully printed SWCNT TFT backplanes can be fabricated in high volume using a roll-to-roll system. In order to match industrial speed, as shown in Figure 16, embodiments disclose that multiple aerosol jet printer heads mounted on a mobile station can be used for high-speed printing carbon nanotube thin films. Above the mobile station, these multiple aerosol jet printer heads can print multiple carbon nanotube patterns.

Exemplary embodiments

Additional embodiments and features are set forth in part in the illustrative embodiments below, and will become apparent to those skilled in the art upon review of the specification or may be learned by practice of the invention. None of the specific embodiments are proposed to limit the scope of the remainder of the specification and drawings, which are provided by way of example of the apparatuses, methods, and materials disclosed herein. In particular, although specific combinations of structures and materials have been recited, it is to be understood that these are provided as examples only, and that any suitable alternative architectures and materials may be substituted.

Example 1: Comparison of conventional a-Si TFT and CNT TFT technologies

A flowchart of an exemplary method for fabricating an amorphous silicon TFT backplane on fabrication lines is provided in FIG. 17 . As shown in this method, amorphous Si is deposited over large areas by plasma enhanced chemical vapor deposition, and then other devices are fabricated according to different conventional fabrication steps. In embodiments, amorphous silicon may be replaced with CNTs. These CNT films can be laminated and/or printed according to the techniques described above. Using these transparent carbon nanotube thin films according to embodiments, standard industrial manufacturing methods further pattern drain/source electrodes, dielectrics, top gate-type electrodes and pixel electrodes as shown in FIGS. 18 and 19 . can be used to

Example 3: SWCNT TFT

Using the above-described techniques, it is possible to form a single-walled carbon nanotube thin film transistor as shown in FIG. 20, for example.

Example 2: Display

Finally, although the preceding exemplary embodiments and discussion have focused on methods, architectures, and structures for individual devices and backplanes, it is understood that the same architectures and structures may be coupled to a display device as pixels. will be understood In such embodiments, a plurality of SWCNT TFTs may be coupled and interconnected, as is well known to those skilled in the art, such as electronically coupling devices to addressing electrode lines as described herein, for a display such as an AMOLED display. A TFT backplane is formed.

equality

While several embodiments have been described, it will be appreciated by those skilled in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. In addition, many well-known methods and elements have not been described in order to avoid unnecessarily obscuring the present invention. Accordingly, the foregoing description should not be construed as limiting the scope of the present invention.

Those skilled in the art will understand that the embodiments disclosed herein are described by way of example and not limitation. Accordingly, matters included in the preceding description or illustrated in the accompanying drawings should be construed as illustrative rather than restrictive. The following claims are intended to include all general and specific features described herein, as well as all statements of the scope of the methods and systems that may be said to fall therebetween as a matter of language.

Claims (23)

A method for manufacturing a single-walled carbon nanotube thin film transistor backplane, comprising:
providing a substrate;
patterning a gate electrode and a dielectric layer on the substrate to form a channel;
laminating a back layer composed of a thin film layer of single-walled carbon nanotubes on the dielectric layer; And
patterning at least one n+ layer, drain and source electrodes on the backside layer using a photomask and a photolithography process, thereby exposing a portion of the backside layer overlapping the channel A method of manufacturing a thin film transistor backplane. In claim 1,
The method for manufacturing a single-walled carbon nanotube thin film transistor backplane, wherein the back layer is laminated by a spray technique selected from the group consisting of aerosol spray, air spray, and ultrasonic spray. In claim 2,
A method of manufacturing a single-walled carbon nanotube thin film transistor backplane, wherein the single-walled carbon nanotube aerosol is formed from an aqueous solution of single-walled carbon nanotubes that is sonicated in an ultrasonic nozzle and emitted in a carrier gas stream. In claim 1,
A method for manufacturing a single-walled carbon nanotube thin film transistor backplane, wherein the back layer is printed on a substrate using aerosol jet printing as a single-walled carbon nanotube aerosol. In claim 4,
A method for manufacturing a single-walled carbon nanotube thin film transistor backplane, wherein the single-walled carbon nanotube aerosol is formed by a technique selected from ultrasonic atomization. In claim 5,
A method for manufacturing a single-walled carbon nanotube thin film transistor backplane, wherein the stacked line width is less than 10 μm with a registration accuracy of less than 2 μm. . In claim 1,
The method for manufacturing a single-walled carbon nanotube thin film transistor backplane, wherein the single-walled carbon nanotubes are high-purity single chiral single-walled carbon nanotubes. In claim 8,
The single-walled carbon nanotubes are (6,4), (9,1), (8,3), (6,5), (7,3), (7,5), (10,2), ( 8,4), (7,6), (9,2), and a method for manufacturing a single-walled carbon nanotube thin film transistor backplane having an index selected from mixtures thereof. In claim 1,
A method for manufacturing a single-walled carbon nanotube thin film transistor backplane, wherein the single-walled carbon nanotube thin film is formed of a plurality of individual thin films. In claim 1,
The method for manufacturing a single-walled carbon nanotube thin film transistor backplane further comprising laminating and patterning an etch stop layer on the backside layer so that an etch stop overlaps the channel. In claim 1,
A method for manufacturing a single-walled carbon nanotube thin film transistor backplane, further comprising treating the single-walled carbon nanotube thin film with an acid gas. In claim 12,
A method of manufacturing a single-walled carbon nanotube thin film transistor backplane in which the acid gas is deposited through aerosol spray. In claim 12,
A method of manufacturing a single-walled carbon nanotube thin film transistor backplane, further comprising washing the treated single-walled carbon nanotube thin film. 15. In claim 14,
at least 100

The method of manufacturing a single-walled carbon nanotube thin film transistor backplane further comprising sintering the single-walled carbon nanotube thin film at a temperature of. In claim 1,
Thin films are formed with sub-threshold leakage current,
spin coating a photoresist on a single-walled carbon nanotube thin film;
defining a pattern over the photoresist by photolithography to create regions of defined photoresist and undefined photoresist;
solution developing the defined pattern to form a developed photoresist; And
A method of manufacturing a single-walled carbon nanotube thin film transistor backplane, comprising plasma or wet etching the single-walled carbon nanotube thin film using a developed photoresist to form a patterned single-walled carbon nanotube thin film. A method for manufacturing a single-walled carbon nanotube thin film transistor backplane, comprising:
providing a substrate;
forming a gate electrode and a dielectric layer on the substrate by patterning;
patterning at least one n+ layer and drain and source electrodes on the dielectric layer using a photomask and a photolithography process to expose a portion of the dielectric overlapping the channel;
laminating a back layer composed of a thin film layer of single-walled carbon nanotubes on the n+ layer, the drain and electrode layers, and the dielectric layer; And
A method of manufacturing a single-walled carbon nanotube thin film transistor backplane, comprising laminating a protective layer on the backside layer. In claim 17,
wherein the back layer is laminated by a spray technique selected from the group consisting of aerosol spray, air spray, and ultrasonic spray. In claim 17,
wherein the back layer is printed on the substrate using aerosol jet printing as a single wall carbon nanotube aerosol. In claim 17,
A method for manufacturing a single-walled carbon nanotube thin film transistor backplane, wherein the single-walled carbon nanotubes are high-purity single chiral single-walled carbon nanotubes. 21. In claim 20,
Single-walled carbon nanotubes (6,4), (9,1), (8,3), (6,5), (7,3), (7,5), (10,2), (8 , 4), (7,6), (9,2), and a method for manufacturing a single-walled carbon nanotube thin film transistor backplane having an index selected from mixtures thereof. 18. In claim 1 or 17,
The method of manufacturing a single-walled carbon nanotube thin film transistor backplane further comprising integrating the single-walled carbon nanotube thin film transistor backplane into a display device. A system configured to stack a single-walled carbon nanotube thin film transistor backplane, comprising:
a plurality of print heads mounted in association with the mobile station;
a plurality of printer heads in fluid communication with a solution of an aqueous solution of single-walled carbon nanotubes to deposit a thin film of single-walled carbon nanotubes on a substrate positioned on the mobile station; And
The printer heads are integrated with a photomask and photolithography process to pattern and form at least one drain and source electrode, a dielectric, one or more top gated electrodes, and one or more pixel electrodes over the stacked thin film. A method of manufacturing a tube thin film transistor backplane.

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