CN111146326B - Thermoelectric device and preparation method thereof - Google Patents
Thermoelectric device and preparation method thereof Download PDFInfo
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- CN111146326B CN111146326B CN201911222436.4A CN201911222436A CN111146326B CN 111146326 B CN111146326 B CN 111146326B CN 201911222436 A CN201911222436 A CN 201911222436A CN 111146326 B CN111146326 B CN 111146326B
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000002070 nanowire Substances 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 28
- KAJBHOLJPAFYGK-UHFFFAOYSA-N [Sn].[Ge].[Si] Chemical compound [Sn].[Ge].[Si] KAJBHOLJPAFYGK-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000010438 heat treatment Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910021332 silicide Inorganic materials 0.000 claims description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229910019001 CoSi Inorganic materials 0.000 claims description 6
- 229910005883 NiSi Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052732 germanium Inorganic materials 0.000 abstract description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- BLMUAVFFONATJG-UHFFFAOYSA-L dipotassium;4-[4-(4-sulfonatophenyl)hexan-3-yl]benzenesulfonate Chemical compound [K+].[K+].C=1C=C(S([O-])(=O)=O)C=CC=1C(CC)C(CC)C1=CC=C(S([O-])(=O)=O)C=C1 BLMUAVFFONATJG-UHFFFAOYSA-L 0.000 description 4
- 230000005678 Seebeck effect Effects 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/01—Manufacture or treatment
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/80—Constructional details
- H10N10/85—Thermoelectric active materials
- H10N10/851—Thermoelectric active materials comprising inorganic compositions
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a preparation method of a thermoelectric device, comprising the steps of providing a first substrate and a second substrate, forming an oxide layer on the first substrate, and forming a silicon germanium tin alloy layer on the second substrate; bonding the oxide layer and the silicon germanium tin alloy layer, and removing the second substrate; etching the silicon germanium tin alloy layer to form a plurality of nanowires; depositing a dielectric layer to isolate the nanowires; forming contact electrodes at two ends of the plurality of nanowires, and forming heating electrodes at the outer sides of the contact electrodes; and (5) annealing treatment. The invention also provides a thermoelectric device, which is prepared by adopting the preparation method of the thermoelectric device. According to the invention, the silicon germanium tin alloy layer is etched to form a plurality of nanowires, namely the formed nanowires are silicon germanium tin alloy, and because silicon is alloyed with other elements in the IV group, such as germanium and tin, the conductivity and carrier mobility of the nanowire material can be greatly increased, and the thermal conductivity of the nanowire material is reduced, so that the thermoelectric quality factor ZT can be improved, and the thermoelectric conversion efficiency can be increased.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a thermoelectric device and a preparation method thereof.
Background
Today, the problems of fossil energy shortage and environmental pollution are prominent, and the diversification and efficient multi-stage utilization of energy become an important technical approach for solving the problems of energy and environment systematically. Thermoelectric devices are used as a self-sufficient energy source, and can directly convert heat energy into electric energy according to Seebeck effect (Seebeck effect), and can maintain an infinite effective life at a proper temperature, so that the thermoelectric devices are used as a high-new technology in the energy source field and become one of the hot spots of international research.
The efficiency of a thermoelectric device fabricated according to the seebeck effect can be characterized by a thermoelectric figure of merit ZT, calculated as:
ZT=σ*s 2 *T/κ
wherein σ is electrical conductivity, s is seebeck coefficient, T is operating temperature, and κ is thermal conductivity.
As can be seen from the calculation formula of the figure of merit ZT, it is critical to improve the efficiency of thermoelectric devices to develop thermoelectric materials with high seebeck coefficient and electrical conductivity, as well as low thermal conductivity.
Research proves that after the thermal conductivity of the thermoelectric material is greatly reduced, the ZT value corresponding to the nanowire can be improved, but at the same time, the nanowire is very likely to have higher resistance, and the performance of the thermoelectric device is also reduced; how to prepare thermoelectric devices with good performance and higher ZT value becomes a problem to be solved urgently.
Disclosure of Invention
In view of the above, it is an object of the present invention to provide a thermoelectric device capable of improving a thermoelectric quality factor and a method of manufacturing the same.
In order to achieve the above purpose, the present invention adopts the following technical scheme: a method of manufacturing a thermoelectric device, comprising the steps of: providing a first substrate and a second substrate, forming an oxide layer on the first substrate, and forming a silicon germanium tin alloy layer on the second substrate;
bonding the oxide layer and the silicon germanium tin alloy layer, and removing the second substrate;
etching the silicon germanium tin alloy layer to form a plurality of nanowires;
depositing a dielectric layer to isolate the nanowires;
forming contact electrodes at two ends of the plurality of nanowires, and forming heating electrodes at the outer sides of the contact electrodes;
and (5) annealing treatment.
Preferably, the silicon germanium tin alloy layer has a layer thickness of less than or equal to 500 nanometers.
Preferably, the length of the nanowires is not less than 50 microns.
Preferably, the contact electrode is formed at both ends of the plurality of nanowires, and the step of forming the heating electrode outside the contact electrode includes:
etching downwards from the top layer of the dielectric layer to form contact holes, wherein the contact holes are positioned at two ends of the nanowire;
forming silicide at the bottom of the contact hole and at the contact position with the nanowire;
depositing metal;
a contact electrode is formed at the contact hole based on the metal, and a heating electrode is formed outside the contact electrode.
Preferably, the silicide is NiSi, tiSi 2 Or CoSi 2 Any one of them; the layer thickness of the silicide is less than or equal to 50 nanometers.
Preferably, the metal is any one of Ni, ti, cu, pt, cr, au, al.
Preferably, the oxide layer is silicon dioxide, and the dielectric layer is any one of silicon dioxide or silicon nitride;
and forming an oxide layer and a dielectric layer by adopting a thermal oxidation method, a chemical vapor deposition method, an atomic layer deposition method or a physical vapor deposition method.
Preferably, the first substrate and the second substrate are each any one of IV, II-V, III-V and II-VI compound semiconductor materials.
The present invention also provides a thermoelectric device comprising:
the semiconductor device comprises a first substrate, an oxide layer formed on the first substrate, a plurality of nanowires formed on the oxide layer, and a plurality of nanowires which are silicon germanium tin nanowires; a dielectric layer for isolating the nanowires; a contact electrode contacting both ends of each nanowire, and a heating electrode disposed outside the contact electrode.
Preferably, the thickness of the nanowires is less than or equal to 500 nanometers.
Preferably, the length of the nanowires is not less than 50 microns.
Preferably, silicide is formed at the contact of the contact electrode and the nanowire.
Preferably, the silicide is NiSi, tiSi 2 Or CoSi 2 Any one of them; the layer thickness of the silicide is less than or equal to 50 nanometers.
Preferably, the material of the contact electrode and the heating electrode is any one of Ni, ti, cu, pt, cr, au, al.
Preferably, the oxide layer is silicon dioxide, and the dielectric layer is any one of silicon dioxide or silicon nitride.
Preferably, the first substrate is any one of IV, II-V, III-V and II-VI compound semiconductor materials.
In summary, compared with the prior art, the invention has the following advantages:
the invention forms a plurality of nanowires by etching the silicon germanium tin alloy layer, namely the formed nanowires are silicon germanium tin alloy, and because silicon is alloyed with other elements in the IV group, such as germanium and tin, the conductivity and carrier mobility of the nanowires can be greatly increased, and the heat conductivity of the nanowires is reduced.
Drawings
FIG. 1 is a flow chart of a method of fabricating a thermoelectric device according to the present invention;
fig. 2 to 15 are structure change diagrams corresponding to each step of the method for manufacturing a thermoelectric device according to the present invention.
The semiconductor device comprises a first substrate 10, an oxide layer 11, a second substrate 20, a silicon germanium tin alloy layer 21, a nanowire 22, a dielectric layer 30, a dielectric layer 40, a contact electrode 400, a contact hole 401, a metal layer 402, silicide 41, a heating electrode 42 and metal.
Detailed Description
The following describes specific embodiments according to the present invention with reference to the drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.
In order to improve the thermoelectric quality factor of a thermoelectric device, the invention provides a thermoelectric device and a preparation method thereof.
Fig. 1 shows an embodiment of a method for manufacturing a thermoelectric device according to the present invention, including the steps of:
s10, referring specifically to fig. 2 and 3, providing a first substrate 10 and a second substrate 20, forming an oxide layer 11 on the first substrate 10, and forming a silicon germanium tin alloy layer 21 on the second substrate 20;
in this step, an oxide layer 11 may be formed on the first substrate 10 by a thermal oxidation method, a chemical vapor deposition method, an atomic layer deposition method, or a physical vapor deposition method. A silicon germanium tin alloy layer 21 may be formed on the second substrate 20 by epitaxial growth.
Preferably, the oxide layer 11 is silicon dioxide, having a thickness of less than or equal to 10 microns.
Preferably, the thickness of the silicon germanium tin alloy layer 21 is selected to be a suitable value between greater than 0 and less than or equal to 500 nanometers.
Illustratively, the first substrate 10 and the second substrate 20 are each any one of IV, II-V, III-V and II-VI compound semiconductor materials, such as a silicon substrate, a germanium-silicon substrate, an SOI substrate or a GOI substrate.
Preferably, the first substrate 10 and the second substrate 20 are silicon substrates, which have low manufacturing cost, abundant raw materials, good performance and are convenient for manufacturing thermoelectric devices.
Of course, the first substrate 10, the second substrate 20 and the oxide layer 11 may be any other existing material that meets the working requirements. The thicknesses of the first substrate 10, the oxide layer 11, the second substrate 20 and the sige tin alloy layer 21 may be selected to any suitable value according to practical requirements.
It should be further noted that the materials of the first substrate 10 and the second substrate 20 may be the same or different, and the thicknesses may be equal or unequal.
S11, referring specifically to fig. 4, 5 and 6, bonding the oxide layer 11 and the silicon germanium tin alloy layer 21, and removing the second substrate 20;
in this step, the first substrate 10 having the oxide layer 11 may be faced upward, and then the second substrate 20 having the sige tin alloy layer 21 may be inverted, so that the sige tin alloy layer 21 is faced to the oxide layer 11, and the two may be closely bonded to form a whole by any bonding method.
Then, the second substrate 20 is completely removed by any one of the conventional thinning processes or a combination of the thinning process and the etching process of the etching solution, and finally the sige tin alloy layer 21 is exposed.
S12, referring specifically to 7, etching the silicon germanium tin alloy layer 21 to form a plurality of nanowires 22;
in this step, the exposed silicon germanium tin alloy layer 21 may be etched by photolithography and etching processes, thereby obtaining a plurality of nanowires 22.
The length of the plurality of nanowires 22 is not less than 50 microns; to create a sufficiently large temperature differential across the nanowire 22 in its direction of extension; wherein, the range of this temperature difference is: 50 to 2000 ℃.
The number of the nanowires 22 is greater than or equal to 1; to capture enough heat to generate more energy. The specific length of the nanowire 22 may also be selected to be a suitable value according to different practical situations.
S13, referring specifically to 8, depositing a dielectric layer 30 to isolate the nanowires 22;
after the nanowires 22 are formed, a dielectric layer 30 is deposited over the formed structure; the dielectric layer 30 may be any of silicon dioxide or silicon nitride. The deposited dielectric layer 30 completely covers the top and side walls of the nanowire 22 and the plane in which the nanowire is located (oxide layer 11).
Of course, other materials having insulating or isolating effects may be selected for dielectric layer 30.
The dielectric layer 30 may be formed using a thermal oxidation method, a chemical vapor deposition method, an atomic layer deposition method, or a physical vapor deposition method.
S14, specifically fig. 14 and 15, contact electrodes 40 are formed at both ends of the plurality of nanowires 22, and heating electrodes 41 are formed outside the contact electrodes 40.
The method of forming the contact electrode 40 and forming the heating electrode 41 outside the contact electrode 40 is as follows:
s140, see fig. 9 and 10 in particular, where fig. 10 is a cross-sectional view from A-A of fig. 9, contact holes 400 are etched from the top layer of dielectric layer 30 down, contact holes 400 are located at both ends of nanowire 22, contact holes 400 are formed by etching dielectric layer 30, and the bottoms of the holes in the contact portions with nanowire 22 are terminated at the surface of nanowire 22, and the thickness of dielectric layer 30 is uniform as a whole, so that the bottoms of the holes not in contact with nanowire 22 are terminated at oxide layer 11.
S141, referring specifically to fig. 11 and 12, silicide 402 is formed at the bottom of the first contact hole 400;
in this step, silicide 402 may be NiSi, tiSi 2 Or CoSi 2 Any one of them; the layer thickness of silicide 402 is less than or equal to 50 nanometers. Silicide 402 is in direct contact with nanowire 22 and the opposing metal electrode is in direct contact with nanowire 22, enabling low contact resistance and improved thermoelectric device performance.
Specifically, a metal layer 401 may be deposited on the formed structure, and the metal layer 401 outside the contact hole 400 is removed, and the metal layer 401 in the contact hole 400 contacts and reacts with the surfaces of the two ends of the nanowire 22 to form the silicide 402;
s142, referring specifically to fig. 13 to 15, a metal 42 is deposited, and the metal 42 forms a contact electrode 40 at the contact hole 400, and a heating electrode 41 is formed outside the contact electrode 40;
in this step, the metal 42 is any one of Ni, ti, cu, pt, cr, au, al, and the deposited metal 42 has a layer thickness that can fill the contact hole 400 and completely cover the top layer of the dielectric layer 30.
A photolithographic etching process may be used to first define the area to be etched away, and then a dry etching or wet etching process may be used to etch away the metal 42 in the area, to finally form the contact electrode 40 and the heating electrode 41.
The contact electrode 40 and the heating electrode 41 may also be formed based on the metal 42 using a lift-off process.
S15, annealing treatment.
In this step, any existing annealing process may be used to anneal the formed structure to repair surface defects or relieve internal stresses.
The present invention also provides a thermoelectric device prepared by using the steps S10 to S15, referring specifically to fig. 14 and 15, wherein fig. 15 is a cross-sectional view taken along A-A of fig. 14, and includes a first substrate 10, an oxide layer 11 formed on the first substrate 10, a plurality of nanowires 22 formed on the oxide layer 11, and a plurality of nanowires 22 each being a sige nanowire; a dielectric layer 30 for isolating the nanowires; a contact electrode 40 contacting both ends of each nanowire 22, and a heating electrode 41 disposed outside the contact electrode 40.
Further, the thickness of the nanowire 22 is less than or equal to 500 nanometers on the basis of the above embodiment.
Further, the length of the nanowire 22 is not less than 50 μm on the basis of the above embodiment.
Further, on the basis of the above embodiment, silicide 402 is formed at the contact of the contact electrode 40 and the nanowire 22.
Further, based on the above embodiment, the silicide 402 is NiSi, tiSi 2 Or CoSi 2 Any one of them; silicide 402 has a thickness less than or equal to 50 nanometers.
Further, on the basis of the above embodiment, the material of the contact electrode 40 and the heating electrode 41 is any one of Ni, ti, cu, pt, cr, au, al.
Further, on the basis of the above embodiment, the oxide layer 11 is silicon dioxide, and the dielectric layer 30 is any one of silicon dioxide and silicon nitride.
Of course, the oxide layer 11 and the dielectric layer 30 may be other materials that can meet the performance requirements.
Further, on the basis of the above-described embodiment, the first substrate 10 is any one of IV, II-V, III-V, and II-VI compound semiconductor materials, such as a silicon substrate, a germanium-silicon substrate, an SOI substrate, or a GOI substrate, or the like.
By combining the above, the invention forms a plurality of nanowires by etching the silicon germanium tin alloy layer, namely the formed nanowires are silicon germanium tin alloy, and because silicon is alloyed with other elements in the IV group, such as germanium and tin, the conductivity and carrier mobility of the nanowires can be greatly increased, and the thermal conductivity of the nanowires is reduced.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A method of fabricating a thermoelectric device, comprising the steps of:
providing a first substrate and a second substrate, forming an oxide layer on the first substrate, and forming a silicon germanium tin alloy layer on the second substrate;
bonding the oxide layer and the silicon germanium tin alloy layer, and removing the second substrate;
etching the silicon germanium tin alloy layer to form a plurality of nanowires; the length of the nanowire is not less than 50 micrometers; to create a sufficiently large temperature differential across the nanowire in the opposite direction of its extension;
depositing a dielectric layer to isolate the nanowire;
etching downwards from the top layer of the dielectric layer to form contact holes, wherein the contact holes are positioned at two ends of the nanowire;
forming silicide at the bottom of the contact hole and at the contact position with the nanowire; the layer thickness of the silicide is less than or equal to 50 nanometers;
depositing metal;
forming a contact electrode at the contact hole based on the metal, and forming a heating electrode outside the contact electrode;
and (5) annealing treatment.
2. The method of claim 1, wherein the silicon germanium tin alloy layer has a layer thickness of less than or equal to 500 nanometers.
3. The method of claim 1, wherein the silicide is NiSi, tiSi 2 Or CoSi 2 Any one of the following.
4. The method of claim 1, wherein the metal is any one of Ni, ti, cu, pt, cr, au, al.
5. The method of claim 1, wherein the oxide layer is silicon dioxide and the dielectric layer is any one of silicon dioxide and silicon nitride;
and forming the oxide layer and the dielectric layer by adopting a thermal oxidation method, a chemical vapor deposition method, an atomic layer deposition method or a physical vapor deposition method.
6. The method of manufacturing a thermoelectric device according to claim 1, wherein the first substrate and the second substrate are each any one of group IV, II-V, III-V, and II-VI compound semiconductor materials.
7. A thermoelectric device, comprising:
a first substrate, an oxide layer formed on the first substrate, a plurality of nanowires formed on the oxide layer, and a plurality of nanowires which are silicon germanium tin nanowires; the length of the nanowire is not less than 50 micrometers; to create a sufficiently large temperature differential across the nanowire in the opposite direction of its extension; a dielectric layer for isolating the nanowires; the dielectric layer is internally provided with a contact hole which is formed by etching downwards from the top of the dielectric layer, the contact hole is positioned at two ends of a plurality of nanowires, silicide is formed at the bottom of the contact hole and at the contact position with the nanowires, and the thickness of the silicide is less than or equal to 50 nanometers; the contact hole is provided with a contact electrode and a heating electrode arranged outside the contact electrode.
8. The thermoelectric device of claim 7, wherein the nanowires have a thickness of less than or equal to 500 nanometers.
9. The thermoelectric device of claim 7 wherein the nanowires have a length of not less than 50 microns.
10. The thermoelectric device of claim 7 wherein the silicide is NiSi, tiSi 2 Or CoSi 2 Any one of them; the silicide has a layer thickness of less than or equal to 50 nanometers.
11. The thermoelectric device according to claim 7, wherein the material of the contact electrode and the heating electrode is any one of Ni, ti, cu, pt, cr, au, al.
12. The thermoelectric device of claim 7 wherein the oxide layer is silicon dioxide and the dielectric layer is any one of silicon dioxide or silicon nitride.
13. The thermoelectric device of claim 7 wherein the first substrate is any one of group IV, II-V, III-V, and II-VI compound semiconductor materials.
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