CN111146279A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN111146279A
CN111146279A CN201911021012.1A CN201911021012A CN111146279A CN 111146279 A CN111146279 A CN 111146279A CN 201911021012 A CN201911021012 A CN 201911021012A CN 111146279 A CN111146279 A CN 111146279A
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pattern
semiconductor
sub
work function
nitride layer
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CN201911021012.1A
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CN111146279B (zh
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李炳训
朴钟昊
金完敦
玄尚镇
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体器件包括：多个半导体图案，所述多个半导体图案在衬底上顺序地堆叠并彼此间隔开；以及栅电极，所述栅电极位于所述多个半导体图案上。所述栅电极包括顺序地堆叠在所述多个半导体图案上的覆盖图案和功函数图案。所述覆盖图案包括第一金属氮化物层和第二金属氮化物层，所述第一金属氮化物层包括第一金属元素，所述第二金属氮化物层包括功函数大于所述第一金属元素的功函数的第二金属元素。所述第一金属氮化物层设置在所述第二金属氮化物层与所述多个半导体图案之间。所述第一金属氮化物层比所述第二金属氮化物层薄。

Description

半导体器件
相关申请的交叉引用
本申请要求于2018年11月2日在韩国知识产权局提交的韩国专利申请No.10-2018-0133297的优先权，通过引用将其全部内容并入本文。
技术领域
本发明构思的一些示例实施例涉及半导体器件，更具体地说，涉及包括栅极环绕式(gate-all-around type)晶体管的半导体器件。
背景技术
半导体器件由于小尺寸、多功能性和/或低制造成本而在电子工业中具有重要作用。半导体器件可以包括存储逻辑数据的半导体存储器件、处理逻辑数据的操作的半导体逻辑器件以及同时具有存储元件和逻辑元件的混合半导体器件。随着电子工业的发展，半导体器件对高度集成的要求越来越高。例如，半导体器件对于高可靠性、高速度和/或多功能性的要求越来越高。半导体器件已经逐渐变得复杂和集成，以满足这些要求的特性。
发明内容
本发明构思的一些示例实施例提供了一种包括具有各种阈值电压的栅极环绕式晶体管的半导体器件。
根据本发明构思的一些示例实施例，半导体器件可以包括：多个半导体图案，所述多个半导体图案在衬底上顺序地堆叠并彼此间隔开；以及栅电极，所述栅电极位于所述多个半导体图案上。所述栅电极可以包括顺序地堆叠在所述多个半导体图案上的覆盖图案和功函数图案。所述覆盖图案可以包括第一金属氮化物层和第二金属氮化物层，所述第一金属氮化物层包括第一金属元素，所述第二金属氮化物层包括功函数大于所述第一金属元素的功函数的第二金属元素。所述第一金属氮化物层可以设置在所述第二金属氮化物层与所述多个半导体图案之间。所述第一金属氮化物层可以比所述第二金属氮化物层薄。
根据本发明构思的一些示例实施例，半导体器件可以包括：衬底；以及多个晶体管，所述多个晶体管位于所述衬底上，所述多个晶体管至少包括第一晶体管和第二晶体管。所述第一晶体管可以包括顺序地堆叠在多个第一半导体图案上的第一栅极介电层和第一栅电极，所述第一栅电极可以包括顺序地堆叠在所述多个第一半导体图案上的第一覆盖图案和第一功函数图案。所述第二晶体管可以包括顺序地堆叠在多个第二半导体图案上的第二栅极介电层和第二栅电极，所述第二栅电极可以包括顺序地堆叠在所述多个第二半导体图案上的第一功函数控制图案、第二覆盖图案和第二功函数图案。所述第一覆盖图案和所述第二覆盖图案均可以包括第一金属氮化物层和第二金属氮化物层，所述第一金属氮化物层包括第一金属元素，所述第二金属氮化物层包括功函数大于所述第一金属元素的功函数的第二金属元素。
根据本发明构思的一些示例实施例，半导体器件可以包括：衬底；以及多个晶体管，所述多个晶体管位于所述衬底上，所述多个晶体管至少包括第一晶体管和第四晶体管。所述第一晶体管可以包括位于多个第一半导体图案上的第一栅电极，所述第一栅电极包括第一覆盖图案，并且所述第一覆盖图案可以包括围绕所述多个第一半导体图案的多个第一子覆盖图案。所述第四晶体管可以包括位于多个第四半导体图案上的第四栅电极，所述第四栅电极包括第四覆盖图案，并且所述第四覆盖图案可以包括围绕所述多个第四半导体图案的多个第二子覆盖图案。所述第一覆盖图案和所述第四覆盖图案中的一个或更多个覆盖图案可以包括多个不同的层。
附图说明
图1示出的俯视图显示出根据本发明构思的一些示例实施例的半导体器件。
图2示出了沿着图1的线I-I'和线II-II'截取的截面图。
图3A和图3B示出的放大视图显示出图2的截面P1。
图4至图6示出的沿着图1的线I-I'和II-II'截取的截面图显示出根据本发明构思的一些示例实施例的制造半导体器件的方法。
图7示出的俯视图显示出根据本发明构思的一些示例实施例的半导体器件。
图8示出了沿着图7的线A1-A1'截取的截面图。
图9示出了沿着图7的线A2-A2'截取的截面图。
图10示出了沿着图7的线B-B'和线C-C'截取的截面图。
图11示出了沿着图7的线D-D'和线E-E'截取的截面图。
图12示出的放大截面图显示出第一晶体管TR1的第一部分P1。
图13示出的放大截面图显示出第二晶体管TR2的第一部分P1。
图14示出的放大截面图显示出第三晶体管TR3的第一部分P1。
图15和图16示出的放大截面图显示出第四晶体管TR4的第一部分P1。
具体实施方式
图1示出的俯视图显示出根据本发明构思的一些示例实施例的半导体器件。图2示出了沿着图1的线I-I'和线II-II'截取的截面图。图3A和图3B示出的放大视图显示出图2的截面P1。
参考图1、图2、图3A和图3B，晶体管TR可以设置在衬底100上。衬底100可以是半导体衬底。例如，衬底100可以是硅衬底或锗衬底。又例如，衬底100可以是绝缘体上硅(SOI)衬底。晶体管TR可以设置在形成有多个存储单元以存储数据的存储单元区域上。例如，衬底100的存储单元区域上可以设置有包括在多个SRAM单元中的存储单元晶体管。晶体管TR可以是存储单元晶体管之一。
或者，晶体管TR可以设置在逻辑晶体管将被包括在半导体器件的逻辑电路中的逻辑单元区域上。例如，逻辑晶体管可以设置在衬底100的逻辑单元区域上。然而，本发明构思的一些示例实施例不限于此。晶体管TR可以是NMOSFET。
器件隔离层ST可以设置在衬底100上。器件隔离层ST可以在衬底100的上部限定上图案UP。上图案UP可以在第二方向D2上延伸。器件隔离层ST可以填充位于上图案UP的相对侧的沟槽。器件隔离层ST的顶表面可以低于上图案UP的顶表面。
有源图案AP可以设置在上图案UP上。例如，有源图案AP可以与上图案UP竖直地叠置。有源图案AP可以具有在第二方向D2上延伸的线形。
有源图案AP可以包括沟道图案CH和源极/漏极图案SD。沟道图案CH可以布置在一对源极/漏极图案SD之间。沟道图案CH可以包括多个竖直堆叠的半导体图案NS。
半导体图案NS可以在垂直于衬底100的顶表面的第三方向D3上彼此间隔开。半导体图案NS可以彼此竖直地叠置。每一个源极/漏极图案SD可以与半导体图案NS的侧壁直接地接触。半导体图案NS可以将一对相邻的源极/漏极图案SD彼此连接。尽管示出了三个半导体图案NS，但是根据一些其他示例实施例，半导体图案NS的数量不限于三个。半导体图案NS可以具有彼此相同的厚度或者彼此不同的厚度。半导体图案NS可以包括Si、SiGe和/或Ge中的一种或更多种。
源极/漏极图案SD可以是由用作晶种层的半导体图案NS和上图案UP形成的外延图案。在一些示例实施例中，当晶体管TR是PMOSFET时，源极/漏极图案SD可以包括向沟道图案CH提供压应变的材料。例如，源极/漏极图案SD可以包括晶格常数大于沟道图案CH的半导体元素(例如，Si)的晶格常数的半导体元素(例如，SiGe)。在本说明书中，短语“包括某一元素”可以排除表述“包括非预期的杂质”。源极/漏极图案SD可以掺杂有杂质以具有P型导电性。
在一些其他示例实施例中，当晶体管TR是NMOSFET时，源极/漏极图案SD可以包括向沟道图案CH提供拉伸应变的材料。例如，源极/漏极图案SD可以包括晶格常数小于沟道图案CH的半导体元素的晶格常数的半导体元素。或者，源极/漏极图案SD可以包括与沟道图案CH的半导体元素相同的半导体元素(例如，Si)。源极/漏极图案SD可以掺杂有杂质以具有N型导电性。
栅电极GE可以设置为在第一方向上D1延伸，同时跨过沟道图案CH。栅电极GE可以包括顺序地堆叠在半导体图案NS上的覆盖图案CL和功函数图案WF。栅电极GE还可以包括电极图案EL。电极图案EL可以设置在功函数图案WF上。电极图案EL的电阻率可以小于功函数图案WF的电阻率。例如，电极图案EL可以包括至少一种低电阻或低电阻率金属，例如钨(W)、钛(Ti)和/或钽(Ta)。在一些示例实施例中，电极图案EL可以包括位于电极图案EL与功函数图案WF之间的边界上的阻挡图案(未示出)。阻挡图案可以沿着功函数图案WF的顶表面共形地设置。阻挡图案可以包括至少一个氮化物层，该氮化物层包含钨(W)、钛(Ti)和/或钽(Ta)中的一种或更多种。例如，阻挡图案可以是TiN层。在一些其他示例实施例中，电极图案EL可以不包括阻挡图案。
功函数图案WF可以填充半导体图案NS之间的第一空间SP1。功函数图案WF可以围绕每一个半导体图案NS。例如，功函数图案WF可以围绕半导体图案NS的顶表面、底表面和侧壁。在这种情况下，晶体管TR可以是栅极环绕式场效应晶体管。
栅电极GE可以包括第一部分P1和第二部分P2。第一部分P1可以位于彼此竖直地相邻的半导体图案NS之间的第一空间SP1中。例如，第一部分P1可以是彼此竖直地相邻的半导体图案NS之间的区段。
第二部分P2可以位于在最上面的半导体图案NS上的第二空间SP2中。第二空间SP2可以是由最上面的半导体图案NS和一对栅极间隔物GS包围的区域，这将在下面讨论。例如，第二部分P2可以是位于最上面的半导体图案NS上并且在一对栅极间隔物GS之间的区段。电极图案EL可以与栅电极GE的第一部分P1间隔开。
栅电极GE的第二部分P2可以包括顺序地堆叠的功函数图案WF、覆盖图案CL和电极图案EL。一对栅极间隔物GS可以设置在栅电极GE的相对侧壁上。栅极间隔物GS可以沿着栅电极GE在第一方向上D1延伸。栅极间隔物GS的顶表面可以比栅电极GE的顶表面高。例如，栅极间隔物GS可以包括SiCN、SiCON和/或SiN中的一种或更多种。又例如，栅极间隔物GS可以包括多层，该多层包括SiCN、SiCON和/或SiN中的两种或更多种。
栅极覆盖层CP可以设置在栅电极GE上。栅极覆盖层CP可以沿着栅电极GE在第一方向上D1延伸。栅极覆盖层CP的顶表面可以与栅极间隔物GS的顶表面共面。栅极覆盖层CP可以包括相对于层间介电层110具有蚀刻选择性的材料，这将在下面讨论。例如，栅极覆盖层CP可以包括SiON、SiCN、SiCON和/或SiN中的一种或更多种。
介电图案IP可以布置在源极/漏极图案SD与栅电极GE之间。介电图案IP可以布置在彼此竖直地间隔开的半导体图案NS之间。介电图案IP可以使栅电极GE与源极/漏极图案SD电绝缘。第一空间SP1可以由一对彼此水平相邻的介电图案IP和一对彼此竖直地相邻的半导体图案NS来限定。例如，介电图案IP可以包括氮化硅层。
界面层IL可以设置为围绕半导体图案NS。界面层IL可以直接覆盖半导体图案NS。例如，界面层IL可以包括氧化硅层。界面层IL可以覆盖上图案UP的顶表面和侧壁，该侧壁由器件隔离层ST暴露。
栅极介电层GI可以布置在栅电极GE与每一个半导体图案NS之间。栅极介电层GI可以共形地填充第一空间SP1的一部分。栅极介电层GI可以包括介电常数大于氧化硅层的介电常数的高k介电材料。例如，高k介电材料可以包括氧化铪、氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化锂、氧化铝、氧化铅钪钽和/或铌酸锌铅中的一种或更多种。
功函数图案WF可以是掺杂(或包含)硅或铝的金属碳化物层或金属氮化物层。在一些示例实施例中，功函数图案WF可以包括TiAlC层、TiSiC层、TaSiC层、TaAlC层、TiSiN层、TaSiN层、TiAlN层或TaAlN层。可以通过控制诸如硅和/或铝的掺杂剂的浓度来调节功函数图案WF的功函数。例如，功函数图案WF可以具有浓度落在约0.1at％至约25at％的范围内的杂质(例如，硅和/或铝)。在一些其他示例实施例中，功函数图案WF可以是氮化钛(TiN)层或氮氧化钛(TiON)层。
如图3A所示，覆盖图案CL可以包括第一金属氮化物层ML1和第二金属氮化物层ML2。第一金属氮化物层ML1可以包括第一金属元素，第二金属氮化物层ML2可以包括第二金属元素。第二金属元素的功函数可以大于第一金属元素的功函数。例如，第一金属元素可以是功函数小于第二金属元素的功函数的元素。例如，第二金属元素可以是钛(Ti)、钽(Ta)、钼(Mo)或钨(W)，第一金属元素可以是铝(Al)、铌(Nb)、镁(Mg)、镧(La)或钒(V)。第一金属氮化物层ML1还可以包括第二金属元素。第一金属元素在第一金属氮化物层ML1中可以具有约5at％至约25at％的比率。
第一金属氮化物层ML1可以是AlN层或TiAlN层，第二金属氮化物层ML2可以是TiN层或TiAlN层。第一金属氮化物层ML1和第二金属氮化物层ML2的组合可以是AlN/TiN层、AlN/TiAlN层或TiAlN/TiN层。在一些示例实施例中，第一金属氮化物层ML1和第二金属氮化物层ML2的位置可以相对于彼此改变。
覆盖图案CL可以防止(抑制、限制或减少)功函数图案WF中包含的掺杂剂的扩散。例如，覆盖图案CL可以不使栅极介电层GI接收功函数图案WF中包含的诸如铝的金属元素，这可以防止(抑制、限制或减少)晶体管TR的阈值电压的变化。
第一金属氮化物层ML1和第二金属氮化物层ML2均可以防止(抑制、限制或减少)功函数图案WF中包含的掺杂剂的扩散。例如，功函数图案WF可以包括第一金属元素。在这种情况下，包含在第一金属氮化物层ML1中的第一金属元素与相邻原子的结合强度可以大于包含在功函数图案WF中的第一金属元素与相邻原子的结合强度，结果可以防止(抑制、限制或减少)包含在功函数图案WF中的掺杂剂的扩散。例如，功函数图案WF可以包括第一金属元素、第二金属元素和碳。
第一金属氮化物层ML1可以降低晶体管TR的阈值电压。包含在第一金属氮化物层ML1中的第一金属元素的功函数可以小于包含在第二金属氮化物层ML2中的第二金属元素的功函数，因此与没有设置第一金属氮化物层ML1的情况相比，可以降低晶体管TR的阈值电压。
第一金属氮化物层ML1可以调节晶体管TR的阈值电压。例如，晶体管TR的阈值电压可以随着包含在第一金属氮化物层ML1中的第一金属元素的浓度增加而降低，并且可以随着第一金属氮化物层ML1的厚度增加而增加。
第二金属氮化物层ML2的电阻率可以小于第一金属氮化物层ML1的电阻率。第一金属氮化物层ML1可以比第二金属氮化物层ML2薄。第二金属氮化物层ML2的厚度可以为第一金属氮化物层ML1的厚度的约2倍至约5倍。例如，第一金属氮化物层ML1可具有约
Figure BDA0002247210910000082
至约
Figure BDA0002247210910000081
的厚度，第二金属氮化物层ML2可具有约
Figure BDA0002247210910000084
至约
Figure BDA0002247210910000083
的厚度。
半导体图案NS可以包括第一子半导体图案和位于第一子半导体图案上的第二子半导体图案。覆盖图案CL可以包括围绕第一子半导体图案的第一子覆盖图案SCL1和围绕第二子半导体图案的第二子覆盖图案SCL2。功函数图案WF可以在第一子覆盖图案SCL1与第二子覆盖图案SCL2之间延伸。
功函数图案WF可以包括围绕第一子半导体图案的第一子功函数图案SWF1和围绕第二子半导体图案的第二子功函数图案SWF2。在一些示例实施例中，如图3A所示，第一子功函数图案SWF1和第二子功函数图案SWF2可以在其之间的界面SL处彼此接触。在一些其他示例实施例中，如图3B所示，电极图案EL的一部分可以在第一子功函数图案SWF1与第二子功函数图案SWF2之间延伸。
层间介电层110可以设置在衬底100的整个表面上。层间介电层110可以覆盖源极/漏极图案SD。层间介电层110的顶表面可以与栅极覆盖层CP的顶表面基本共面。例如，层间介电层110可以包括氧化硅层或氮氧化硅层。虽然未示出，但是可以设置接触以穿透层间介电层110并与源极/漏极图案SD连接。接触可以包括金属材料，例如钨(W)、钛(Ti)和/或钽(Ta)。
诸如在本发明构思的一些示例实施例中公开的栅极环绕式晶体管可以具有随着高集成度而减小的栅极长度，从而可能难以通过控制功函数层和/或功函数控制层的厚度来调节阈值电压。特别地，对于NMOSFET，通过减小功函数控制层的厚度来降低其阈值电压的程度可能是有限的。根据本发明构思的一些示例实施例，可以设置由双层组成的覆盖图案CL。双层覆盖图案CL可以防止(抑制、限制或减少)功函数图案WF中包含的掺杂剂的扩散，并且可以降低晶体管TR的阈值电压(例如，在不改变功函数控制层的厚度的情况下，阈值电压可以降低期望的程度)。
图4至图6示出的沿着图1的线I-I'和线II-II'截取的截面图显示出根据本发明构思的一些示例实施例的制造半导体器件的方法。为了简洁起见，将省略对重复组件的描述。
参考图1和图4，可以在衬底100的整个表面上交替地且重复地堆叠牺牲层120和半导体层130。半导体层130可以重复地堆叠三次，但是本发明构思的一些其他示例实施例不限于此。牺牲层120可以包括相对于半导体层130具有蚀刻选择性的材料。在一些示例实施例中，半导体层130可以包括在蚀刻牺牲层120的工艺中基本上不被蚀刻的材料。例如，在蚀刻牺牲层120的工艺中，牺牲层120与半导体层130的蚀刻速率比可以落在约10∶1至约200∶1的范围内。例如，牺牲层120可以包括SiGe或Ge，半导体层130可以包括Si。
牺牲层120和半导体层130可以通过外延生长工艺形成，其中衬底100用作晶种层。牺牲层120和半导体层130可以连续地形成在同一腔室中。牺牲层120和半导体层130可以在衬底100的整个表面上共形地生长。
可以将牺牲层120、半导体层130和衬底100图案化以形成初步有源图案PAP。图案化工艺可以蚀刻衬底100的上部以形成上图案UP。初步有源图案PAP可以设置在上图案UP上。初步有源图案PAP可以形成为具有在第二方向D2延伸的线形或条形。
当图案化工艺蚀刻衬底100的上部时，可以在上图案UP的相对侧形成沟槽。可以形成器件隔离层ST来填充沟槽。器件隔离层ST的形成可以包括：在衬底100的整个表面上形成介电层；以及使介电层凹陷，直到完全暴露初步有源图案PAP。因此，器件隔离层ST的顶表面可以低于上图案UP的顶表面。
牺牲栅极图案140可以形成为跨过初步有源图案PAP。牺牲栅极图案140可以形成为具有在第一方向D1上延伸的线形或条形。可以在对应的牺牲栅极图案140上提供栅极掩模图案MP。牺牲栅极图案140和栅极掩模图案MP的形成可以包括：在衬底100上顺序地形成牺牲栅极层和栅极掩模层；以及顺序地图案化栅极掩模层和牺牲栅极层。牺牲栅极层可以包括多晶硅。栅极掩模层可以包括氮化硅层或氮氧化硅层。
可以在牺牲栅极图案140的相对侧壁上形成一对栅极间隔物GS。例如，栅极间隔物GS可以包括SiCN、SiCON和/或SiN中的一种或更多种。栅极间隔物GS的形成可以包括：通过诸如化学气相沉积(CVD)或原子层沉积(ALD)的沉积工艺形成间隔物层；以及对间隔物层执行各向异性蚀刻工艺。
参考图1和图5，可以将初步有源图案PAP图案化以形成沟道图案CH。可以通过使用栅极掩模图案MP和栅极间隔物GS作为蚀刻掩模来图案化初步有源图案PAP。因此，上图案UP可以被栅极掩模图案MP和栅极间隔物GS部分地暴露。
例如，可以将初步有源图案PAP的牺牲层120图案化以形成牺牲图案125。可以将初步有源图案PAP的半导体层130图案化以形成半导体图案NS。在图案化工艺之后，可以水平地去除牺牲图案125的暴露部分以形成凹陷区域DR。凹陷区域DR的形成可以包括使用相对于牺牲图案125具有蚀刻选择性的蚀刻源来执行蚀刻工艺。例如，当半导体图案NS包括Si并且牺牲图案125包括SiGe时，凹陷区域DR的形成可以包括执行使用包括过乙酸的蚀刻剂的蚀刻工艺。
可以形成介电图案IP以填充凹陷区域DR。介电图案IP可以跨半导体图案NS彼此竖直地间隔开。例如，介电层可以共形地形成在衬底100的整个表面上。介电层可以填充凹陷区域DR。此后，可以蚀刻介电层，直到介电图案IP局部地保留在凹陷区域DR中。
可以在每一个沟道图案CH的相对侧上形成源极/漏极图案SD。例如，源极/漏极图案SD可以通过外延生长工艺形成，其中上图案UP用作晶种层。沟道图案CH和源极/漏极图案SD可以彼此连接，以包括在沿第二方向D2延伸的有源图案AP中。
在一些示例实施例中，源极/漏极图案SD可以由向沟道图案CH提供压应变的材料形成。例如，源极/漏极图案SD可以由晶格常数大于Si的晶格常数的SiGe形成。在选择性外延生长工艺期间或之后，可以用P型杂质掺杂源极/漏极图案SD。
在一些其他示例实施例中，源极/漏极图案SD可以由与沟道图案CH的半导体元素相同的半导体元素(例如，Si)形成。在选择性外延生长工艺期间或之后，可以用N型杂质掺杂源极/漏极图案SD。
参考图1和图6，可以在衬底100的整个表面上形成层间介电层110。可以对层间介电层110执行平坦化工艺，直到暴露牺牲栅极图案140的顶表面。平坦化工艺可以包括回蚀工艺和/或化学机械抛光(CMP)工艺。当层间介电层110被平坦化时，栅极掩模图案MP也可以被去除。例如，层间介电层110可以由氧化硅层或氮氧化硅层形成。
可以对通过平坦化工艺暴露的牺牲栅极图案140执行选择性去除。牺牲栅极图案140的去除可以在衬底100上形成沟槽TC。沟槽TC可以暴露牺牲图案125。可以选择性地去除暴露的牺牲图案125。例如，当牺牲图案125包括SiGe并且半导体图案NS包括Si时，选择性蚀刻工艺可以使用包括过乙酸的蚀刻剂。蚀刻剂还可以包括氢氟酸(HF)溶液和去离子水。源极/漏极图案SD可以被介电图案IP和层间介电层110覆盖，因此可以被保护而免受选择性蚀刻工艺的影响。
可以去除牺牲图案125以形成第一空间SP1和第二空间SP2。第一空间SP1可以是彼此竖直地相邻的半导体图案NS之间的空白区域。第二空间SP2可以是由一对栅极间隔物GS和最上面的半导体图案NS包围的空白区域。第一空间SP1和第二空间SP2可以在空间上连接到暴露半导体图案NS的沟槽TC。
返回参照图1、图2和图3A，可以在沟槽TC中顺序地形成界面层IL、栅极介电层GI和栅电极GE。界面层IL的形成可以包括使用等离子体对暴露于沟槽TC的半导体图案NS执行氧化工艺。因此，可以从暴露的半导体图案NS生长界面层IL。界面层IL可以直接围绕暴露的半导体图案NS的表面。
界面层IL的形成可以包括热氧化工艺和/或化学氧化工艺。氧化工艺可以使用氧等离子体、臭氧等离子体和/或蒸气等离子体中的一种或更多种。例如，界面层IL可以包括氧化硅层。
可以在界面层IL上共形地形成栅极介电层GI。栅极介电层GI可以部分地填充沟槽TC的第一空间SP1。栅极介电层GI可以部分地填充第二空间SP2。栅极介电层G1可以直接覆盖介电图案IP和界面层IL。栅极介电层GI可以使用介电常数大于氧化硅层的介电常数的高k介电材料形成。
栅电极GE的形成可以包括在栅极介电层GI上顺序地形成覆盖图案CL、功函数图案WF和电极图案EL。可以通过诸如ALD的沉积工艺形成覆盖图案CL。覆盖图案CL可以包括第一金属氮化物层ML1和第二金属氮化物层ML2。第一金属氮化物层ML1和第二金属氮化物层ML2可以原位形成。例如，第一金属氮化物层ML1和第二金属氮化物层ML2可以在同一腔室中连续地形成。
第一金属氮化物层ML1可以由氮化物层形成，该氮化物层包括功函数低的第一金属元素，例如铝(Al)、铌(Nb)、镁(Mg)、镧(La)或钒(V)。例如，当第一金属氮化物层ML1是氮化铝层时，可以使用TMA、TEA或AlCl4作为铝前体，并可以使用NH3作为氮源。可以通过控制铝前体和氮源的供应周期来调节第一金属氮化物层ML1的铝的浓度。可以在供应铝前体的步骤与供应氮源的步骤之间进行吹扫步骤。
第二金属氮化物层ML2可以由包括诸如钛(Ti)、钽(Ta)、钼(Mo)或钨(W)的第二金属元素的氮化物层形成。例如，当第二金属氮化物层ML2是氮化钛层时，可以使用TiCl4作为钛前体，并可以使用NH3作为氮源。可以在供应钛前体的步骤与供应氮源的步骤之间进行吹扫步骤。
可以通过诸如ALD的沉积工艺形成功函数图案WF。例如，功函数图案WF可以由掺杂(或包含)硅或铝的金属碳化物层或金属氮化物层形成。覆盖图案CL和功函数图案WF可以部分地填充第二空间SP2。此外，覆盖图案CL和功函数图案WF可以完全地填充第一空间SP1。
可以执行使形成在第二空间SP2中的栅极介电层GI、覆盖图案CL和功函数图案WF的上部凹陷的工艺。此后，可以顺序地形成电极图案EL和栅极覆盖层CP，以填充第二空间SP2。
图7示出的俯视图显示出根据本发明构思的一些示例实施例的半导体器件。图8示出了沿着图7的线A1-A1'截取的截面图。图9示出了沿着图7的线A2-A2'截取的截面图。图10示出了沿着图7的线B-B'和线C-C'截取的截面图。图11示出了沿着图7的线D-D'和线E-E'截取的截面图。图12示出的放大截面图显示出第一晶体管TR1的第一部分P1。图13示出的放大截面图显示出第二晶体管TR2的第一部分P1。图14示出的放大截面图显示出第三晶体管TR3的第一部分P1。图15和图16示出的放大截面图显示出第四晶体管TR4的第一部分P1。为了简洁起见，将省略对重复组件的描述。
参照图7至图16，可以设置包括第一区域RG1至第四区域RG4的衬底100。第一区域RG1至第四区域RG4可以分别在其上设置有第一晶体管TR1至第四晶体管TR4。第一晶体管TR1至第四晶体管TR4可以具有彼此不同的阈值电压。例如，第四晶体管TR4的阈值电压可以大于第三晶体管TR3的阈值电压。第三晶体管TR3的阈值电压可以大于第二晶体管TR2的阈值电压。第二晶体管TR2的阈值电压可以大于第一晶体管TR1的阈值电压。然而，一些其他示例实施例不限于此。
第一晶体管TR1至第四晶体管TR4的不同的阈值电压可以由第一栅电极GE1至第四栅电极GE4的不同构造引起。在一些示例实施例中，除了第一栅电极GE1至第四栅电极GE4之外，第一晶体管TR1至第四晶体管TR4可以关于第一半导体图案NS1至第四半导体图案NS4、界面层IL和栅极介电层GI相同地配置。例如，第一半导体图案NS1至第四半导体图案NS4可以以相同的高度形成以具有相同的厚度。在一些其他示例实施例中，第一晶体管TR1至第四晶体管TR4可以关于第一半导体图案NS1至第四半导体图案NS4、界面层IL和栅极介电层GI不同地配置。
第一栅电极GE1可以包括顺序地形成在栅极介电层GI上的第一覆盖图案CL1和第一功函数图案WF1。第二栅电极GE2可以包括顺序地形成在栅极介电层GI上的第一功函数控制图案TL1、第二覆盖图案CL2和第二功函数图案WF2。第三栅电极GE3可以包括顺序地形成在栅极介电层GI上的第二功函数控制图案TL2、第三覆盖图案CL3和第三功函数图案WF3。第四栅电极GE4可以包括顺序地形成在栅极介电层GI上的第三功函数控制图案TL3和第四覆盖图案CL4。根据一些示例实施例，第一栅电极GE1至第四栅电极GE4可以分别包括在对应的第二部分P2上的第一电极图案EL1至第四电极图案EL4，或者根据一些其他示例实施例，第一栅电极GE1至第四栅电极GE4中的一个或更多个可以不包括电极图案。
第一栅电极GE1可以不包括功函数控制图案。第一功函数控制图案TL1至第三功函数控制图案TL3可以同时由相同的材料形成，但是可以具有彼此不同的厚度。例如，第一功函数控制图案TL1至第三功函数控制图案TL3可以是包括钛、钽和/或钨中的一种或更多种的氮化物层。第一功函数控制图案TL1可以具有第一厚度t1，第二功函数控制图案TL2可以具有第二厚度t2，第三功函数控制图案TL3可以具有第三厚度t3。第三厚度t3可以大于第二厚度t2，第二厚度t2可以大于第一厚度t1。然而，一些其他示例实施例不限于此。
第一栅电极GE1至第四栅电极GE4可以分别包括第一覆盖图案CL1至第四覆盖图案CL4。第一覆盖图案CL1至第四覆盖图案CL4可以同时由相同的材料形成。例如，第一覆盖图案CL1至第四覆盖图案CL4可以具有相同的厚度。第一覆盖图案CL1至第四覆盖图案CL4均可以包括第一子覆盖图案SCL1和第二子覆盖图案SCL2。如图12至图14所示，第一功函数图案WF1至第三功函数图案WF3均可以在第一子覆盖图案SCL1与第二子覆盖图案SCL2之间延伸。另一方面，如图15所示，第四栅电极GE4可以不包括功函数图案，并且第一子覆盖图案SCL1和第二子覆盖图案SCL2可以在它们之间的界面SL处彼此接触。或者，如图16所示，第四覆盖图案CL4可以包括第一子覆盖图案SCL1和第二子覆盖图案SCL2，并且第一子覆盖图案SCL1和第二子覆盖图案SCL2均可以包括第一金属氮化物层ML1，但是不包括第二金属氮化物层。例如，第一金属氮化物层ML1可以在它们之间的界面SL处彼此接触。在图16所示的示例实施例中，第三功函数控制图案TL3可以具有比图15所示的示例实施例中的第三功函数控制图案TL3的第三厚度t3大的第四厚度t4。
根据本发明构思的一些示例实施例，第一区域RG1至第四区域RG4上可以设置具有彼此不同的阈值电压的栅极环绕式晶体管。因此，可以实现具有多个阈值电压的半导体器件。
根据本发明构思的一些示例实施例，可以提供由双层组成的覆盖图案。双层覆盖图案可以防止(抑制、限制或减少)功函数图案中包含的掺杂剂(例如，硅和/或铝)的扩散，并且晶体管的阈值电压可以降低(例如，通过控制或调节双层覆盖图案的第一金属层中的铝浓度，晶体管的阈值电压可以降低期望的程度，而无需改变功函数层和/或功函数控制层的厚度)。
尽管已经参考附图讨论了本发明构思的一些示例实施例，但是应当理解，在不脱离本发明构思的精神和范围的情况下，可以在其中做出形式和细节上的各种改变。因此，应当理解，上述示例实施例在所有方面仅是说明性的，而不是限制性的。

Claims (25)

1.一种半导体器件，所述半导体器件包括：
多个半导体图案，所述多个半导体图案在衬底上顺序地堆叠并彼此间隔开；以及
栅电极，所述栅电极位于所述多个半导体图案上，
其中，所述栅电极包括顺序地堆叠在所述多个半导体图案上的覆盖图案和功函数图案，
所述覆盖图案包括第一金属氮化物层和第二金属氮化物层，所述第一金属氮化物层包括第一金属元素，所述第二金属氮化物层包括功函数大于所述第一金属元素的功函数的第二金属元素，
所述第一金属氮化物层设置在所述第二金属氮化物层与所述多个半导体图案之间，并且
所述第一金属氮化物层比所述第二金属氮化物层薄。
2.根据权利要求1所述的半导体器件，其中，所述第二金属氮化物层的电阻率小于所述第一金属氮化物层的电阻率。
3.根据权利要求1所述的半导体器件，其中，所述第一金属元素包括铝、铌、镁、镧或钒。
4.根据权利要求3所述的半导体器件，其中，所述第二金属元素包括钛、钽、钼或钨。
5.根据权利要求4所述的半导体器件，其中，所述第一金属氮化物层还包括所述第二金属元素。
6.根据权利要求1所述的半导体器件，其中，
所述第一金属氮化物层包括AlN层或TiAlN层，并且
所述第二金属氮化物层包括TiN层或TiAlN层。
7.根据权利要求1所述的半导体器件，其中，所述功函数图案包括所述第一金属元素。
8.根据权利要求7所述的半导体器件，其中，所述功函数图案还包括所述第二金属元素。
9.根据权利要求1所述的半导体器件，其中，所述第二金属氮化物层的厚度为所述第一金属氮化物层的厚度的2倍至5倍。
10.根据权利要求1所述的半导体器件，其中，
所述多个半导体图案包括第一子半导体图案和位于所述第一子半导体图案上的第二子半导体图案，
所述覆盖图案包括围绕所述第一子半导体图案的第一子覆盖图案和围绕所述第二子半导体图案的第二子覆盖图案，并且
所述功函数图案在所述第一子覆盖图案与所述第二子覆盖图案之间延伸。
11.根据权利要求10所述的半导体器件，其中，所述功函数图案包括围绕所述第一子半导体图案的第一子功函数图案和围绕所述第二子半导体图案的第二子功函数图案，所述第一子功函数图案和所述第二子功函数图案彼此接触。
12.根据权利要求10所述的半导体器件，其中，
所述栅电极还包括位于所述功函数图案上的电极图案，
所述功函数图案包括围绕所述第一子半导体图案的第一子功函数图案和围绕所述第二子半导体图案的第二子功函数图案，并且
所述电极图案在所述第一子功函数图案与所述第二子功函数图案之间延伸。
13.一种半导体器件，所述半导体器件包括：
衬底；以及
多个晶体管，所述多个晶体管至少包括第一晶体管和第二晶体管，所述多个晶体管位于所述衬底上，
所述第一晶体管包括顺序地堆叠在多个第一半导体图案上的第一栅极介电层和第一栅电极，所述第一栅电极包括顺序地堆叠在所述多个第一半导体图案上的第一覆盖图案和第一功函数图案，
所述第二晶体管包括顺序地堆叠在多个第二半导体图案上的第二栅极介电层和第二栅电极，所述第二栅电极包括顺序地堆叠在所述多个第二半导体图案上的第一功函数控制图案、第二覆盖图案和第二功函数图案，并且
所述第一覆盖图案和所述第二覆盖图案均包括第一金属氮化物层和第二金属氮化物层，所述第一金属氮化物层包括第一金属元素，所述第二金属氮化物层包括功函数大于所述第一金属元素的功函数的第二金属元素。
14.根据权利要求13所述的半导体器件，其中，
所述第一覆盖图案与所述第一栅极介电层接触，并且
所述第一晶体管的阈值电压小于所述第二晶体管的阈值电压。
15.根据权利要求13所述的半导体器件，其中，所述第一功函数图案包括所述第二金属元素。
16.根据权利要求15所述的半导体器件，其中，所述第一功函数控制图案和所述第二覆盖图案均包括TiN层。
17.根据权利要求13所述的半导体器件，其中，
所述多个晶体管还包括位于所述衬底上的第三晶体管，
所述第三晶体管包括顺序地堆叠在多个第三半导体图案上的第三栅极介电层和第三栅电极，
所述第三栅电极包括顺序地堆叠在所述多个第三半导体图案上的第二功函数控制图案和第三覆盖图案，并且
所述第二功函数控制图案比所述第一功函数控制图案厚。
18.根据权利要求13所述的半导体器件，其中，
所述多个晶体管还包括位于所述衬底上的第四晶体管，
所述第四晶体管包括顺序地堆叠在多个第四半导体图案上的第四栅极介电层和第四栅电极，
所述第四栅电极包括第四覆盖图案，
所述多个第四半导体图案包括第一子半导体图案和位于所述第一子半导体图案上的第二子半导体图案，并且
所述第四覆盖图案包括围绕所述第一子半导体图案的第一子覆盖图案和围绕所述第二子半导体图案的第二子覆盖图案，所述第一子覆盖图案和所述第二子覆盖图案彼此接触。
19.根据权利要求18所述的半导体器件，其中，所述第一子覆盖图案和所述第二子覆盖图案均包括金属氮化物层，所述金属氮化物层包括所述第一金属元素，所述第一子覆盖图案的所述金属氮化物层与所述第二子覆盖图案的所述金属氮化物层接触。
20.根据权利要求13所述的半导体器件，其中，所述第一金属氮化物层比所述第二金属氮化物层薄。
21.一种半导体器件，所述半导体器件包括：
衬底；以及
多个晶体管，所述多个晶体管至少包括第一晶体管和第四晶体管，所述多个晶体管位于所述衬底上，
所述第一晶体管包括位于多个第一半导体图案上的第一栅电极，所述第一栅电极包括第一覆盖图案，所述第一覆盖图案包括围绕所述多个第一半导体图案的多个第一子覆盖图案，
所述第四晶体管包括位于多个第四半导体图案上的第四栅电极，所述第四栅电极包括第四覆盖图案，所述第四覆盖图案包括围绕所述多个第四半导体图案的多个第二子覆盖图案，并且
所述第一覆盖图案和所述第四覆盖图案中的一个或更多个覆盖图案包括多个不同的层。
22.根据权利要求21所述的半导体器件，其中，所述第一覆盖图案和所述第四覆盖图案中的一个或更多个覆盖图案包括第一金属氮化物层和第二金属氮化物层，所述第一金属氮化物层包括第一金属元素，所述第二金属氮化物层包括功函数大于所述第一金属元素的功函数的第二金属元素。
23.根据权利要求22所述的半导体器件，其中，所述第四覆盖图案不包括所述第二金属氮化物层。
24.根据权利要求22所述的半导体器件，其中，所述第一金属氮化物层比所述第二金属氮化物层薄。
25.根据权利要求22所述的半导体器件，其中，
所述第一栅电极还包括位于所述第一覆盖图案上的功函数图案，并且
所述第四栅电极还包括位于所述第四覆盖图案与所述多个第四半导体图案之间的功函数控制图案。
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