CN111146272A - Super junction device and manufacturing method thereof - Google Patents
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- CN111146272A CN111146272A CN201911362994.0A CN201911362994A CN111146272A CN 111146272 A CN111146272 A CN 111146272A CN 201911362994 A CN201911362994 A CN 201911362994A CN 111146272 A CN111146272 A CN 111146272A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000007789 sealing Methods 0.000 claims abstract description 40
- 238000005520 cutting process Methods 0.000 claims abstract description 23
- 230000007547 defect Effects 0.000 claims abstract description 22
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention discloses a super junction device which comprises a device unit area, a sealing ring area and a cutting path area. In a plane of top view, the seal ring region surrounds the periphery of the corresponding device unit region, and the dicing lane region is located between the device unit regions. The second conduction type column of the super junction device is composed of a second conduction type epitaxial layer filled in the groove. Each groove is of a straight strip-shaped structure without turning, and in the length direction of the groove, each groove extends into the cutting channel area and has the extending length which enables the filling defects generated by the crystal orientation change of the length direction side face and the width direction top head side face of the groove to be close to the inner side face of the sealing ring area or extend out of the sealing area. The invention also discloses a manufacturing method of the super junction device. The invention can reduce the groove filling defect of the super junction, reduce the influence of the defect near the side surface of the groove top on the device unit area and improve the product yield.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction device; the invention also relates to a manufacturing method of the super junction device.
Background
The super junction is composed of alternately arranged P-type thin layers, also called P-type pillars (pilar), and N-type thin layers, also called N-type pillars, formed in a semiconductor substrate, and the device employing the super junction is a super junction device such as a super junction MOSFET. The technology of reducing the surface electric field (Resurf) in a body by utilizing the charge balance of the P-type thin layer and the N-type thin layer can improve the reverse breakdown voltage of the device and simultaneously keep smaller on-resistance.
The PN-spaced Pillar structure of the super junction is the biggest characteristic of the super junction. The conventional method for manufacturing the p-n spaced pilar structure mainly comprises two methods, one is obtained by multiple times of epitaxy and ion implantation, and the other is manufactured by deep trench etching and Epitaxy (EPI) filling. The latter method is to fabricate the super junction device by a trench process, in which a trench with a certain depth and width is first etched on an N-type doped epitaxial layer on the surface of a semiconductor substrate, such as a silicon substrate, and then a P-type doped silicon epitaxy is filled on the etched trench by an epitaxial Filling (EPI Filling) method.
The second method forms the super junction with a technical difficulty of trench filling. Trench filling is not only related to the profile of the trench, but also to the surface topology of the trench. The simplest straight strip shape is preferably selected for the trench surface layout because of the different growth rates during P-type epitaxial filling in different crystal orientations. The right angle and the fillet design are both very unfavorable for the filling process, and the high-yield production is difficult to realize.
The straight strip shape is easy to fill due to the good uniformity of the side wall of the groove, and the yield of the device is high. However, even in the straight bar shape, there is a variation in crystal orientation at the top of the trench, and thus there is a difference in EPI growth rate, which leads to a fill defect easily occurring near the top of the straight bar, and becomes a weak point of the device. And cause yield loss.
As shown in fig. 1, it is a layout structure diagram of the existing super junction device; the conventional super junction device includes a device cell region 101, a seal ring region 102, and a scribe line region 103.
In a top view, the seal ring region 102 surrounds the periphery of the corresponding device unit region 101, and the scribe lane region 103 is located between the device unit regions 101.
The super junction of the super junction device is formed by alternately arranging N-type columns and P-type columns 104; the P-type column 104 is composed of a P-type epitaxial layer filled in a trench formed in an N-type semiconductor substrate.
In the prior art, in order to avoid the filling problem caused by the crystal orientation change caused by the turning structure of the groove such as a right angle turn or a round angle turn, the grooves are arranged into a straight strip structure without a turn in the prior art.
However, as can be seen from fig. 1, the longitudinal side of the trench and the lateral side of the plug are still at an angle, which also causes a crystal orientation change, which also causes a filling defect, as indicated by reference numeral 105. The defects 105 can adversely affect device yield.
Disclosure of Invention
The invention aims to provide a super junction device, which can reduce the groove filling defect of a super junction, reduce the influence of the defect near the side surface of the groove top on a device unit area and improve the product yield. Therefore, the invention also provides a manufacturing method of the super junction device.
In order to solve the technical problem, the super junction device provided by the invention comprises a device unit area, a sealing ring area and a cutting path area.
In a top view, the seal ring region surrounds the periphery of the corresponding device unit region, and the dicing street region is located between the device unit regions.
The super junction of the super junction device is formed by alternately arranging first conductive type columns and second conductive type columns; the second conductive type column is composed of a second conductive type epitaxial layer filled in a trench formed in a first conductive type semiconductor substrate.
Each groove is of a straight strip-shaped structure without turning, in the length direction of the groove, each groove extends from the device unit area to the cutting path area, and the length of the groove extending into the cutting path area is enough to enable filling defects of the second conduction type epitaxial layer generated by crystal orientation changes of the length direction side face and the width direction top head side face of the groove to be close to the inner side face of the sealing ring area or extend out of the sealing area.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the sides of each of the trenches are slanted or perpendicular.
In a further improvement, the width of the scribe line region is several tens of μm.
In a further improvement, the distance that the trench extends out of the corresponding sealing ring area is more than 1 μm, and the maximum value that the trench extends out of the corresponding sealing ring area is that the trenches corresponding to two adjacent device unit areas are connected together.
In a further improvement, the outermost trench is located in the region of the seal ring in the width direction of the trench; alternatively, the outermost trench extends beyond the region of the seal ring in the width direction of the trench.
In a further improvement, the second conductivity type epitaxial layer is a second conductivity type silicon epitaxial layer.
The further improvement is that the first conductive type is N type, and the second conductive type is P type; or the first conduction type is P type, and the second conduction type is N type.
In order to solve the above technical problem, the method for manufacturing a super junction device provided by the present invention comprises the following steps:
step one, defining a device unit area, a sealing ring area and a cutting path area of the super junction device on a semiconductor substrate of a first conduction type.
In a top view, the seal ring region surrounds the periphery of the corresponding device unit region, and the dicing street region is located between the device unit regions.
And secondly, defining a forming area of a groove corresponding to a second conductive type column of a super junction of the super junction device, wherein each groove is in a straight strip structure without turning, each groove extends from the device unit area to the cutting channel area along the length direction of the groove, and the length of the groove extending to the cutting channel area meets the requirement that the filling defect of a second conductive type epitaxial layer generated by the crystal orientation change of the side surface of the top head in the length direction and the width direction of the groove is close to the inner side surface of the sealing ring area or extends out of the sealing area.
And step three, filling a second conductive type epitaxial layer in the groove to form second conductive type columns, forming first conductive type columns by the semiconductor substrate of the first conductive type between the second conductive type columns, and forming the super junction of the super junction device by the first conductive type columns and the second conductive type columns in an alternative arrangement mode.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the sides of each of the trenches are slanted or perpendicular.
In a further improvement, the width of the scribe line region is several tens of μm.
In a further improvement, the distance that the trench extends out of the corresponding sealing ring area is more than 1 μm, and the maximum value that the trench extends out of the corresponding sealing ring area is that the trenches corresponding to two adjacent device unit areas are connected together.
In a further improvement, the outermost trench is located in the region of the seal ring in the width direction of the trench; alternatively, the outermost trench extends beyond the region of the seal ring in the width direction of the trench.
The further improvement is that the first conductive type is N type, and the second conductive type is P type; or the first conduction type is P type, and the second conduction type is N type.
The grooves of the super junction are all arranged into straight strip structures without turning, so that the crystal directions of the side surfaces of the grooves in the length direction are consistent, and the filling defect caused by inconsistent crystal directions generated during turning of the grooves can be avoided.
The invention also combines the layout relation of the device unit area, the sealing ring area and the cutting channel area, and extends all the grooves from the device unit area to the cutting channel area along the length direction of the grooves, namely, the top side surface of the width direction of the grooves is positioned in the cutting channel area, and the extending length meets the requirement that the filling defect of the second conductive type epitaxial layer generated by the crystal orientation change of the length direction side surface and the width direction top side surface of the grooves is close to the inner side surface of the sealing ring area or extends out of the sealing area, thereby avoiding the defect near the top side surface of the grooves from generating adverse effect on the device unit area, and improving the product yield.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a layout structure diagram of a conventional super junction device;
fig. 2 is a layout structure diagram of a super junction device according to an embodiment of the present invention.
Detailed Description
As shown in fig. 2, it is a layout structure diagram of a super junction device according to an embodiment of the present invention; the super junction device comprises a device unit area 1, a sealing ring area 2 and a cutting path area 3.
In a plan view, the seal ring region 2 surrounds the outer periphery of the corresponding device unit region 1, and the scribe lane region 3 is located between the device unit regions 1.
The super junction of the super junction device is formed by alternately arranging a first conductive type column and a second conductive type column 4; the second conductive type column 4 is composed of a second conductive type epitaxial layer filled in a trench formed in a first conductive type semiconductor substrate.
Each of the trenches has a straight stripe structure without a turn, each of the trenches extends from the device cell region 1 into the scribe line region 3 in a length direction of the trench, and the length of the trench extending into the scribe line region 3 is such that a filling defect 5 of the second conductivity type epitaxial layer generated by a crystal orientation change of a lengthwise side surface and a widthwise top side surface of the trench approaches an inner side surface of the seal ring region 2 or extends outside the sealing region. That is, by extending the trench, the defect 5 can be extended as far as possible outside the sealing region, and even if the defect is located within the inner side surface of the sealing ring region 2, the yield of the device can still be improved.
In the embodiment of the invention, the semiconductor substrate is a silicon substrate. The second conductive type epitaxial layer is a second conductive type silicon epitaxial layer.
The side surface of each groove is inclined or vertical.
The width of the scribe line region 3 is several tens of μm, for example, 60 μm or more.
The distance that the grooves extend out of the corresponding sealing ring regions 2 is more than 1 μm, and the maximum value that the grooves extend out of the corresponding sealing ring regions 2 is that the grooves corresponding to two adjacent device unit regions 1 are connected together.
The outermost trench is located in a region of the seal ring in a width direction of the trench. In other embodiments, this can also be: in the width direction of the groove, the outermost groove extends to the outside of the sealing ring area, so that the load effect of groove etching and filling at the edge of the device unit area 1 can be reduced by arranging more grooves at the edge of the device unit area 1.
In the embodiment of the invention, the first conductive type is an N type, and the second conductive type is a P type. In other embodiments, this can also be: the first conductivity type is P-type and the second conductivity type is N-type.
The grooves of the super junction are all arranged into straight strip structures without turning, so that the crystal directions of the side surfaces in the length direction of the grooves are consistent, and the filling defect caused by inconsistent crystal directions generated when the grooves turn can be avoided.
In the embodiment of the present invention, in combination with the layout relationship of the device cell region 1, the seal ring region 2, and the scribe line region 3, each trench is extended from the device cell region 1 to the scribe line region 3 in the length direction of the trench, that is, the top side surface in the width direction of the trench is located in the scribe line region 3, and the extended length satisfies that the filling defect 5 of the second conductivity type epitaxial layer generated by the crystal orientation change of the side surface in the length direction and the top side surface in the width direction of the trench is close to the inner side surface of the seal ring region 2 or extends outside the sealed region, so that the defect near the top side surface of the trench can be prevented from adversely affecting the device cell region 1, and the product yield can be improved.
The manufacturing method of the super junction device comprises the following steps:
step one, defining a device unit area 1, a sealing ring area 2 and a cutting path area 3 of the super junction device on a semiconductor substrate of a first conduction type.
In a plan view, the seal ring region 2 surrounds the outer periphery of the corresponding device unit region 1, and the scribe lane region 3 is located between the device unit regions 1.
The semiconductor substrate is a silicon substrate.
The width of the scribe line region 3 is several tens of μm.
And secondly, defining a forming area of a groove corresponding to a second conductive type column 4 of the super junction device, wherein each groove is in a straight strip structure without turning, each groove extends from the device unit area 1 to the cutting channel area 3 along the length direction of the groove, and the length of the groove extending into the cutting channel area 3 meets the requirement that the filling defect 5 of a second conductive type epitaxial layer generated by the crystal orientation change of the length direction side face and the width direction top head side face of the groove is close to the inner side face of the sealing ring area 2 or extends out of the sealing area.
The side surface of each groove is inclined or vertical.
The distance that the grooves extend out of the corresponding sealing ring regions 2 is more than 1 μm, and the maximum value that the grooves extend out of the corresponding sealing ring regions 2 is that the grooves corresponding to two adjacent device unit regions 1 are connected together.
The outermost trench is located in a region of the seal ring in a width direction of the trench. Can also be: the outermost trench extends beyond the region of the seal ring in a width direction of the trench.
And step three, filling a second conductive type epitaxial layer in the groove to form the second conductive type columns 4, forming first conductive type columns by the semiconductor substrate of the first conductive type between the second conductive type columns 4, and forming the super junctions of the super junction device by the first conductive type columns and the second conductive type columns 4 in an alternate arrangement mode.
In the method of the embodiment of the invention, the first conductive type is an N type, and the second conductive type is a P type. In other embodiments the method can also be: the first conductivity type is P-type and the second conductivity type is N-type.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A super junction device, characterized by: the super junction device comprises a device unit area, a sealing ring area and a cutting path area;
on a plane of top view, the sealing ring area surrounds the periphery of the corresponding device unit area, and the cutting path area is positioned between the device unit areas;
the super junction of the super junction device is formed by alternately arranging first conductive type columns and second conductive type columns; the second conductive type column is composed of a second conductive type epitaxial layer filled in a groove, and the groove is formed in the semiconductor substrate of the first conductive type;
each groove is of a straight strip-shaped structure without turning, in the length direction of the groove, each groove extends from the device unit area to the cutting path area, and the length of the groove extending into the cutting path area is enough to enable filling defects of the second conduction type epitaxial layer generated by crystal orientation changes of the length direction side face and the width direction top head side face of the groove to be close to the inner side face of the sealing ring area or extend out of the sealing area.
2. The super-junction device of claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. The super-junction device of claim 1, wherein: the side surface of each groove is inclined or vertical.
4. The super-junction device of claim 1, wherein: the width of the scribe line region is several tens of μm.
5. The super-junction device of claim 4, wherein: the distance of the grooves extending out of the corresponding sealing ring areas is more than 1 mu m, and the maximum value of the grooves extending out of the corresponding sealing ring areas is that the grooves corresponding to two adjacent device unit areas are mutually connected.
6. The super-junction device of claim 1, wherein: the outermost groove is positioned in the region of the seal ring in the width direction of the groove; alternatively, the outermost trench extends beyond the region of the seal ring in the width direction of the trench.
7. The super-junction device of claim 2, wherein: the second conductive type epitaxial layer is a second conductive type silicon epitaxial layer.
8. The super-junction device of any one of claims 1 to 7, wherein: the first conductive type is N type, and the second conductive type is P type; or the first conduction type is P type, and the second conduction type is N type.
9. A method for manufacturing a super junction device is characterized by comprising the following steps:
step one, defining a device unit area, a sealing ring area and a cutting path area of a super junction device on a semiconductor substrate of a first conduction type;
on a plane of top view, the sealing ring area surrounds the periphery of the corresponding device unit area, and the cutting path area is positioned between the device unit areas;
defining a forming area of a groove corresponding to a second conductive type column of a super junction of the super junction device, wherein each groove is of a straight strip structure without turning, and extends from the device unit area to the cutting channel area along the length direction of the groove, and the length of the groove extending to the cutting channel area meets the requirement that the filling defect of a second conductive type epitaxial layer generated by the crystal orientation change of the side face in the length direction and the side face in the width direction of the groove is close to the inner side face of the sealing ring area or extends out of the sealing area;
and step three, filling a second conductive type epitaxial layer in the groove to form second conductive type columns, forming first conductive type columns by the semiconductor substrate of the first conductive type between the second conductive type columns, and forming the super junction of the super junction device by the first conductive type columns and the second conductive type columns in an alternative arrangement mode.
10. The method of manufacturing a super junction device of claim 9, wherein: the semiconductor substrate is a silicon substrate.
11. The method of manufacturing a super junction device of claim 9, wherein: the side surface of each groove is inclined or vertical.
12. The method of manufacturing a super junction device of claim 9, wherein: the width of the scribe line region is several tens of μm.
13. The method of manufacturing a super junction device of claim 4, wherein: the distance of the grooves extending out of the corresponding sealing ring areas is more than 1 mu m, and the maximum value of the grooves extending out of the corresponding sealing ring areas is that the grooves corresponding to two adjacent device unit areas are mutually connected.
14. The method of manufacturing a super junction device of claim 9, wherein: the outermost groove is positioned in the region of the seal ring in the width direction of the groove; alternatively, the outermost trench extends beyond the region of the seal ring in the width direction of the trench.
15. The method of manufacturing a super junction device according to any of claims 9 to 14, wherein: the first conductive type is N type, and the second conductive type is P type; or the first conduction type is P type, and the second conduction type is N type.
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| CN201911362994.0A CN111146272B (en) | 2019-12-26 | 2019-12-26 | Super junction device and manufacturing method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035680A (en) * | 2012-05-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Super junction device |
| CN103456674A (en) * | 2012-06-04 | 2013-12-18 | 上海华虹Nec电子有限公司 | Method for preparing deep groove morphology analyzing sample |
| CN105529363A (en) * | 2016-01-29 | 2016-04-27 | 上海华虹宏力半导体制造有限公司 | Super junction and manufacturing method thereof |
| US20170309705A1 (en) * | 2016-04-21 | 2017-10-26 | Super Group Semiconductor Co., Ltd. | Super-junction semiconductor device |
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- 2019-12-26 CN CN201911362994.0A patent/CN111146272B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035680A (en) * | 2012-05-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Super junction device |
| CN103456674A (en) * | 2012-06-04 | 2013-12-18 | 上海华虹Nec电子有限公司 | Method for preparing deep groove morphology analyzing sample |
| CN105529363A (en) * | 2016-01-29 | 2016-04-27 | 上海华虹宏力半导体制造有限公司 | Super junction and manufacturing method thereof |
| US20170309705A1 (en) * | 2016-04-21 | 2017-10-26 | Super Group Semiconductor Co., Ltd. | Super-junction semiconductor device |
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