CN111145809A - SRAM anti-irradiation unit based on FinFET technology - Google Patents
SRAM anti-irradiation unit based on FinFET technology Download PDFInfo
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- CN111145809A CN111145809A CN202010134721.7A CN202010134721A CN111145809A CN 111145809 A CN111145809 A CN 111145809A CN 202010134721 A CN202010134721 A CN 202010134721A CN 111145809 A CN111145809 A CN 111145809A
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- 230000005540 biological transmission Effects 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 22
- 230000008569 process Effects 0.000 abstract description 19
- 230000003471 anti-radiation Effects 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 9
- 230000015654 memory Effects 0.000 description 8
- 239000002245 particle Substances 0.000 description 5
- 238000005728 strengthening Methods 0.000 description 5
- 230000005855 radiation Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000002787 reinforcement Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- LMDZBCPBFSXMTL-UHFFFAOYSA-N 1-ethyl-3-(3-dimethylaminopropyl)carbodiimide Chemical compound CCN=C=NCCCN(C)C LMDZBCPBFSXMTL-UHFFFAOYSA-N 0.000 description 2
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- 230000005684 electric field Effects 0.000 description 1
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- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
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Abstract
The invention relates to an SRAM anti-radiation unit based on a FinFET process, which comprises a DICE anti-radiation unit formed based on the FinFET process, wherein the DICE anti-radiation unit comprises a read word line RWL and a write word line WL, and the read word line RWL and the write word line WL are connected to corresponding electrical levels to control PMOS transmission tube switches and separate read-write operations. The anti-radiation unit can improve the anti-radiation effect, improve the reading stability and eliminate the problem of writing failure caused by the process deviation of the small-size pull-up tube.
Description
Technical Field
The invention relates to the technical field of memories, in particular to an SRAM anti-radiation unit based on a FinFET process.
Background
The high-energy particles bombard the semiconductor device, interact with the device material in the incident process, and generate a large number of electron-hole pairs through direct ionization, indirect ionization and other modes. With the collection of charge, the circuit can generate a single event upset effect when the charge amount is greater than the amount of "critical charge" required for the circuit to upset. The single event upset effect is a "soft" error caused by a change in the state of a latch or memory cell, mainly a logic level upset caused by excessive transient current, and the wrong logic state is latched.
The conventional general Static Memory Cell (Static Random Access Memory Cell) has a 6T structure as shown in fig. 1, and is hereinafter referred to as a 6T SRAM Cell. When the Q node stores '1' and the QB node stores '0', the transistors P1 and N0 are in an off state, and the drains of the two transistors are sensitive nodes with single event effect. The high-energy particles bombard any position in the sensitive area, and the single-particle upset is possibly caused.
Whether the SRAM memory cell is in a holding state or a reading state or a writing state, a built-in electric field in a sensitive area exists all the time, so that the transistor performs a charge collection process when electron-hole pairs are generated. By taking the particle bombardment on the sensitive node Q point as an example, after the high-energy particles bombard the sensitive node Q point, the charges are collected to form a transient current pulse of the drain of the N0 tube, and the N0 tube is turned on. The Q-point voltage decreases with an increase in the amount of collected charge, and when the Q-point voltage is lowered to a certain value, the transistor P0 is turned off and causes a change in logic state at Q to reach a stable state. In this process, the voltages of the Q and QB storage nodes are affected mainly by two aspects: the gate of transistor N1 is continuously charged, keeping N1 in the on state, and point QB is discharged, restoring the SRAM cell to the correct logic state. But on the other hand, due to the generation of the drain pulse current of the transistor N0, the potential of the point Q is lowered to cause the states of the two transistors P1 and N1 to change, the P0 is gradually turned off and the P1 is turned on, and the storage node QB is charged. The QB point voltage is increased and fed back to the gates of the left inverters P0, N0, causing P0 to turn off and N0 to turn on, eventually holding the voltage at the storage node Q point low, and the logic state stored by the SRAM cell flips from "1" to "0". It can be seen that the 6T SRAM Cell is ineffective against single event effects.
In a traditional planar structure transistor process, the ratio of the driving capability (Idsatp) of the PMOS to the driving capability (Idsatn) of the NMOS is about 2.5-2. To achieve the same driving capability, the SRAM Cell area must be sacrificed. Meanwhile, some error models exist in the SRAM Cell reading and writing process. One of the error mechanisms of the read operation is that the read current of the memory cell is too small, which results in too slow read speed or even no read at all. One of the error mechanisms of the write operation is that the write margin is too small, so that the write operation cannot be performed within a certain time, and the specific expression is that the states before and after the write operation are the same. With the future higher working frequency, the challenge for writing operation is larger and larger, because the clock period is short, and it is difficult to write data successfully in a short time.
The single Event upset SEU (single Event Upset) strengthening method has a plurality of strengthening methods, such as process strengthening, system level strengthening, circuit level strengthening and the like, so that the circuit obtains better SEU resistance. And (4) process reinforcement, namely, a special process is adopted to inhibit single event upset, such as an SOI (silicon on insulator) technology, an epitaxial process and the like. And the system level reinforcement technology is used for carrying out error correction and detection on the information with errors through logic decision, such as EDAC error correction coding technology. The circuit level reinforcement is reinforced by adopting a method for increasing redundancy, such as DICE technology, triple modular redundancy technology and the like.
The DICE technology has the basic idea that redundant storage states are added in storage units, and a state recovery feedback circuit is used for recovering reversed data, so that the SEU resistance is high, and the application is wide. However, the conventional DICE cell structure has the following disadvantages: 1) the anti-irradiation effect in the read-write state is easy to lose efficacy; 2) the reading operation time is not fixed and is prolonged; 3) poor ability to write; 4) the layout design of the memory cell is very difficult to make, and the area balance is very difficult.
Disclosure of Invention
The invention aims to overcome the problems in the prior art and provides an SRAM anti-radiation unit based on a FinFET process, which can resist single event upset and improve the data reading stability and the data writing capability of a storage unit.
In order to achieve the technical purpose and achieve the technical effect, the invention is realized by the following technical scheme:
an SRAM anti-radiation unit based on FinFET technology comprises a DICE anti-radiation unit formed based on FinFET technology, wherein the DICE anti-radiation unit comprises a read word line RWL and a write word line WL, and the read word line RWL and the write word line WL are connected to corresponding electric levels to control PMOS transmission tube switches to separate read and write operations.
Further, the DICE radiation-resistant unit further comprises a first PMOS tube P0 to an eighth PMOS tube P7, and a first NMOS tube N0 to a sixth NMOS tube N5; wherein the content of the first and second substances,
the gates of the fifth PMOS transistor P4 to the eighth PMOS transistor P7 are connected with a write word line WL;
the drain of a fifth PMOS tube P4 is respectively connected with the drains of a first PMOS tube P0 and a first NMOS tube N0 and the gates of a second PMOS tube P1 and a fourth NMOS tube N3, the drain of a sixth PMOS tube P5 is respectively connected with the drains of a second PMOS tube P1 and a second NMOS tube N1 and the gates of a third PMOS tube P2 and a first NMOS tube N0, the drain of a seventh PMOS tube P6 is respectively connected with the drains of a third PMOS tube P2 and a third NMOS tube N2 and the gates of a fourth PMOS tube P3 and a second NMOS tube N1, and the drain of an eighth PMOS tube P7 is respectively connected with the drains of a fourth PMOS tube P3 and a fourth NMOS tube N3 and the gates of a first PMOS tube P0, a third NMOS tube N2 and a fifth NMOS tube N4;
the drain of the fifth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth NMOS transistor N5 is connected to the read word line RWL.
Furthermore, the sources of the first to fourth NMOS transistors N0 to N3 and the sixth NMOS transistor N5 are grounded, and the source of the fifth NMOS transistor N4 is connected to the read bit line RBL.
Further, the sources of the first to fourth PMOS transistors P0 to P3 are commonly connected to a power supply voltage terminal.
Further, the sources of the fifth PMOS transistor P4 and the seventh PMOS transistor P6 are commonly connected to the first bit line BL, and the sources of the sixth PMOS transistor P5 and the eighth PMOS transistor P7 are commonly connected to the second bit line BLB.
The invention has the beneficial effects that:
(1) the anti-irradiation unit can improve the anti-irradiation effect;
(2) the anti-irradiation unit can improve the reading stability;
(3) the anti-radiation unit can eliminate the problem of write failure caused by the process deviation of the small-size pull-up tube.
Drawings
FIG. 1 is a 6T static memory cell of the general type;
FIG. 2 is a circuit diagram of a DICE radiation-resistant unit according to the present invention;
fig. 3 is a diagram illustrating a write operation of the DICE radiation protection unit of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
An SRAM anti-radiation unit based on FinFET technology comprises a DICE anti-radiation unit formed based on FinFET technology, wherein the DICE anti-radiation unit comprises a read word line RWL and a write word line WL, and the read word line RWL and the write word line WL are connected to corresponding electric levels to control PMOS transmission tube switches to separate read and write operations.
As shown in fig. 2, the DICE radiation protection unit further includes first to eighth PMOS transistors P0 to P7, and first to sixth NMOS transistors N0 to N5; wherein the content of the first and second substances,
the gates of the fifth to eighth PMOS transistors P4 to P7 are connected to a write word line WL for performing a write operation;
the drain of a fifth PMOS tube P4 is respectively connected with the drains of a first PMOS tube P0 and a first NMOS tube N0 and the gates of a second PMOS tube P1 and a fourth NMOS tube N3, the drain of a sixth PMOS tube P5 is respectively connected with the drains of a second PMOS tube P1 and a second NMOS tube N1 and the gates of a third PMOS tube P2 and a first NMOS tube N0, the drain of a seventh PMOS tube P6 is respectively connected with the drains of a third PMOS tube P2 and a third NMOS tube N2 and the gates of a fourth PMOS tube P3 and a second NMOS tube N1, and the drain of an eighth PMOS tube P7 is respectively connected with the drains of a fourth PMOS tube P3 and a fourth NMOS tube N3 and the gates of a first PMOS tube P0, a third NMOS tube N2 and a fifth NMOS tube N4;
the drain of the fifth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth NMOS transistor N5 is connected to the read word line RWL for read operation.
The sources of the first to fourth NMOS transistors N0-N3 and the sixth NMOS transistor N5 are grounded, and the source of the fifth NMOS transistor N4 is connected to the read bit line RBL.
The sources of the first to fourth PMOS transistors P0-P3 are commonly connected to a power supply voltage terminal.
The sources of the fifth PMOS transistor P4 and the seventh PMOS transistor P6 are commonly connected to a first bit line BL, the sources of the sixth PMOS transistor P5 and the eighth PMOS transistor P7 are commonly connected to a second bit line BLB, and the voltage values of the first bit line BL and the second bit line BLB are opposite.
Working process and principle of the invention
In the present invention, as shown in fig. 2, nodes X0, X1, X2 and X3 are labeled in the circuit on the figure, and assuming that the values of the nodes X0, X1, X2 and X3 are "0101", the following MOS transistor names are abbreviated with the device symbol in fig. 2.
During a read operation, the voltage of the read word line RWL is pulled to a high level, the voltage of the write word line WL is pulled to a low level, so that the read and write operations are separated, and meanwhile, the read bit line RBL is precharged to a high level; since the node X3 is stored as "1", N4 and N5 form a pull-down path with the read bit line RBL, and the read bit line RBL is pulled down to a low level, completing the read operation; taking the example of bombarding the storage point X1 by using a negative current pulse, at this time, the X1 node becomes "0", N0 is cut off, P2 is turned on, at this time, the pull-up tube P2 pulls up the storage node X2 to "1", so that P3 and N0 are cut off, the storage nodes X0 and X3 are kept unchanged, and they are fed back to P0 and N2, respectively, the X1 and X2 are pulled back to "1", "0", and after the irradiation reaction is finished, the original values are restored; in the invention, the grid of the storage node X3 is connected with a transmission tube (namely the node X3 is connected with the grid of N4), so that the anti-interference performance is strong, the anti-irradiation effect is obvious in the reading operation process, and the reading stability is improved by single-ended reading and writing.
During writing operation, due to the particularity of the MOS tube, the traditional DICE anti-radiation unit can only perform writing '0' operation, but the invention combines the process characteristics of the FFinFET, and adopts PMOS as a transmission tube to perform writing '1' operation as shown in figure 3; generally in design, the write driver (write driver) for data can be relatively large in design; when data is written, the first bit line BL is driven to be '1', the second bit line BLB is pulled down to be '0', the driving capability of the data driver is strong, the transmission tube adopts PMOS design, the storage nodes X0 and X2 can be quickly charged to be '1', when the nodes X0 and X2 are charged to be '1', the pull-down tubes N1 and N3 are in a strong conduction state, the nodes X1 and X3 can be quickly discharged to be '0', the time for establishing positive feedback of the storage unit is short, the situation of new data writing failure is not easy to occur, meanwhile, the size of the pull-down tubes is large, the performance of the pull-down tubes is small along with process deviation, and the data writing capability of the novel DICE anti-irradiation unit is stable.
In addition, the novel DICE anti-radiation unit of the invention uses PMOS as the transmission tube, and the size ratio of PMOS to NMOS is 1: 1, PMOS and NMOS are more balanced than before, and the layout design of the memory cell is easier to achieve smaller area.
In addition, it should be noted that the terms "first", "second", "third", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. The DICE anti-irradiation unit is characterized by comprising a read word line RWL and a write word line WL, wherein the read word line RWL and the write word line WL are connected to corresponding levels to control PMOS transmission tube switches and separate read and write operations.
2. The SRAM irradiation resistant unit of claim 1, further comprising a first PMOS transistor P0 through an eighth PMOS transistor P7, and a first NMOS transistor N0 through a sixth NMOS transistor N5; wherein the content of the first and second substances,
the gates of the fifth PMOS transistor P4 to the eighth PMOS transistor P7 are connected with a write word line WL;
the drain of a fifth PMOS tube P4 is respectively connected with the drains of a first PMOS tube P0 and a first NMOS tube N0 and the gates of a second PMOS tube P1 and a fourth NMOS tube N3, the drain of a sixth PMOS tube P5 is respectively connected with the drains of a second PMOS tube P1 and a second NMOS tube N1 and the gates of a third PMOS tube P2 and a first NMOS tube N0, the drain of a seventh PMOS tube P6 is respectively connected with the drains of a third PMOS tube P2 and a third NMOS tube N2 and the gates of a fourth PMOS tube P3 and a second NMOS tube N1, and the drain of an eighth PMOS tube P7 is respectively connected with the drains of a fourth PMOS tube P3 and a fourth NMOS tube N3 and the gates of a first PMOS tube P0, a third NMOS tube N2 and a fifth NMOS tube N4;
the drain of the fifth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth NMOS transistor N5 is connected to the read word line RWL.
3. The SRAM irradiation resisting unit of claim 2, wherein the sources of the first N0 through fourth N3 NMOS transistors and the sixth N5 NMOS transistor are grounded, and the source of the fifth N4 NMOS transistor is connected to a read bit line RBL.
4. The SRAM irradiation resistant cell of claim 2, wherein sources of the first through fourth PMOS transistors P0-P3 are commonly connected to a power supply voltage terminal.
5. The SRAM irradiation resisting unit of claim 2 or 4, wherein sources of the fifth PMOS transistor P4 and the seventh PMOS transistor P6 are commonly connected to a first bit line BL, and sources of the sixth PMOS transistor P5 and the eighth PMOS transistor P7 are commonly connected to a second bit line BLB.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010134721.7A CN111145809A (en) | 2020-03-02 | 2020-03-02 | SRAM anti-irradiation unit based on FinFET technology |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010134721.7A CN111145809A (en) | 2020-03-02 | 2020-03-02 | SRAM anti-irradiation unit based on FinFET technology |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100110773A1 (en) * | 2008-07-07 | 2010-05-06 | Manoj Sachdev | Sram cell without dedicated access transistors |
| US20120069650A1 (en) * | 2009-08-13 | 2012-03-22 | Southeast University | Sub-threshold memory cell circuit with high density and high robustness |
| CN105869668A (en) * | 2016-03-25 | 2016-08-17 | 西安交通大学 | Radiation-proof DICE memory cell applied to DVS system |
| CN107103928A (en) * | 2017-04-27 | 2017-08-29 | 苏州无离信息技术有限公司 | A kind of new 8TSRAM element circuits system |
| CN110379448A (en) * | 2019-07-04 | 2019-10-25 | 安徽大学 | The 9T TFET and MOSFET element mixed type SRAM cell circuit of nargin are write with height |
-
2020
- 2020-03-02 CN CN202010134721.7A patent/CN111145809A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100110773A1 (en) * | 2008-07-07 | 2010-05-06 | Manoj Sachdev | Sram cell without dedicated access transistors |
| US20120069650A1 (en) * | 2009-08-13 | 2012-03-22 | Southeast University | Sub-threshold memory cell circuit with high density and high robustness |
| CN105869668A (en) * | 2016-03-25 | 2016-08-17 | 西安交通大学 | Radiation-proof DICE memory cell applied to DVS system |
| CN107103928A (en) * | 2017-04-27 | 2017-08-29 | 苏州无离信息技术有限公司 | A kind of new 8TSRAM element circuits system |
| CN110379448A (en) * | 2019-07-04 | 2019-10-25 | 安徽大学 | The 9T TFET and MOSFET element mixed type SRAM cell circuit of nargin are write with height |
Non-Patent Citations (1)
| Title |
|---|
| MILI LAVANIA等: "Read-Decoupled Radiation Hardened RD-DICE SRAM Cell for Low-Power Space Applications", 2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, 8 July 2019 (2019-07-08), pages 1 * |
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