CN211045046U

CN211045046U - SRAM anti-irradiation unit based on FinFET technology

Info

Publication number: CN211045046U
Application number: CN202020235667.0U
Authority: CN
Inventors: 张曼; 张立军; 张一平; 马亚奇
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2020-03-02
Filing date: 2020-03-02
Publication date: 2020-07-17
Anticipated expiration: 2030-03-02

Abstract

The utility model relates to an anti irradiation unit based on FinFET technology SRAM, include the DICE anti irradiation unit that constitutes based on the FinFET technology, DICE anti irradiation unit is including reading word line RW L and writing line W L, read word line RW L and writing line W L and be connected to corresponding level to control PMOS transmission tube switch, separately read-write operation.

Description

SRAM anti-irradiation unit based on FinFET technology

Technical Field

The utility model relates to a memory technical field, concretely relates to based on FinFET technology SRAM anti-radiation unit.

Background

The high-energy particles bombard the semiconductor device, interact with the device material in the incident process, and generate a large number of electron-hole pairs through direct ionization, indirect ionization and other modes. With the collection of charge, the circuit can generate a single event upset effect when the charge amount is greater than the amount of "critical charge" required for the circuit to upset. The single event upset effect is a "soft" error caused by a change in the state of a latch or memory cell, mainly a logic level upset caused by excessive transient current, and the wrong logic state is latched.

The conventional general Static Memory Cell (Static Random Access Memory Cell) has a 6T structure as shown in fig. 1, and is hereinafter referred to as a 6T SRAM Cell. When the Q node stores '1' and the QB node stores '0', the transistors P1 and N0 are in an off state, and the drains of the two transistors are sensitive nodes with single event effect. The high-energy particles bombard any position in the sensitive area, and the single-particle upset is possibly caused.

Whether the SRAM memory cell is in a holding state or a reading state or a writing state, a built-in electric field in a sensitive area exists all the time, so that the transistor performs a charge collection process when electron-hole pairs are generated. By taking the particle bombardment on the sensitive node Q point as an example, after the high-energy particles bombard the sensitive node Q point, the charges are collected to form a transient current pulse of the drain of the N0 tube, and the N0 tube is turned on. The Q-point voltage decreases with an increase in the amount of collected charge, and when the Q-point voltage is lowered to a certain value, the transistor P0 is turned off and causes a change in logic state at Q to reach a stable state. In this process, the voltages of the Q and QB storage nodes are affected mainly by two aspects: the gate of transistor N1 is continuously charged, keeping N1 in the on state, and point QB is discharged, restoring the SRAM cell to the correct logic state. But on the other hand, due to the generation of the drain pulse current of the transistor N0, the potential of the point Q is lowered to cause the states of the two transistors P1 and N1 to change, the P0 is gradually turned off and the P1 is turned on, and the storage node QB is charged. The QB point voltage is increased and fed back to the gates of the left inverters P0, N0, causing P0 to turn off and N0 to turn on, eventually holding the voltage at the storage node Q point low, and the logic state stored by the SRAM cell flips from "1" to "0". It can be seen that the 6T SRAM Cell is ineffective against single event effects.

In a traditional planar structure transistor process, the ratio of the driving capability (Idsatp) of the PMOS to the driving capability (Idsatn) of the NMOS is about 2.5-2. To achieve the same driving capability, the SRAM Cell area must be sacrificed. Meanwhile, some error models exist in the SRAM Cell reading and writing process. One of the error mechanisms of the read operation is that the read current of the memory cell is too small, which results in too slow read speed or even no read at all. One of the error mechanisms of the write operation is that the write margin is too small, so that the write operation cannot be performed within a certain time, and the specific expression is that the states before and after the write operation are the same. With the future higher working frequency, the challenge for writing operation is larger and larger, because the clock period is short, and it is difficult to write data successfully in a short time.

The single Event upset SEU (single Event Upset) strengthening method has a plurality of strengthening methods, such as process strengthening, system level strengthening, circuit level strengthening and the like, so that the circuit obtains better SEU resistance. And (4) process reinforcement, namely, a special process is adopted to inhibit single event upset, such as an SOI (silicon on insulator) technology, an epitaxial process and the like. And the system level reinforcement technology is used for carrying out error correction and detection on the information with errors through logic decision, such as EDAC error correction coding technology. The circuit level reinforcement is reinforced by adopting a method for increasing redundancy, such as DICE technology, triple modular redundancy technology and the like.

The DICE technology has the basic idea that redundant storage states are added in storage units, and a state recovery feedback circuit is used for recovering reversed data, so that the SEU resistance is high, and the application is wide. However, the conventional DICE cell structure has the following disadvantages: 1) the anti-irradiation effect in the read-write state is easy to lose efficacy; 2) the reading operation time is not fixed and is prolonged; 3) poor ability to write; 4) the layout design of the memory cell is very difficult to make, and the area balance is very difficult.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome the problem that prior art exists, provide one kind based on FinFET technology SRAM anti-irradiation unit, not only can resist single event upset, can also improve the reading stability and the write data ability of memory cell simultaneously.

For realizing above-mentioned technical purpose, reach above-mentioned technological effect, the utility model discloses a following technical scheme realizes:

the DICE anti-radiation unit comprises a read word line RW L and a write word line W L, wherein the read word line RW L and the write word line W L are connected to corresponding levels to control PMOS transmission tube switches and separate read and write operations.

Further, the DICE radiation-resistant unit further comprises a first PMOS tube P0 to an eighth PMOS tube P7, and a first NMOS tube N0 to a sixth NMOS tube N5; wherein the content of the first and second substances,

the gates of the fifth PMOS transistor P4 to the eighth PMOS transistor P7 are connected with a write word line W L;

the drain of a fifth PMOS tube P4 is respectively connected with the drains of a first PMOS tube P0 and a first NMOS tube N0 and the gates of a second PMOS tube P1 and a fourth NMOS tube N3, the drain of a sixth PMOS tube P5 is respectively connected with the drains of a second PMOS tube P1 and a second NMOS tube N1 and the gates of a third PMOS tube P2 and a first NMOS tube N0, the drain of a seventh PMOS tube P6 is respectively connected with the drains of a third PMOS tube P2 and a third NMOS tube N2 and the gates of a fourth PMOS tube P3 and a second NMOS tube N1, and the drain of an eighth PMOS tube P7 is respectively connected with the drains of a fourth PMOS tube P3 and a fourth NMOS tube N3 and the gates of a first PMOS tube P0, a third NMOS tube N2 and a fifth NMOS tube N4;

the drain of the fifth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth NMOS transistor N5 is connected to the read word line RW L.

Furthermore, the sources of the first to fourth NMOS transistors N0 to N3 and the sixth NMOS transistor N5 are grounded, and the source of the fifth NMOS transistor N4 is connected to the read bit line RB L.

Further, the sources of the first to fourth PMOS transistors P0 to P3 are commonly connected to a power supply voltage terminal.

Further, the sources of the fifth PMOS transistor P4 and the seventh PMOS transistor P6 are commonly connected to a first bit line B L, and the sources of the sixth PMOS transistor P5 and the eighth PMOS transistor P7 are commonly connected to a second bit line B L B.

The utility model has the advantages that:

(1) the anti-irradiation unit of the utility model can improve the anti-irradiation effect;

(2) the utility model discloses an anti-irradiation unit can improve and read stability;

(3) the utility model discloses an irradiation-resistant unit can eliminate the write failure problem that causes because small-size trombone slide process deviation.

Drawings

FIG. 1 is a 6T static memory cell of the general type;

FIG. 2 is a circuit diagram of a DICE anti-radiation unit of the present invention;

fig. 3 is a diagram illustrating the writing operation of the DICE irradiation resistant unit of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

As shown in fig. 2, the DICE radiation protection unit further includes first to eighth PMOS transistors P0 to P7, and first to sixth NMOS transistors N0 to N5; wherein the content of the first and second substances,

the gates of the fifth PMOS transistor P4 to the eighth PMOS transistor P7 are connected with a write word line W L for write operation;

the drain of the fifth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth NMOS transistor N5 is connected to the read word line RW L for performing a read operation.

The sources of the first to fourth NMOS transistors N0-N3 and the sixth NMOS transistor N5 are grounded, and the source of the fifth NMOS transistor N4 is connected to the read bit line RB L.

The sources of the first to fourth PMOS transistors P0-P3 are commonly connected to a power supply voltage terminal.

The sources of the fifth PMOS transistor P4 and the seventh PMOS transistor P6 are commonly connected with a first bit line B L, the sources of the sixth PMOS transistor P5 and the eighth PMOS transistor P7 are commonly connected with a second bit line B L B, and the voltage values of the first bit line B L and the second bit line B L B are opposite.

The working process and principle of the utility model

In the present invention, as shown in fig. 2, nodes X0, X1, X2, and X3 are marked in the circuit on the graph, and it is assumed that the stored values of the nodes X0, X1, X2, and X3 are "0101", and the following MOS transistor names are abbreviated as device symbols in fig. 2.

In the embodiment of the present invention, the voltage of the read word line RW L is pulled to a high level, the voltage of the write word line W L is pulled to a low level, so the read and write operations are separated, and the read bit line RB L is precharged to a high level, since the node X3 is stored as "1", the nodes N4 and N5 and the read bit line RB L form a pull-down path, the read bit line RB L is pulled down to a low level, so the read operation is completed, taking bombardment with a negative current pulse to the storage node X1 as an example, the node X1 is changed to "0", the node N0 is turned off, the P2 is turned on, the pull-up pipe P2 pulls up the storage node X2 to "1", so the nodes P3 and N0 are turned off, the storage nodes X9 and X3 remain unchanged, they are respectively fed back to the nodes P0 and N2, the nodes X1 and X2 are pulled back to "1", "0", and the original value is restored after the irradiation reaction ends, and the storage node X6867 is connected to the gate pass transistor (i.e., the gate electrode 36874 is connected to the read-node X4.

During writing operation, due to the particularity of the MOS tube, the traditional DICE anti-radiation unit can only write '0', but the utility model discloses combine FFinFET technology characteristics, as shown in FIG. 3, adopt PMOS as the transmission tube to write '1', generally in the design, the write driver (write driver) of data can be designed to be relatively big, during writing data, drive the first bit line B L to '1', pull down the second bit line B L B to '0', because the driving capability of the data driver is stronger, the transmission tube adopts PMOS design, can charge the storage nodes X0 and X2 to '1' soon, when the nodes X0 and X2 charge to '1', the pull-down tube N1 and N3 are in the strong conducting state, can discharge the nodes X1 and X3 to '0' quickly, the time for establishing positive feedback of the storage unit is shorter, the situation of new data writing failure is difficult to occur, simultaneously because the size of the pull-down tube is all relatively larger along with the technology deviation, the novel DICE anti-radiation unit is also relatively larger.

Additionally, the utility model discloses a novel DICE anti irradiation unit, owing to the transfer line has used PMOS, PMOS is 1 than NMOS's size ratio probably: 1, PMOS and NMOS are more balanced than before, and the layout design of the memory cell is easier to achieve smaller area.

In addition, it should be noted that the terms "first", "second", "third", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The SRAM anti-radiation unit based on the FinFET process comprises a DICE anti-radiation unit formed based on the FinFET process, and is characterized in that the DICE anti-radiation unit comprises a read word line RW L and a write word line W L, wherein the read word line RW L and the write word line W L are connected to corresponding levels to control PMOS pass transistor switches and separate read and write operations.

2. The SRAM irradiation resistant unit of claim 1, further comprising a first PMOS transistor P0 through an eighth PMOS transistor P7, and a first NMOS transistor N0 through a sixth NMOS transistor N5; wherein the content of the first and second substances,

3. The SRAM irradiation resisting unit based on FinFET process of claim 2, wherein the sources of the first N0 through fourth N3 and sixth N5 NMOS transistors are grounded, and the source of the fifth N4 NMOS transistor is connected to a read bit line RB L.

4. The SRAM irradiation resistant cell of claim 2, wherein sources of the first through fourth PMOS transistors P0-P3 are commonly connected to a power supply voltage terminal.

5. The SRAM irradiation resisting unit of claim 2 or 4, wherein sources of the fifth PMOS transistor P4 and the seventh PMOS transistor P6 are commonly connected to a first bit line B L, and sources of the sixth PMOS transistor P5 and the eighth PMOS transistor P7 are commonly connected to a second bit line B L B.