US8181074B2 - Soft error recoverable storage element and soft error protection technique - Google Patents
Soft error recoverable storage element and soft error protection technique Download PDFInfo
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- US8181074B2 US8181074B2 US11/961,952 US96195207A US8181074B2 US 8181074 B2 US8181074 B2 US 8181074B2 US 96195207 A US96195207 A US 96195207A US 8181074 B2 US8181074 B2 US 8181074B2
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- 238000000034 method Methods 0.000 title description 7
- 230000008859 change Effects 0.000 claims abstract description 10
- 230000005540 biological transmission Effects 0.000 claims description 13
- 230000001902 propagating effect Effects 0.000 claims description 4
- 230000003068 static effect Effects 0.000 abstract description 3
- 239000002245 particle Substances 0.000 description 25
- 238000011084 recovery Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000000644 propagated effect Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
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- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
Definitions
- the present invention relates to integrated circuits.
- the present invention relates to high performance flip-flops with a soft error recoverable storage element.
- Soft errors may be caused by package radioactive decay that results in the emission of an alpha particle. Soft errors may also be caused by neutrons. A neutron may undergo neutron capture by a nucleus of an atom, producing an unstable isotope that in turn may cause a soft error when the isotope decays producing an alpha particle.
- a soft error may occur when an alpha particle hits a transistor device, transferring a charge to a sensitive node of the device that alters a data value stored in the device.
- a soft error may result in improper operation.
- a soft error may alter the program code stored in the memory of a microprocessor resulting in improper microprocessor operation. Such an error may be referred to as a soft error because the affected program code may be rewritten to restore proper microprocessor operation.
- a circuit may be prone to soft errors when its critical charge value, the minimum electron charge disturbance needed to flip its logic state, becomes too low.
- a circuit's critical charge value may be a function of capacitance and voltage.
- a circuit with a higher critical charge value may result in less sensitivity to soft errors, but also may result in a slower device having higher power dissipation. As device geometries continue to shrink and supply voltages continue to decrease for performance reasons, devices may become more prone to soft errors.
- Soft errors may be a serious issue for memory cells because their critical charges may be very small. Error correcting codes may be implemented in memory modules to reduce soft errors. As integrated circuit processes continue to shrink feature sizes, the critical charge for logic circuits, such as static combinational logic and sequential elements, may become small enough to be less than the charges generated by alpha particles. In microprocessors, network processors and network storage controllers, the overall soft error rate for a state of the art design may be on the order of 40% for unprotected SRAM, 11% for combinational logic and 49% for sequential elements. Because the soft error rate of sequential elements, such as latches and flip-flops, may exceed that of unprotected SRAMs, sequential elements with reduced soft error rates may be needed.
- FIG. 1 depicts a storage element 10 employing a conventional configuration of back-to-back inverters 12 , 14 as a storage node in a sequential element such as a latch or flip-flop, also sometimes referred to as a “keeper.”
- the inverters 12 , 14 may maintain the voltage level on a storage node 16 .
- FIG. 2 depicts a conventional CMOS implementation of the storage element 10 of FIG. 1 .
- Each inverter 12 , 14 may include a PMOS transistor 18 , 20 , respectively, and an NMOS transistor 22 , 24 , respectively.
- Node 26 may initially be in a logic one state with the NMOS transistor 22 on and the PMOS transistor 18 off.
- An alpha particle hitting the node 26 around the active region of NMOS transistor 24 may drain the charge stored on the node 26 to a supply node Vss, causing the node 26 to flip to the opposite logic state, a logic zero. This causes the NMOS transistor 22 to turn off and PMOS transistor 18 to turn on, flipping the logic state of the following output node from a logic zero to a logic one. Thus, the stored data in the storage element 10 is altered by the alpha particle hit. This change of logic state is a soft error.
- the node 26 may also be in a logic zero state with the PMOS transistor 18 on and the NMOS transistor 22 off.
- An alpha particle hitting the node 26 around the active region of PMOS transistor 20 can source the charge from a supply node vdd to the node 26 and cause the node to flip from a logic zero to a logic one.
- the stored data in the storage element 10 is altered by the alpha particle hit.
- FIG. 3 depicts a latch 30 employing a keeper-type storage element 32 , which may be implemented by back-to-back inverters, for example.
- a transmission gate 34 of the latch 30 may become transparent. While the transmission gate 34 is transparent, the upstream combinational logic may drive the D input of the latch 30 and may write the corresponding logic value into the storage element 32 .
- any soft error that affects the transistors inside the latch 30 may have a negligible effect because the correct logic value is being driven at the D input of the latch.
- the clock input of the latch 30 is at a logic zero, i.e., when the latch is holding a logic state, a soft error may flip the latch state.
- the latch 30 may be more susceptible to soft errors when the storage element 32 of the latch is holding a logic state.
- the storage element includes a plurality of inverting elements configured in a loop.
- the storage element further includes a plurality of gating elements operably coupled to the plurality of inverters.
- Each gating element includes a control node operably coupled to the output of the next inverter in the loop. When a gating element's control node is at a logic zero value, the corresponding inverting element is unable to drive its output to a logic zero state.
- the storage element includes four inverters and four gating devices.
- Each inverter includes a switching element operable to drive the inverter output to a logic zero when the inverter input is a logic one and another switching element operable to driver the inverter output to a logic one when the inverter input is a logic zero.
- a gating device is operably coupled to an inverter and includes a control node operably coupled to the output node of the next inverter in the loop. The gating device prevents the inverter from driving its output node to a logic zero value when the control node is at a logic zero value.
- FIG. 1 depicts storage element with back to back inverters.
- FIG. 3 depicts a latch employing the storage element of FIG. 1 .
- FIG. 5 depicts a circuit diagram of a second embodiment of a soft error recoverable storage element.
- one aspect of the present invention may involve a soft error recoverable storage element that may be used as a storage element in a latch or memory cell to provide soft error recovery.
- an interlocking four inverter loop 42 may be employed as a soft error recoverable storage element 40 , as depicted in FIG. 4 .
- a logic state may be stored in the nodes S 1 , S 2 , S 1 b and S 2 b (note that S 1 b and S 2 b store the complementary values of S 1 and S 2 , respectively).
- Internal feedback circuitry including gating elements 52 , 54 , 56 , 58 enable the storage element 40 to recover from a soft error.
- Each inverter 44 , 46 , 48 , 50 of the storage element 40 may include a respective PMOS transistor 60 a , 60 b , 60 c , 60 d and a respective NMOS transistor 61 a , 61 b , 61 c , 61 d .
- the NMOS transistors 61 a , 61 b , 61 c , 61 d may be gated by respective transistors 52 , 54 , 56 , 58 controlled by respective nodes S 2 , S 2 b , S 1 , S 1 b .
- nodes S 1 and S 2 generally are at the same logic state and nodes S 1 b and S 2 b generally are at the same logic state.
- a suffix b on a signal name stands for bar, meaning that the signal is inverted.
- Inverter 44 may include a PMOS transistor 60 a and a NMOS transistor 61 a .
- the source of the PMOS transistor 60 a is connected to supply node Vdd.
- the gate of PMOS transistor 60 a is connected to the gate of the NMOS transistor 61 a which in turn is connected to input node S 1 , which is the input of inverter 44 .
- the drain of the PMOS transistor 60 a is connected to the drain of the NMOS transistor 61 a which in turn is connected to node S 1 b .
- the source of the NMOS transistor 61 a is connected to the drain of the NMOS transistor 52 .
- the source of the NMOS transistor 52 is connected to a power node Vss.
- the gate of NMOS transistor 52 is connected to node S 2 .
- Inverter 48 may include a PMOS transistor 60 c and a NMOS transistor 61 c .
- the source of the PMOS transistor 60 c is connected to supply node Vdd.
- the gate of PMOS transistor 60 c is connected to the gate of the NMOS transistor 61 c which in turn is connected to node S 2 , which is the input of inverter 48 .
- the drain of the PMOS transistor 60 c is connected to the drain of the NMOS transistor 61 c which in turn is connected to node S 2 b .
- the source of the NMOS transistor 61 c is connected to the drain of the NMOS transistor 56 .
- the source of the NMOS transistor 56 is connected to a power node Vss.
- the gate of NMOS transistor 56 is connected to node S 1 .
- Inverter 50 may include a PMOS transistor 60 d and a NMOS transistor 61 d .
- the source of the PMOS transistor 60 d is connected to supply node Vdd.
- the gate of PMOS transistor 60 d is connected to the gate of the NMOS transistor 61 d which in turn is connected to node S 2 b , which is the input of inverter 50 .
- the drain of the PMOS transistor 60 d is connected to the drain of the NMOS transistor 61 d which in turn is connected to node S 1 .
- the source of the NMOS transistor 61 d is connected to the drain of the NMOS transistor 58 .
- the source of the NMOS transistor 58 is connected to a power node Vss.
- the gate of NMOS transistor 58 is connected to node S 1 b.
- a soft error occurs at a node of the inverter loop
- that node may be in one of two possible states: a logic one state or a logic zero state. If the node is in a logic one state, the alpha particle causes the node to lose charge and transition to a logic zero state. This logic zero will propagate to the next node through the corresponding PMOS device of that node's inverter which is not gated by the feedback circuit. The PMOS device may drive that node to a logic one. However, the soft error does not propagate further because the NMOS device of that node is gated by the feedback circuit and prevents a change in state. The remaining two nodes of the storage element retain the original stored data. Because the alpha particle hit does not change the state of the whole inverter loop, the loop drives the two changed nodes back to their original stored data states.
- the node may be charged to a logic one state.
- This change in data state may not be propagated to the next node in the loop because the NMOS device of the next inverter in the loop is gated by the feedback circuit.
- the other three nodes of the inverter loop retain their original data states.
- the loop drives the changed node back to its original stored data state.
- a soft error may flip the state in one or two nodes of the loop but does not flip the states of the entire loop.
- the loop recovers its original data state to maintain the correct stored data value.
- the glitch may not be propagated to the output of inverter 48 .
- the gate of transistor 56 is at a logic zero because it is connected to the output of inverter 50 .
- gating transistor 56 for inverter 48 , is opaque.
- transistor 61 c is blocked from pulling the output of the inverter 48 to a logic zero.
- the output of inverter 50 (at a logic zero state) is connected to the input of inverter 44 . This feedback results in the output of inverter 44 recovering to its original logic one output state.
- the alpha particle may instead hit the inverter 46 causing its output to temporarily transition to a logic one state.
- the gating transistor 56 connected in series with the NMOS transistor 61 c of the inverter 48 , is opaque because its gate is connected to the output of inverter 50 (which is at a logic zero state).
- the NMOS transistor 61 c is blocked from driving the output of the inverter 48 to a logic zero state.
- the outputs of inverters 48 , 50 , 44 retain their original stored data values of one, zero, one, respectively. The inverter loop, thus results in the output of inverter 46 recovering to its original logic zero state.
- the 12 transistor half gater storage element 40 may provide soft error recovery from an alpha particle hit on any one of the four nodes S 1 , S 1 b , S 2 , S 2 b of the storage element.
- the storage element 40 may have a 50% chance of soft error recovery when two adjacent nodes of the storage element are simultaneously altered. For example, if node S 1 is at a logic one and node S 1 b is at a logic zero state, simultaneous alpha particle hits may flip S 1 from a logic one to a logic zero and S 1 b from a logic zero to a logic one. Because node S 2 is gated by S 2 b , still at a logic zero, the error propagation may end at node S 1 b . Eventually the original node states may be recovered.
- the transistor pairs 61 a and 52 , 61 b and 54 , 61 c and 56 , 61 d and 58 may each form an NMOS stack, the impact on chip area is generally small.
- technology allowed minimum device sizes for the NMOS transistors and the PMOS transistors to maintain a beta-ratio of 2 may be employed in the 12 transistor storage element design.
- Such a design may achieve a total transistor sizing that is about double the normal back-to-back inverter storage element, even though the transistor count increases from 4 to 12.
- the circuit depicted in FIG. 5 may be referred to as a full gater storage element 70 .
- the full gater storage element 70 may have a faster recovery time from a single alpha particle hit and be more resistant to two alpha particle hits as described below.
- the soft error recoverable storage element 40 may have minimal impact to circuit performance as compared to prior art approaches to soft-error hardening employing extra evaluation logic that may affect timing margins.
- the storage element 40 may present an additional capacitive load on the D input of the latch 71 due to the additional input capacitance of inverter 86 .
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US11/961,952 US8181074B2 (en) | 2007-12-20 | 2007-12-20 | Soft error recoverable storage element and soft error protection technique |
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US9397642B2 (en) * | 2014-12-08 | 2016-07-19 | SK Hynix Inc. | Latch circuit |
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Publication number | Priority date | Publication date | Assignee | Title |
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US7782107B2 (en) * | 2008-06-30 | 2010-08-24 | Oracle America, Inc. | Method and apparatus for an event tolerant storage circuit |
US8837203B2 (en) * | 2011-05-19 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
CN115001481A (en) * | 2022-05-31 | 2022-09-02 | 安徽理工大学 | Low-overhead radiation-resistant reinforced latch capable of tolerating three-node overturning self-recovery |
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US20070133261A1 (en) * | 2004-08-10 | 2007-06-14 | Fujitsu Limited | Semiconductor storage device |
US7474116B2 (en) * | 2006-05-18 | 2009-01-06 | Fujitsu Limited | Latch circuit |
US7613067B2 (en) * | 2006-10-20 | 2009-11-03 | Manoj Sachdev | Soft error robust static random access memory cells |
US7923762B2 (en) * | 2008-03-07 | 2011-04-12 | Sony Corporation | Semiconductor device and method of manufacturing the same |
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2007
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US7023235B2 (en) * | 2003-12-12 | 2006-04-04 | Universities Research Association, Inc. | Redundant single event upset supression system |
US20070133261A1 (en) * | 2004-08-10 | 2007-06-14 | Fujitsu Limited | Semiconductor storage device |
US7474116B2 (en) * | 2006-05-18 | 2009-01-06 | Fujitsu Limited | Latch circuit |
US7613067B2 (en) * | 2006-10-20 | 2009-11-03 | Manoj Sachdev | Soft error robust static random access memory cells |
US7923762B2 (en) * | 2008-03-07 | 2011-04-12 | Sony Corporation | Semiconductor device and method of manufacturing the same |
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Author Unknown, "Soft Error", Wikipedia, http://en.wikipedia.org/wiki/Soft-error, 6 pages, at least as early as Aug. 3, 2007. |
Heijmen et al., "A Comparative Study on the Soft-Error Rate of Flip-Flops from 90-nm Production Libraries", IEEE, 44th Annual International Reliability Physics Symposium, San Jose, California, pp. 204-211, 2006. |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US9397642B2 (en) * | 2014-12-08 | 2016-07-19 | SK Hynix Inc. | Latch circuit |
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