CN115273931A - RHBD-14T radiation-resistant SRAM storage unit, chip and module - Google Patents

Abstract

The invention relates to an RHBD-14T radiation-resistant SRAM storage unit, a chip and a module. The RHBD-14T radiation-resistant SRAM storage unit based on the source isolation technology comprises PMOS transistors P1-6 and NMOS transistors N0-7; p4 and P3, P2 and P5 are cross-coupled, two main storage nodes Q and QN are respectively connected with bit lines BL and BLB through N4 and N5, two redundant storage nodes S0 and S1 are respectively connected with bit lines BL and BLB through N6 and N7, N4-N7 are controlled by a word line WL, the source of P1 and the source of P6 are connected with VDD in common, and the source of N0, the source of N1, the source of N3 and the source of N2 are connected with VDD in common. According to the invention, the source isolation technology is adopted when the space particles bombard the sensitive node, so that only weak voltage pulse is generated, the states of other transistors are not influenced, and the SEU resistance of the SRAM storage unit is improved.

Description

RHBD-14T radiation-resistant SRAM storage unit, chip and module

Technical Field

The invention relates to the technical field of static random access memory unit circuits, in particular to an RHBD-14T radiation-resistant SRAM memory unit, a chip and a module based on a source isolation technology.

Background

As technology has evolved, light weight satellites have begun to be built to reduce manufacturing and maintenance costs. Due to the size limitations of lightweight satellites, they require a high density of storage units. Static Random Access Memory (SRAM) cells have a high packing density, improving the logic performance of digital data processing and satellite control systems, and are an ideal choice for achieving this goal. Space contains energetic charged particles. When a particle strikes a logic circuit, electron-hole pairs are generated. Due to the electric field, these electron-hole pairs are separated and collected at the sensitive node, and the accumulated charges generate a transient voltage pulse. If the amplitude of the pulse exceeds the switching threshold of the logic circuit, the stored data may be altered, resulting in a Single Event Upset (SEU) or software error.

Disclosure of Invention

Based on this, it is necessary to provide the RHBD-14T radiation-resistant SRAM memory cell, chip, module based on the source isolation technology for the problem that the probability of single particle impact affecting the cell increases, thereby causing cell disturbance.

In order to achieve the purpose, the invention adopts the following technical scheme:

the RHBD-14T radiation-resistant SRAM memory cell based on the source isolation technology comprises:

a PMOS transistor P1;

the source electrode of the PMOS transistor P2 and the drain electrode of the PMOS transistor P2 are electrically connected with the drain electrode of the PMOS transistor P1;

the source electrodes of the PMOS transistors P3 and P3 are electrically connected with the drain electrode of the P1 and the source electrode of the P2;

the grid electrodes of the PMOS transistors P4 and P4 are electrically connected with the drain electrode of the PMOS transistor P3;

the source electrode of the PMOS transistor P5 is electrically connected with the source electrode of the P4, and the grid electrode of the P5 is electrically connected with the drain electrode of the P2;

the source electrode of the PMOS transistor P6 is electrically connected with the source electrode of P1, the drain electrode of P6 is electrically connected with the source electrode of P5 and the source electrode of P4, and the grid electrode of P6 is electrically connected with the grid electrode of P5 and the drain electrode of P2;

the drain electrode of the NMOS transistor N0, N0 is electrically connected with the drain electrode of the P5, and the grid electrode of the N0 is electrically connected with the drain electrode of the P3;

the drain electrode of the NMOS transistor N1 and the drain electrode of the NMOS transistor N1 are electrically connected with the drain electrode of the NMOS transistor P4, the grid electrode of the NMOS transistor N1 is electrically connected with the grid electrode of the NMOS transistor P5, the grid electrode of the NMOS transistor P6 and the drain electrode of the NMOS transistor P2, and the source electrode of the NMOS transistor N1 is electrically connected with the source electrode of the NMOS transistor N0;

the drain electrode of the NMOS transistor N2 and the drain electrode of the N2 are electrically connected, the grid electrode of the N2 is electrically connected with the drain electrode of the P4 and the drain electrode of the N1, and the source electrode of the N2 is electrically connected with the source electrode of the N1 and the source electrode of the N0;

the drain electrode of the NMOS transistor N3 and N3 is electrically connected with the drain electrode of P3, the grid electrode of P4, the grid electrode of N0 and the drain electrode of N5, the grid electrode of N3 is electrically connected with the grid electrode of P1, the grid electrode of P2, the drain electrode of P5 and the drain electrode of N0, and the source electrode of N3 is electrically connected with the source electrode of N2, the source electrode of N1 and the source electrode of N0;

the drain electrode of the NMOS transistor N4 and N4 is electrically connected with the drain electrode of the N1, the grid electrode of the N4 is electrically connected with a word line WL, and the source electrode of the N4 is electrically connected with a bit line BL;

the drain electrode of the NMOS transistor N5 and the drain electrode of the N5 are electrically connected with the drain electrode of the N3, the grid electrode of the N5 is electrically connected with a word line WL, and the N5 is electrically connected with a bit line BLB;

the drain electrode of the NMOS transistor N6, N6 is electrically connected with the drain electrode of N0, the grid electrode of N6 is electrically connected with a word line WL, and the source electrode of N6 is electrically connected with a bit line BL;

the drain electrode of the NMOS transistor N7 and the drain electrode of the N7 are electrically connected with the drain electrode of the N2, the grid electrode of the N7 is electrically connected with a word line WL, and the N7 is electrically connected with a bit line BLB;

transistors P4 and P3, P2 and P5 are cross-coupled, P1 and P6 are used as pull-up tubes, N0, N1, N2 and N3 are used as pull-down tubes, two main storage nodes Q and QN are respectively connected with bit lines BL and BLB through N4 and N5, two redundant storage nodes S0 and S1 are respectively connected with bit lines BL and BLB through N6 and N7, N4, N5, N6 and N7 are controlled by a word line WL, the source electrode of P1 and the source electrode of P6 are connected with VDD in common, and the source electrode of N0, the source electrode of N1, the source electrode of N3 and the source electrode of N2 are connected with ground in common.

Further, the gate lengths of the transistors N0 to N7 and the transistors P1 to P6 are all 65nm, wherein the gate widths of the transistors P1 to P6 are 140nm, the gate widths of the transistors N0 to N3 are 280nm, and the gate widths of the transistors N4 to N7 are 140nm.

In one embodiment, when the RHBD-14T radiation-resistant SRAM memory cell is in a holding stage, the bit lines BL and BLB are precharged to a high level, the word line WL is at a low level, and the inside of the cell is kept in an initial state and does not work.

In one embodiment, when the RHBD-14T radiation-resistant SRAM memory cell is in a read data phase, the bit lines BL and BLB are precharged to a high level, the word line WL is at a high level, and the transistors N4-N7 are opened.

Further, if the data stored in the RHBD-14T radiation-resistant SRAM memory cell is '0', then "Q = S1=0, QN = S0=1"; bit line BL passes through discharge path 1: transistors N4, N1 and discharge path 2: the transistors N6 and N0 discharge to the ground, and a voltage difference is generated between the bit lines, and data is read by the sense amplifier.

Further, if the data stored in the RHBD-14T radiation-resistant SRAM memory cell is '1', then "Q = S1=1, QN = S0=0"; bit line BLB passes through discharge path 1: transistors N5, N3 and discharge path 2: the transistors N7 and N2 discharge to the ground, and a voltage difference is generated between the bit lines, and data is read by the sense amplifier.

In one embodiment, when the RHBD-14T radiation-resistant SRAM memory cell is in the data writing phase, the word line WL is at high level, and if the bit line BL is at high level and the bit line BLB is at low level, '1' is written to the storage node Q and the storage node S1 through the transistors N4 and N6, respectively.

Further, when the RHBD-14T radiation-resistant SRAM memory cell is in a data writing phase, the word line WL is at a high level, and if the bit line BL is at a low level and the bit line BLB is at a high level, a '0' is written into the storage node QN and the storage node S0 through the transistors N5 and N7, respectively.

The invention also comprises an RHBD-14T irradiation-resistant SRAM memory chip based on the source isolation technology, which is formed by adopting the circuit package of the RHBD-14T irradiation-resistant SRAM memory unit based on the source isolation technology, wherein the pins of the RHBD-14T irradiation-resistant SRAM memory chip based on the source isolation technology comprise:

a first pin electrically connected to gates of the transistors N4 to N7 through a word line WL;

a second pin electrically connected to the sources of the transistors N4 and N6 via a bit line BL;

and a third pin electrically connected to the sources of transistors N5, N7 through bit line BLB.

The invention also comprises a source isolation technology-based RHBD-14T irradiation-resistant SRAM storage module, which adopts the circuit of the source isolation technology-based RHBD-14T irradiation-resistant SRAM storage unit, and the storage module comprises:

the grids of the transistors N4 to N7 are electrically connected with a word line WL, so that a first connection end is led out;

the source electrodes of the transistors N4 and N6 are electrically connected with a bit line BL, so that a second connection end is led out;

the sources of the transistors N5, N7 are electrically connected to the bit line BLB, thereby leading to a third connection terminal.

The technical scheme provided by the invention has the following beneficial effects:

according to the invention, the source isolation technology is adopted when the space particles bombard the sensitive node, so that only weak voltage pulses are generated, and the states of other transistors are not influenced, thereby improving the SEU resistance of the SRAM storage unit and improving the stability of the SRAM storage unit.

Drawings

Fig. 1 is a schematic structural diagram of an SEA14T circuit in the prior art according to the present invention;

FIG. 2 is a schematic diagram of a prior art QUATRO10T circuit according to the present invention;

FIG. 3 is a schematic diagram of an S4P8N circuit according to the prior art;

FIG. 4 is a schematic diagram of a prior art QUCCE12T circuit according to the present invention;

FIG. 5 is a schematic diagram of a prior art RSP14T circuit according to the present invention;

FIG. 6 is a schematic circuit structure diagram of an RHBD-14T radiation-resistant SRAM storage unit based on a source isolation technology;

FIG. 7 is a simulation diagram of timing waveforms based on the memory cell of FIG. 6;

FIG. 8 is a simulation diagram of transient waveforms injected by dual-exponential current source pulses at different nodes at different times based on the memory cell of FIG. 6;

FIG. 9 is a comparison graph of HSNM, RSNM, WSNM based on the memory cell of FIG. 6 and a prior art SRAM cell circuit;

FIG. 10 is a simulation diagram showing the result of closing the tube based on the three-dimensional TCAD blending simulation true simulation particle bombardment anti-radiation unit of FIG. 6;

FIG. 11 is a schematic structural diagram of an RHBD-14T radiation-resistant SRAM memory chip based on the source isolation technology of FIG. 6.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to improve the unit's ability to resist SEU, the prior art mainly includes the following solutions: FIG. 1 illustrates an SEA14T circuit that employs polarity hardening techniques, which, while reducing the number of sensitive nodes, results in greater read delay and lower HSNM and RSNM values; FIG. 2 is a QUATRO10T circuit that has better SEU resistance than the conventional six-pipe cell structure, but the cell has poor write capability and it maintains a poor noise margin HSNM and a poor read static noise margin RSNM; FIG. 3 shows an S4P8N circuit, which has a large area and a small noise margin HSNM, and has poor stability; FIG. 4 shows a QUCCE12T circuit that is resistant to all single-node flips and has a high read static noise margin RSNM but a small critical charge; fig. 5 shows an RSP14T circuit, which has a small critical charge and a complicated circuit structure, and is not easy to integrate.

Aiming at the problem of unit disturbance caused by increased SEU probability of a single particle impact influence unit, the embodiment provides the RHBD-14T irradiation-resistant SRAM storage unit based on the source isolation technology, so that the source isolation technology is adopted when space particles bombard sensitive nodes, only weak voltage pulses are generated, the states of other transistors are not influenced, and the SEU resistance of the SRAM storage unit is improved.

As shown in FIG. 6, the present embodiment provides a RHBD-14T radiation-resistant SRAM memory cell based on the source isolation technology, which mainly comprises six PMOS transistors and eight NMOS transistors; the six PMOS transistors are sequentially marked as P1-P6, and the eight NMOS transistors are sequentially marked as N0-N7; p1 and P6 are used as pull-up tubes, P4 and P3, P2 and P5 are in cross coupling, and N0-N3 are used as pull-down tubes; two main storage nodes Q and QN are respectively connected with bit lines BL and BLB through N4 and N5, and two redundant storage nodes S0 and S1 are respectively connected with bit lines BL and BLB through N6 and N7; where the tubes N4-N7 are controlled by word lines WL.

The bit line BL is electrically connected with the source electrodes of the transmission tubes N4 and N6; bit line BLB is electrically connected to the sources of transistors N5 and N7; the word line WL is electrically connected to the gates of the pass transistors N4, N5, N6, and N7; the drain electrode of the transmission transistor N4 is electrically connected with the drain electrode of the NMOS transistor N1; the drain of the transfer transistor N6 is electrically connected to the drain of the NMOS transistor N0; the drain electrode of the transmission transistor N5 is electrically connected with the drain electrode of the NMOS transistor N3; the drain of the transfer transistor N7 is electrically connected to the drain of the NMOS transistor N2; VDD is electrically connected with the sources of PMOS transistors P6 and P1; the sources of the PMOS transistors P5 and P4 and the sources of the PMOS transistors P3 and P2 are respectively connected with the drains of the PMOS transistors P6 and P1; the drains of the PMOS transistors P5, P4, P3 and P2 are respectively connected with the drains of the NMOS transistors N0, N1, N3 and N2; the sources of N0, N1, N3 and N2 are connected to ground.

The specific connection mode is as follows: the drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P3 and the source of the PMOS transistor P2, and the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N3, and the gate of the PMOS transistor P2 is electrically connected to the drain of the PMOS transistor P5 and the drain of the NMOS transistor N0; the drain electrode of the PMOS transistor P2 is electrically connected with the drain electrode of the NMOS transistor N2; the source electrode of the PMOS transistor P2 is electrically connected with the drain electrode of the PMOS transistor P1 and the source electrode of the PMOS transistor P3; the grid electrode of the PMOS transistor P2 is electrically connected with the drain electrode of the PMOS transistor P5 and the drain electrode of the NMOS transistor N0; the drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N3 and the gate of the PMOS transistor P4, and is electrically connected to the gate of the NMOS transistor N0 and to the drain of the NMOS transistor N5, the source of the PMOS transistor P3 is connected to the drain of P1 and the source of the PMOS transistor P2 is electrically connected; the grid electrode of the PMOS transistor P3 is electrically connected with the drain electrode of the NMOS transistor N1 and the drain electrode of the PMOS transistor P4; the drain electrode of the PMOS transistor P4 is electrically connected with the drain electrode of the NMOS transistor N1; the source of PMOS transistor P4 is connected to the drain of P6 and the source of PMOS transistor P5 is electrically connected; the grid electrode of the PMOS transistor P4 is electrically connected with the drain electrode of the NMOS transistor N3 and the drain electrode of the PMOS transistor P3; the drain electrode of the PMOS transistor P5 is electrically connected with the drain electrode of the NMOS transistor N0, the grid electrode of the PMOS transistor P1 is electrically connected with the grid electrode of the NMOS transistor N3, the grid electrode of the PMOS transistor P2 is electrically connected with the drain electrode of the NMOS transistor N6; the source electrode of the PMOS transistor P5 is electrically connected with the drain electrode of the PMOS transistor P6 and the source electrode of the PMOS transistor P4; the grid electrode of the PMOS transistor P5 is electrically connected with the drain electrode of the PMOS transistor P2 and the drain electrode of the NMOS transistor N2; the drain of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P5 and the source of the PMOS transistor P4, and the gate of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N1, and the gate of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2.

The drain electrode of the NMOS transistor N0 is electrically connected with the drain electrode of the PMOS transistor P5, and the grid electrode of the NMOS transistor N0 is electrically connected with the drain electrode of the PMOS transistor P3; the drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P4 and the gate of the NMOS transistor N2, and the gate of the NMOS transistor N1 is electrically connected to the gate of the PMOS transistor P5, the gate of the PMOS transistor P6, the drain of the PMOS transistor P2, and the drain of the NMOS transistor N2; the drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P2, the gate of the NMOS transistor N1 is electrically connected to the gate of the PMOS transistor P5 and the gate of the PMOS transistor P6, and the gate of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P4 and the drain of the NMOS transistor N1; the drain of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P3, and the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N0 and the drain of the NMOS transistor N5, the gate of the NMOS transistor N3 is electrically connected to the gate of the PMOS transistor P1, the gate of the PMOS transistor P2 is electrically connected to the drain of the PMOS transistor P5, and the drain of the NMOS transistor N0; the drain electrode of the NMOS transistor N4 and the drain electrode of the N4 are electrically connected with the drain electrode of the N1, the grid electrode of the N4 is electrically connected with a word line WL, and the source electrode of the N4 is electrically connected with a bit line BL; the drains of the NMOS transistors N5 and N5 are electrically connected with the drain of the NMOS transistor N3, the grid of the NMOS transistor N5 is electrically connected with the word line WL, and the NMOS transistor N5 is electrically connected with the bit line BLB; the drain electrode of the NMOS transistor N6, N6 is electrically connected with the drain electrode of N0, the grid electrode of N6 is electrically connected with a word line WL, and the source electrode of N6 is electrically connected with a bit line BL; the drains of the NMOS transistors N7, N7 are electrically connected to the drain of N2, the gate of N7 is electrically connected to the word line WL, and N7 is electrically connected to the bit line BLB.

The gate length of all MOS transistors is 65nm, wherein the gate width of the PMOS transistors is 140nm, the gate width of the transistors N0, N1, N2 and N3 is 280nm, and the gate width of the transistors N4, N5, N6 and N7 is 140nm.

The RHBD-14T radiation-resistant SRAM memory cell has the following principle: in the holding stage, the bit lines BL and BLB are precharged to high level, the word line WL is low level, the circuit is maintained in an initial state, and the circuit does not operate. When in the data reading stage, the bit lines BL and BLB are precharged to high level, the word line WL is high level, and the transmission transistors N4, N5, N6 and N7 are turned on; if the cell circuit stores data of '0', Q = S1=0, QN = S0=1"; then BL goes through discharge path 1: transistors N4 and N1, and discharge path 2: the transistors N6 and N0 discharge to the ground, so that the bit lines generate a voltage difference, and then data is read out through the sensitive amplifier; if the cell circuit stores data of '1', then "Q = S1=1, QN = S0=0" and BLB passes through discharge path 1: transistors N5 and N3, and discharge path 2: transistors N7, N2 discharge to ground, causing the bit lines to develop a voltage difference, which is then read out by the sense amplifier. In the data writing stage, the word line WL is at high level, and if BL is at high level and BLB is at low level, '1' is written to the storage node Q point and S1 point through the pass transistors N4 and N6, respectively; if BL is low and BLB is high, '0' is written to the storage node QN and S0 points through the pass transistors N5 and N7, respectively.

When only considering the improvement of the anti-irradiation performance of the circuit structure, if the storage node of the circuit is bombarded by particles, because the circuit node is composed of two PMOS transistors to form a pull-up path, according to the source isolation principle, the parasitic bipolar amplification effect in the PMOS transistors is weakened by connecting one PMOS transistor in series through the pull-up path, namely when space particles bombard sensitive nodes, the node storing '0' only generates a weak voltage pulse of '0-1' due to the adoption of the source isolation technology, and the state of other transistors cannot be influenced by the existence of gate capacitance, so that the SEU resistance of the circuit is improved, and the other two nodes storing '1' can recover the stored value by depending on the circuit structure of the storage unit when being overturned by single particle bombardment.

Under the simulation conditions of Corner: TT; temperature:27 ℃; VDD: FIG. 7 shows a waveform diagram of the RHBD-14T radiation-resistant SRAM memory cell under 1.2V; the simulation graph of the transient waveform of the RHBD-14T irradiation-resistant SRAM storage unit at different times and different nodes when the double-exponential current source pulse is injected is shown in FIG. 8; the comparison of HSNM, RSNM and WSNM of the RHBD-14T radiation-resistant SRAM memory cell compared with the SRAM cell circuit in the prior art is shown in FIG. 9; the results of tube closing in the three-dimensional TCAD phantom true simulation of particle bombardment RHBD-14T radiation resistant SRAM memory cell are shown in fig. 10, where node Q = S1=1, QN = S0=0, let value is 80.

The simulation conditions are consistent with those described above, and the simulation comparison table of the read-write time and the power consumption of the RHBD-14T radiation-resistant SRAM memory cell provided in this embodiment and the SRAM cell circuit in the prior art is shown in the following table:

read-write time and power consumption simulation comparison table

Unit cell	Read delay (ps)	Write latency (ps)	Power consumption (μ W)
				SEA14T	100.44	39.7	15.15
Quatro	119.2	388.02	7.43
				S4P8N	82.4	34.4	7.73
QUCCE12T	44.61	34.7	15.2
				RSP14T	110.38	31.9	15.12
RHBD-14T	54.7	32.0	15.053

The simulation conditions are consistent with those described above, and the critical charge comparison table of the RHBD-14T radiation-resistant SRAM memory cell provided in this embodiment and the SRAM cell circuit in the prior art is shown as follows:

critical charge comparison table

Circuit name	Critical charge (fC)
		SEA14T	>80
Quatro	19.1
		S4P8N	32.61
QUCCE12T	31.51
		RSP14T	18.75
RHBD-14T	>80

Therefore, the anti-overturning performance of the RHBD-14T radiation-resistant SRAM memory cell to the SEU is verified through SPICE simulation and 3D technology computer-aided design mixed mode simulation. Two pull-up PMOS transistors are shared and overlapped in internal nodes Q \ QN and S0\ S1, so that the stability of the SRAM storage unit is improved, and the single event upset resistance of the unit is improved.

As shown in fig. 11, on the basis of the foregoing RHBD-14T radiation-resistant SRAM memory cell based on the source isolation technology, there is further provided a RHBD-14T radiation-resistant SRAM memory chip based on the source isolation technology, where the chip is packaged by a circuit of the RHBD-14T radiation-resistant SRAM memory cell based on the source isolation technology, and a pin of the RHBD-14T radiation-resistant SRAM memory cell includes: a first pin electrically connected to gates of the transistors N4 to N7 through a word line WL; a second pin electrically connected to the sources of the transistors N4 and N6 via a bit line BL; and a third pin electrically connected to the sources of transistors N5, N7 through bit line BLB.

The mode of packaging into a chip is easier for popularization and application of the RHBD-14T irradiation-resistant SRAM storage unit, and is convenient for technicians in the field to quickly use the RHBD-14T irradiation-resistant SRAM storage unit, and only the pins of the chip need to be connected through lines according to the specification.

On the basis of the RHBD-14T irradiation-resistant SRAM storage unit based on the source isolation technology, an RHBD-14T irradiation-resistant SRAM storage module based on the source isolation technology is further provided, and the storage module comprises: the grids of the transistors N4 to N7 are electrically connected with a word line WL, so that a first connection end is led out; the source electrodes of the transistors N4 and N6 are electrically connected with a bit line BL, so that a second connection end is led out; the sources of the transistors N5, N7 are electrically connected to the bit line BLB, thereby leading to a third connection terminal.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. RHBD-14T radiation-resistant SRAM memory cell based on source isolation technology, characterized in that it comprises:

a PMOS transistor P1;

the source electrode of the PMOS transistor P2 and the drain electrode of the PMOS transistor P2 are electrically connected with the drain electrode of the PMOS transistor P1;

the source electrodes of the PMOS transistors P3 and P3 are electrically connected with the drain electrode of P1 and the source electrode of P2;

the grid electrode of the PMOS transistor P4 and the grid electrode of the P4 are electrically connected with the drain electrode of the P3;

the source electrode of the PMOS transistor P5 is electrically connected with the source electrode of the P4, and the grid electrode of the P5 is electrically connected with the drain electrode of the P2;

the source electrode of the PMOS transistor P6 is electrically connected with the source electrode of P1, the drain electrode of P6 is electrically connected with the source electrode of P5 and the source electrode of P4, and the grid electrode of P6 is electrically connected with the grid electrode of P5 and the drain electrode of P2;

the drain electrode of the NMOS transistor N0, the drain electrode of the N0 is electrically connected with the drain electrode of the P5, and the grid electrode of the N0 is electrically connected with the drain electrode of the P3;

the drain electrode of the NMOS transistor N1 and the drain electrode of the NMOS transistor N1 are electrically connected with the drain electrode of the NMOS transistor P4, the grid electrode of the NMOS transistor N1 is electrically connected with the grid electrode of the NMOS transistor P5, the grid electrode of the NMOS transistor P6 and the drain electrode of the NMOS transistor P2, and the source electrode of the NMOS transistor N1 is electrically connected with the source electrode of the NMOS transistor N0;

the drain electrode of the NMOS transistor N2 and the drain electrode of the NMOS transistor N2 are electrically connected with the drain electrode of the NMOS transistor P2, the grid electrode of the NMOS transistor N2 is electrically connected with the drain electrode of the NMOS transistor P4 and the drain electrode of the NMOS transistor N1, and the source electrode of the NMOS transistor N2 is electrically connected with the source electrode of the NMOS transistor N1 and the source electrode of the NMOS transistor N0;

the drain electrode of the NMOS transistor N3 and N3 is electrically connected with the drain electrode of P3, the grid electrode of P4, the grid electrode of N0 and the drain electrode of N5, the grid electrode of N3 is electrically connected with the grid electrode of P1, the grid electrode of P2, the drain electrode of P5 and the drain electrode of N0, and the source electrode of N3 is electrically connected with the source electrode of N2, the source electrode of N1 and the source electrode of N0;

the drain electrode of the NMOS transistor N4 and the drain electrode of the N4 are electrically connected with the drain electrode of the N1, the grid electrode of the N4 is electrically connected with a word line WL, and the source electrode of the N4 is electrically connected with a bit line BL;

the drain electrode of the NMOS transistor N5 and the drain electrode of the N5 are electrically connected with the drain electrode of the N3, the grid electrode of the N5 is electrically connected with a word line WL, and the N5 is electrically connected with a bit line BLB;

the drain electrode of the NMOS transistor N6, N6 is electrically connected with the drain electrode of N0, the grid electrode of N6 is electrically connected with a word line WL, and the source electrode of N6 is electrically connected with a bit line BL;

the drain electrode of the NMOS transistor N7 and the drain electrode of the N7 are electrically connected with the drain electrode of the N2, the grid electrode of the N7 is electrically connected with a word line WL, and the N7 is electrically connected with a bit line BLB;

transistors P4 and P3, P2 and P5 are cross-coupled, P1 and P6 are used as pull-up tubes, N0, N1, N2 and N3 are used as pull-down tubes, two main storage nodes Q and QN are respectively connected with bit lines BL and BLB through N4 and N5, two redundant storage nodes S0 and S1 are respectively connected with bit lines BL and BLB through N6 and N7, N4, N5, N6 and N7 are controlled by a word line WL, the source electrode of P1 and the source electrode of P6 are connected with VDD in common, and the source electrode of N0, the source electrode of N1, the source electrode of N3 and the source electrode of N2 are connected with ground in common.

2. The RHBD-14T radiation-resistant SRAM memory cell based on source isolation technology as claimed in claim 1, wherein gate lengths of transistors N0-N7 and P1-P6 are all 65nm, wherein gate widths of transistors P1-P6 are 140nm, gate widths of transistors N0-N3 are 280nm, and gate widths of transistors N4-N7 are 140nm.

3. The RHBD-14T radiation-resistant SRAM memory cell based on the source isolation technology as claimed in claim 1, wherein when the RHBD-14T radiation-resistant SRAM memory cell is in a hold phase, bit lines BL and BLB are both precharged to a high level, word line WL is a low level, and the inside of the cell is kept in an initial state and is not operated.

4. The RHBD-14T irradiation resistant SRAM memory cell based on the source isolation technology as claimed in claim 1, wherein when the RHBD-14T irradiation resistant SRAM memory cell is in a read data phase, bit lines BL and BLB are precharged to a high level, word line WL is a high level, and transistors N4-N7 are turned on.

5. The RHBD-14T irradiation resistant SRAM memory cell based on the source isolation technology as claimed in claim 4, wherein if the data stored in the RHBD-14T irradiation resistant SRAM memory cell is '0', then "Q = S1=0, QN = S0=1"; bit line BL passes through discharge path 1: transistors N4, N1 and discharge path 2: the transistors N6 and N0 discharge to the ground, and a voltage difference is generated between the bit lines, and data is read by the sense amplifier.

6. The RHBD-14T irradiation resistant SRAM memory cell based on the source isolation technology as claimed in claim 4, wherein if the data stored in the RHBD-14T irradiation resistant SRAM memory cell is '1', then "Q = S1=1, QN = S0=0"; bit line BLB passes through discharge path 1: transistors N5, N3 and discharge path 2: the transistors N7 and N2 discharge to the ground, and a voltage difference is generated between the bit lines, and data is read by the sense amplifier.

7. The RHBD-14T irradiation resistant SRAM memory cell based on the source isolation technology as claimed in claim 1, wherein when the RHBD-14T irradiation resistant SRAM memory cell is in a data writing phase, word line WL is high, if bit line BL is high, bit line BLB is low, then '1' is written into storage node Q and storage node S1 through transistors N4 and N6 respectively.

8. The RHBD-14T radiation-resistant SRAM memory cell based on the source isolation technology as claimed in claim 1, wherein when the RHBD-14T radiation-resistant SRAM memory cell is in a data writing phase, a word line WL is high, if a bit line BL is low and a bit line BLB is high, then '0' is written to a storage node QN and a storage node S0 through transistors N5 and N7 respectively.

9. The RHBD-14T irradiation-resistant SRAM memory chip based on the source isolation technology is formed by adopting the circuit package of the RHBD-14T irradiation-resistant SRAM memory unit based on the source isolation technology according to any one of claims 1-8, and pins of the RHBD-14T irradiation-resistant SRAM memory chip comprise:

a first pin electrically connected to gates of the transistors N4 to N7 through a word line WL;

a second pin electrically connected to the sources of the transistors N4 and N6 via a bit line BL;

and a third pin electrically connected to the sources of transistors N5, N7 through bit line BLB.

10. The RHBD-14T irradiation-resistant SRAM memory module based on source isolation technology, characterized in that it adopts the circuit of RHBD-14T irradiation-resistant SRAM memory cell based on source isolation technology as claimed in any one of claims 1 to 8, said memory module comprising:

the grids of the transistors N4 to N7 are electrically connected with a word line WL, so that a first connection end is led out;

the source electrodes of the transistors N4 and N6 are electrically connected with a bit line BL, so that a second connection end is led out;

the sources of the transistors N5, N7 are electrically connected to the bit line BLB, thereby leading to a third connection terminal.

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