CN113160864B - Static memory-based single event upset resistant reinforcing circuit - Google Patents

Static memory-based single event upset resistant reinforcing circuit Download PDF

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CN113160864B
CN113160864B CN202110217615.XA CN202110217615A CN113160864B CN 113160864 B CN113160864 B CN 113160864B CN 202110217615 A CN202110217615 A CN 202110217615A CN 113160864 B CN113160864 B CN 113160864B
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transistor
drain
gate
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storage node
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CN113160864A (en
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刘红侠
梁妍
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Xidian University
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Xidian University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Abstract

The invention provides a static memory-based single event upset resistant reinforcing circuit, which combines the advantages of a DICE unit and a stable structure, so that the circuit has complete single-node upset resistance, and the reduction of the number of sensitive nodes improves the double-node resistance of a storage circuit, so that the reinforcing circuit has complete single-node upset resistance and basically has double-node upset resistance. The excellent single-particle resistance of the reinforcing circuit can improve the single-particle resistance of the aerospace memory.

Description

Static memory-based single event upset resistant reinforcing circuit
Technical Field
The invention belongs to the technical field of semiconductor chips, and particularly relates to a single event upset resistant reinforcing circuit based on a static memory.
Background
With the rapid development of aerospace technology in China, the requirement on the reliability and performance of a chip used for aerospace is higher and higher. Meanwhile, along with the development of the process size to the nanometer level, the probability of single particles entering the space chip is increased, so that the influence of the single particle effect on the space chip is larger. The static memory is used as a core unit of an aerospace chip, the correctness of the storage logic of the static memory influences the normal work of the aerospace chip, but the single-particle incident storage unit easily enables the storage logic to be turned over, so that the working state of the whole aerospace circuit is influenced, even the function of the whole aerospace circuit is failed, how to reinforce the static memory built by the FDSOI from the aspect of circuit level is realized, and the static memory is a new challenge for improving the single-particle resistance of the static memory circuit for aerospace.
Simulation experiments show that: under the condition of heavy ions, the drain terminal of a cut-off NMOS device in a 6T-SRAM unit can cause the voltage change of a storage node due to the action of single particles, the voltage change causes the turn-on of an originally cut-off transistor in an adjacent inverter, so that the voltage of another storage node is changed, the error turning of the storage node caused by the heavy ion incidence device is aggravated by positive feedback formed by the voltage change, and if the recovery time is longer than the feedback time, the turning of the storage logic of the 6T-SRAM unit can be caused.
The traditional reinforcing method for the single-particle incident memory cell is mainly based on the reinforcing research of a resistor, a capacitor and a circuit level, and the reinforcing method of the resistor and the capacitor has the defects of large inherent layout area, unstable reinforcing effect, poor reinforcing effect and the like, so that the circuit level reinforcing method becomes the main method for reinforcing the SRAM cell against the single particles, but most of the traditional circuit level reinforcing method based on the bulk silicon process cannot reinforce all single nodes, only the DICE unit circuit can realize the complete single-node overturn resistance of the memory cell, but the reinforcing effect for double nodes is poor, so that the traditional circuit level reinforcing method based on the bulk silicon process cannot meet the single-particle resistance performance requirement of the space chip. The research shows that: the storage circuit built by adopting the FDSOI process can improve the single event upset resistance, the DICE unit built by the process has the complete single node upset resistance, and the 1/2 double nodes have the double node upset resistance. It can be seen that: the storage circuit is built by adopting the FDSOI technology, and if the traditional circuit level reinforcing method is adopted, the storage circuit still has no good single particle resistance.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a static memory-based single event upset resistant reinforcement circuit, which is called a DICE-WD structure with reduced number of sensitive nodes. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a static memory-based single event upset resistant reinforcing circuit, which comprises: a first transistor N1, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, a sixth transistor N6, a seventh transistor N7, an eighth transistor N8, a ninth transistor N9, a tenth transistor N10, an eleventh transistor P1, a twelfth transistor P2, a thirteenth transistor P3, and a fourteenth transistor P3, wherein a gate of the first transistor N3 is connected to a source of the fifth transistor N3, a drain of the second transistor N3, a drain of the eighth transistor N3, and a gate of the thirteenth transistor P3, respectively, and substrates of the first transistor N3, the second transistor N3, the eighth transistor N3, and the fourth transistor N3 are connected to a ground of the respective sources, and then the fifth transistor N3, the sixth transistor N3, the seventh transistor N3, the eighth transistor N3, the ninth transistor N3, and the tenth transistor N3 are connected to the ground of the substrate of the transistor N3, a drain of the first transistor N1 is connected to a gate of the fourth transistor N4, a drain of the seventh transistor N7, a gate of the second transistor N2, a drain of the eleventh transistor P1 and a gate of the sixth transistor N6, a gate of the third transistor N3 is connected to a drain of the fourth transistor N4, a drain of the tenth transistor N10, a drain of the fourteenth transistor P4, a gate of the eleventh transistor P1 and a gate of the fifth transistor N5, a drain of the third transistor N3 is connected to a source of the sixth transistor N6, a gate of the twelfth transistor P2 and a drain of the ninth transistor N9, a drain of the fifth transistor N5 is connected to a drain of the twelfth transistor P2, a drain of the sixth transistor N6 is connected to a drain of the thirteenth transistor P3 and a gate of the fourteenth transistor P4, a source of the seventh transistor N7 is connected to a source of the ninth transistor N9, and a bit line BL is connected, a gate of the seventh transistor N7 is connected to a gate of the eighth transistor N8, a gate of the ninth transistor N9, and a gate of the tenth transistor N10, respectively, and then connected to a word line WL, a source of the eighth transistor N8 is connected to a source of the tenth transistor N10, and then connected to a bit line BLN, and substrates of the eleventh transistor P1, the twelfth transistor P2, the thirteenth transistor P3, and the fourteenth transistor P4 are connected to sources thereof, and then commonly connected to a power supply voltage VDD.
Optionally, the first transistor N1, the second transistor N2, the third transistor N3, the fourth transistor N4, the fifth transistor N5, the sixth transistor N6, the seventh transistor N7, the eighth transistor N8, the ninth transistor N9, and the tenth transistor N10 are NMOS transistors, and the eleventh transistor P1, the twelfth transistor P2, the thirteenth transistor P3, and the fourteenth transistor P4 are PMOS transistors.
Optionally, a storage node between the drain of the eleventh transistor P1 and the drain of the first transistor N1 is X1, a storage node between the drain of the second transistor N2 and the source of the fifth transistor N5 is X2, a connection storage node between the drain of the third transistor N3 and the source of the sixth transistor N6 is X3, a storage node between the drain of the fourteenth transistor P4 and the drain of the fourth transistor N4 is X4, the twelfth transistor P2, the thirteenth transistor P3, the second transistor N2 and the third transistor N3 form a stable structure, the storage node X2 and the storage node X3 are change points of the stable structure, the storage node X1 and the storage node X4 are redundant points of the stable structure, and the eleventh transistor P1, the fourteenth transistor P4, the first transistor N1 and the fourth transistor N4 constitute a part of the DICE unit, when the logic levels of the Bit Line (BL), the Word Line (WL), and the bit Bar Line (BLN) are changed, the storage nodes X1, X2, X3, and X4 have corresponding logic changes in different states.
Optionally, the eleventh transistor P1, the twelfth transistor P2, the thirteenth transistor P3 and the fourteenth transistor P4 are pull-up transistors, the first transistor N1, the second transistor N2, the third transistor N3 and the fourth transistor N4 are pull-down transistors, the seventh transistor N7, the eighth transistor N8, the ninth transistor N9 and the tenth transistor N10 are pass transistors, and a pass transistor size is smaller than a pull-down transistor size and larger than a pull-up transistor size.
Optionally, the length of each transistor is 28nm, the transistor width of the pull-down tube is 190nm, the transistor width of the pull-up tube is 80nm, and the transistor width of the transmission tube is 140 nm.
The invention provides a static memory-based single event upset resistant reinforcing circuit, which combines the advantages of a DICE unit and a stable structure, so that the circuit has complete single-node upset resistance, and the reduction of the number of sensitive nodes improves the double-node resistance of a storage circuit, so that the reinforcing circuit has complete single-node upset resistance and basically has double-node upset resistance. The excellent single particle resistance of the reinforced circuit can improve the single particle resistance of the aerospace memory. The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a single event upset resistance reinforcing circuit based on a static memory according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a transistor under a set size configuration according to an embodiment of the present invention;
FIG. 3 is a timing diagram of the reinforcing circuitry of the present invention in three states, read, write, and hold;
FIG. 4 is a diagram showing the effect of the transient pulse current generated by the simulated single-particle incident turn-off device in the present invention;
FIG. 5a is the upset condition of the store logic when single event incident turns off N1;
FIG. 5b is a flip of the store logic when single event incident turns off N3;
FIG. 5c is a flip of the store logic when single event incident turns off P4;
FIG. 6a shows the inversion of the storage logic when single-particle simultaneous incident turns off N1 and N3;
FIG. 6b is the upset condition of the storage logic when single particle is incident and turned off N3 and P4 simultaneously;
FIG. 6c shows the inversion of the memory logic when a single event is incident simultaneously to turn off N1 and P4.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
As shown in fig. 1, a structure of a single event upset resistant reinforcing circuit based on a static memory according to an embodiment of the present invention includes:
a first transistor N1, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, a sixth transistor N6, a seventh transistor N7, an eighth transistor N8, a ninth transistor N9, a tenth transistor N10, an eleventh transistor P1, a twelfth transistor P2, a thirteenth transistor P3, and a fourteenth transistor P3, wherein a gate of the first transistor N3 is connected to a source of the fifth transistor N3, a drain of the second transistor N3, a drain of the eighth transistor N3, and a gate of the thirteenth transistor P3, respectively, and substrates of the first transistor N3, the second transistor N3, the eighth transistor N3, and the fourth transistor N3 are connected to a ground of the respective sources, and then the fifth transistor N3, the sixth transistor N3, the seventh transistor N3, the eighth transistor N3, the ninth transistor N3, and the tenth transistor N3 are connected to the ground of the substrate of the transistor N3, a drain of the first transistor N1 is connected to a gate of the fourth transistor N4, a drain of the seventh transistor N7, a gate of the second transistor N2, a drain of the eleventh transistor P1 and a gate of the sixth transistor N6, a gate of the third transistor N3 is connected to a drain of the fourth transistor N4, a drain of the tenth transistor N10, a drain of the fourteenth transistor P4, a gate of the eleventh transistor P1 and a gate of the fifth transistor N5, a drain of the third transistor N3 is connected to a source of the sixth transistor N6, a gate of the twelfth transistor P2 and a drain of the ninth transistor N9, a drain of the fifth transistor N5 is connected to a drain of the twelfth transistor P2, a drain of the sixth transistor N6 is connected to a drain of the thirteenth transistor P3 and a gate of the fourteenth transistor P4, a source of the seventh transistor N7 is connected to a source of the ninth transistor N9, and a bit line BL is connected, a gate of the seventh transistor N7 is connected to a gate of the eighth transistor N8, a gate of the ninth transistor N9, and a gate of the tenth transistor N10, respectively, and then connected to a word line WL, a source of the eighth transistor N8 is connected to a source of the tenth transistor N10, and then connected to a bit line BLN, and substrates of the eleventh transistor P1, the twelfth transistor P2, the thirteenth transistor P3, and the fourteenth transistor P4 are connected to sources thereof, and then commonly connected to a power supply voltage VDD.
The first transistor N1, the second transistor N2, the third transistor N3, the fourth transistor N4, the fifth transistor N5, the sixth transistor N6, the seventh transistor N7, the eighth transistor N8, the ninth transistor N9 and the tenth transistor N10 are NMOS transistors, and the eleventh transistor P1, the twelfth transistor P2, the thirteenth transistor P3 and the fourteenth transistor P4 are PMOS transistors.
Wherein a storage node between the drain of the eleventh transistor P1 and the drain of the first transistor N1 is X1, a storage node between the drain of the second transistor N2 and the source of the fifth transistor N5 is X2, a connection storage node between the drain of the third transistor N3 and the source of the sixth transistor N6 is X3, a storage node between the drain of the fourteenth transistor P4 and the drain of the fourth transistor N4 is X4, the twelfth transistor P2, the thirteenth transistor P3, the second transistor N2 and the third transistor N3 form a stable structure, the storage node X2 and the storage node X3 are transition points of the stable structure, the storage node X1 and the storage node X4 are redundancy points of the stable structure, the eleventh transistor P1, the fourteenth transistor P4, the first transistor N1 and the fourth transistor N4 constitute a part of the DICE cell, when the logic levels of the Bit Line (BL), the Word Line (WL), and the bit Bar Line (BLN) are changed, the storage nodes X1, X2, X3, and X4 have corresponding logic changes in different states.
The reinforcing circuit is manufactured based on an FDSOI process, and is a memory cell.
The core circuit of the memory cell is a stable structure, and the redundancy point of the structure has excellent single particle resistance. The structure of the reinforced circuit of the embodiment has the transistors P2, P3, N2 and N3 forming a stable structure, wherein the gate of P2P3 is connected to the storage node X3X2, X3X2 is a change point of the stable structure, the gate of N2N3 is connected to the storage node X1X4, and X1X4 is a redundant point of the stable structure.
The research shows that: for the single-particle incidence DICE unit, all storage nodes of the single-particle incidence DICE unit have single-node upset resistance, in the structure of the reinforced circuit, the transistors N1, N4, P1 and P4 adopt a circuit connection mode in the DICE unit, so that the unit has excellent single-node upset resistance.
The sensitive node of the storage unit is connected with the source and drain of the NMOS, the connection point of the transistor N2N5 is X2, and the connection point of the transistor N3N6 is X3.
According to the principle analysis, the storage node X4 is connected to the gate terminal of P1, when X4 stores logic 0, the turned-on P1 enables X1 to store logic 1, the storage node X1 is connected to the gate terminal of N2, the high level of X1 enables N2 to be turned on, X2 stores logic 0, X1X2 is respectively connected to the gate terminals of N6P3, the turned-on N6P3 enables the storage node X3 to store logic 1, and the storage unit can complete correct storage logic.
The word line WL is connected to the gate terminals of the transistors N7, N8, N9, and N10, the memory cell is in a hold state when the WL is low, the memory cell is in a read/write state when the WL is high, the source terminal of the transistor N7N9 is connected to the bit line BL, and the source terminal of the transistor N8N10 is connected to the bit bar line BLN.
The invention provides a static memory-based single event upset resistant reinforcing circuit, which combines the advantages of a DICE unit and a stable structure, so that the circuit has complete single-node upset resistance, and the reduction of the number of sensitive nodes improves the double-node resistance of a storage circuit, so that the reinforcing circuit has complete single-node upset resistance and basically has double-node upset resistance. The excellent single-particle resistance of the reinforcing circuit can improve the single-particle resistance of the aerospace memory.
Example two
As an alternative embodiment of the present invention, the eleventh transistor P1, the twelfth transistor P2, the thirteenth transistor P3 and the fourteenth transistor P4 are pull-up transistors, the first transistor N1, the second transistor N2, the third transistor N3 and the fourth transistor N4 are pull-down transistors, the seventh transistor N7, the eighth transistor N8, the ninth transistor N9 and the tenth transistor N10 are pass transistors, and a pass transistor size is smaller than a pull-down transistor size and larger than a pull-up transistor size.
The length of each transistor is 28nm, the transistor width of a pull-down tube is 190nm, the transistor width of a pull-up tube is 80nm, and the transistor width of a transmission tube is 140 nm.
Referring to fig. 2, fig. 2 is a circuit connection diagram of transistors under size setting, and the following analyzes the transistor size required for normal operation of the memory circuit with reference to fig. 2, and all the transistor names refer to fig. 1:
and (3) keeping operation: when the word line WL is low, the pass transistor (access transistor) N7-N10 is turned off, and at this time, the connection between the bit line, the bit bar line, and the storage node is interrupted, and the storage cell maintains the original stored logic value, thereby realizing the holding operation of the SRAM.
In the process of reading and writing of the SRAM unit, because the NMOS transistor can generate a weak 1 problem when transmitting 1, and can correctly transmit a logic value when transmitting 0, the write 1 operation writes 0 to X2X4 through BLN, when an X2X4 point meets the threshold voltage of P1P3, the conducted P1P3N6 pulls up the X1X3 node, finally the SRAM unit can correctly write 1, and the process of reading 1 is also realized through BLN output of 0.
And (3) reading: the read operation of the SRAM means outputting the logic value stored in the storage node X1X2X3X4 to the external port through the bit line BL and the bit bar line BLN, and readability requires that the pull-down pipe size be larger than the pass pipe. When the storage node X1X2X3X4 is 0101, the transistor N1N3 is turned on, and a BL read-out 0 process, that is, a read-0 operation can be implemented by turning on N1N7 and N3N 9. Before a read operation, firstly, a bit line BL and a bit bar BLN need to be precharged to a high level 1, if the transistor size N7> N1 and N9> N3, the transmission capability of a pass transistor N7N9 is greater than the pull-down capability of a pull-down transistor N1N3, so that the logic value of a node X1X3 is pulled up to 1 by an N7N9 pass transistor, and the SRAM generates wrong logic inversion, which is called as read damage of the SRAM; if the transistor size N7< N1, N9< N3, the pull-down capability of turning on N1N3 is greater than the transmission capability of the pass transistor N7N9, so that the node X1X3 remains as the original logic 0, the BL starts to discharge by turning on N1N7, N3N9, the node X1X3 stores the correct logic 0, the logic 0 of the node X1 turns off N2N4, and the BLN does not form a conductive path with N2N8, N4N10, so that the potential of the BLN remains at the logic high level, and the voltage difference between the BL and BLN realizes the SRAM read 0 operation. From the above analysis it follows that: the readability of SRAM for read 0 operation requires transistor sizes N7< N1, N9< N3, where the logic value of the SRAM storage node can be kept unchanged. When the storage node X1X2X3X4 is 1010, the transistor N2N4 is turned on, the BLN read-out 0 process, that is, the read 1 operation, can be realized by turning on N2N8 and N4N10, before the read operation, the bit line BL and the bit bar BLN need to be precharged to a high level first, since X2X4 stores logic 0, when the transistor sizes N8> N2 and N10> N4, since the transfer capability of the pass transistor N8N10 is greater than the pull-down capability of the pull-down transistor N2N4, the pass transistor N8N10 causes X2X4 to store logic 1, so that X2X4 makes an erroneous logic inversion, which is called a read break of the SRAM, if the transistor sizes N8< N2, N10< N4, the X2X4 node keeps storage logic 0 through the pull-down N2N4 with strong pull-down capability, the turned on N2N 58, N4N10 starts to discharge from the storage node BL 3N 10, so that no conductive bit line BL 72 and no BL 72 form a conductive bit line BL 3N 10, at this time, BL and BLN form a voltage difference to realize the read 1 operation. For reading operation, a sensitive amplifier can be externally connected at two ends of a bit line BL and an inverted bit line BLN, even if the voltage difference between the two ends of the BL and the BLN is very small, the larger voltage difference between the two ends can be realized through the amplification effect of the sensitive amplifier, high and low levels are sent to a data output end, and the reading 0 and reading 1 operation of the SRAM is realized.
And (3) writing operation: when the storage node X1X2X3X4 is 1010, and N2N4P1P3 is turned on at this time, a write 0 operation of the SRAM may be realized, the word line WL is set to a high level, the bit line BL and the bit bar BLN are respectively set to logic 0 and logic 1, when the transistor sizes N7< P1 and N9< P3, since the driving capability of the pass transistor N7N9 is smaller than the pull-up capability of P1P3, the X1X3 node keeps logic 1 unchanged, and logic 0 cannot be written through the bit line BL, which is called write-break, when the transistor sizes N7> P1 and N9> P3, the driving capability of the pass transistor N7N9 is larger than the pull-up capability of P1P3, so that the node X1X 8 correctly writes logic 0, which is called a write 0 operation of the SRAM, and the writability requires the transistor sizes N6 > P1, N9> P3673729. When the storage node X1X2X3X4 is 0101, the transistor N1N3P2P4 is turned on, so that a write 1 operation of the SRAM can be realized, the word line WL is set to a high level, the bit line BL and the bit bar BLN are respectively set to logic 1 and logic 0, since the NMOS transistor transmits weak 1, logic 1 cannot be written to the storage node X1X3 through BL, when the transistor sizes N8< P2 and N10< P4, since the driving capability of the pass transistor N8N10 is smaller than the pull-up capability of the P2P4, the storage node X2X4 keeps the original logic 1 unchanged, so that an operation of writing 0 to the X2X4 through BLN cannot be realized, when the transistor sizes N8> P2 and N10> P4, the storage node X2X4 writes logic 0 through the bit bar BLN, when the logic value of the node X2X4 node satisfies the threshold voltage of P1P3, the turned on transistor N3P2P4 is turned on, so that the storage node X1X 461 operation is realized through the internal feedback mechanism of the SRAM X461 node, so that the SRAM 1 operation is high-stored value is realized.
By combining the above analysis of the working state of the SRAM cell, it can be obtained: the access pipe is required to be smaller than the pull-down pipe in the read operation, the access pipe is required to be larger than the pull-up pipe in the write operation, 0 and 0 are written and read through the bit line BL when 0 and 0 are written and 0 and read through the bit bar line BLN when 1 and 1 are written and read, and then the function of correctly reading and writing the logic 1 of each node is realized according to a feedback mechanism in the storage unit. Therefore, the transistor size of the storage unit determines the correct reading and writing state, the transmission tube size is smaller than the pull-down tube size and larger than the pull-up tube size, and the transistor size determines the correct reading and writing of the storage unit.
The working principle of the present invention will be described with reference to the timing diagram of the reinforcing circuit of the present invention in three states of read, write and hold provided in fig. 3.
When X1X2X3X4 is 1010, at this time, 0 needs to be written to the memory cell, BL 0, BLN 1, and WL 0 need to be set before 9ns, and at 9ns, WL 1 needs to be set, at this time, since the transistor N1N5P2N3P4 is turned off and the pass size is larger than the pull-up tube, at this time, the X1X3 node can correctly write logic 0 through the pass tube, and finally, under the action of internal feedback and BLN, the X2X4 node stores logic 1, thereby realizing that the memory cell writes 0.
For the above-mentioned write 0 process, finally making X1X2X3X4 equal to 0101, when WL equal to 0, the memory cell is in the hold state, for the read process, first, BL and BLN need to be precharged before 19ns, that is, making BL equal to BLN equal to 1, when WL equal to 1, the read 0 process of the memory cell is entered, since the transistor N1N5P2N3P4 is turned on and the pass size is smaller than the pull-down NMOS, at this time, the logic 1 of the pass is not transferred to the storage node, so that the logic value of X1X3 is not changed, the pull-down on N1N3 respectively forms a path with the pass N7N9, so that the bit line BL potential starts to drop, the turned-off N2N4 does not form a path with the bit line BL and GND, at this time, the potential difference between BL and BLN does not change, and the read 0 operation of the memory cell is realized.
The performance of the invention is explained below by setting the current value of ipwl to simulate the transient pulse current generated by the single-particle incident shutoff device and verifying the upset condition of the storage logic when the single-particle incident memory cell is verified.
Referring to fig. 4, the pulse current generated by the simulated single-particle incident turn-off device in the sentaurus is set to be an ipwl current source to truly simulate the influence of heavy ions on the memory cell, and the single-particle LET value corresponding to the transient pulse current of the figure is 0.8 pc/um.
Next, the inversion of the memory logic of the reinforcing circuit when a single particle is incident on a single node of the memory cell will be described.
5 a-5 c, FIG. 5a is the upset condition of the store logic when single event incident turns off N1, and FIG. 5b is the upset condition of the store logic when single event incident turns off N3; fig. 5c shows the flip of the memory logic when the single event incident turns off P4.
Assuming that the storage node X1X2X3X4 is 1010 and the heavy ion incidence time is 32ns, the principle of the anti-single node analysis for the storage cell is as follows:
for the storage node X1, when a single event is incident to turn off the transistor N1, an electron current is generated at the drain terminal of the turn-off N1, at this time, the node X1 is turned to 0, which causes the N2N6N4 to be in an off state, so that the node X2X3X4 is in a high-resistance state, and the storage node X2X3X4 is not turned over by the transient turning of the node X1, and since the P1 transistor is always turned on in this process, after the electron pulse current of the node X1 disappears, the node X1 is pulled to 1 by the turned-on P1, and finally, all the nodes restore the initial correct logic.
For the storage node X2 being 0, this node is not a sensitive node since it is connected to the source and drain terminals of the N2N5 transistor.
For the storage node X3, when a single event incidence turns off the transistor N3, at this time, the storage node X3 generates an electron current pulse, the X3 node flips to 0, the change of the node only affects the P2 transistor, so the storage node X1X4 keeps logic 10, X1X4 equals 10 to turn on N2 and turn off N5, so that turning on P2 does not affect the logic value of X2, X1X2 equals 10 to turn on N6P3, under the action of turning on N6P3, the X3 node is pulled up to 1, and finally, all the nodes restore the initial correct logic.
For the storage node X4, when the transistor P4 is turned off by single-particle incidence, a hole current pulse is generated at the node X4, and for a storage unit built by FDSOI of the single-particle incidence single node, research shows that: for a single event with an LET value of 0.8pc/um, the memory unit cannot be overturned, so that the memory node keeps the initial correct logic at the moment.
The following describes the inversion of the memory logic of the reinforcing circuit when a single particle enters a double node of a memory cell.
Referring to fig. 6a to 6c, fig. 6a shows the upset condition of the storage logic when single-particle simultaneous incidence turns off N1 and N3, and fig. 6b shows the upset condition of the storage logic when single-particle simultaneous incidence turns off N3 and P4; FIG. 6c shows the inversion of the memory logic when a single event is incident simultaneously to turn off N1 and P4.
Assuming that the storage node X1X2X3X4 is 1010 and the heavy ion incidence time is 32ns, the principle of the anti-binodal analysis for the storage cell is as follows:
since the X2 node is not a sensitive node, for a double node including the X2 node, the analysis mechanism is consistent with the single-particle incident single-node inversion mechanism, and at this time, the logic inversion of the memory cell cannot occur.
When the N1N3 device is turned off by single event incidence, the storage node X1X3 is 00, X1 is turned over to 0 to turn off N4, at this time, the storage node X4 keeps logic 0, since X3 is turned over to 0 to only turn on P2, X4 is 0 to turn off N5 all the time, the X2 node is in a floating state, the X2 node keeps logic 0 unchanged, since X4 is kept 0 all the time, P1 is always turned on, when an electron current pulse at the point X1 disappears, the node X1 recovers logic 1 under the pull-up action of P1, when the electron pulse current at the node X3 disappears, the node X3 pulls up to logic 1 under the action of turning on P3N6, and finally, all the nodes recover the initial correct logic.
When the N3P4 device is turned off by single event incidence, the storage node X3X4 is 01, the N3N5 is turned on by the logic 1 of X4, the P2 is turned on by the logic 0 of X3, the P1 is in an off state by the logic 1 of X4, X1 keeps logic 1, although P2N5 is turned on, since the transmission of the two is weak 1, the transistor N1 is hard to turn on, X1 finally keeps logic 1, X2 is turned over to 0 under the action of the logic 1 of X1, X3 is turned over to 1, X4 is turned over to 0, and finally all nodes restore the initial correct logic.
When the N1P4 device is turned off by single event incidence, the storage node X1X4 is 01, although the logic 0 of X1 does not temporarily cause the originally turned-off device to be turned on, since the logic 1 of X4 causes N3N5 to be turned on, the turned-on N3 causes X3 to be turned over to 0, further causing P2 to be turned on, the turned-on P2N5 causes the storage node X2 to be turned over to 1, the logic 1 finally causes N1 to be turned on, and this positive feedback mechanism finally causes all nodes to be turned over erroneously.
The following experiment was conducted to evaluate the single particle resistance of the DICE-WD structure for reducing the number of sensitive nodes.
Verification software
Adopting sentaurus software to generate pulse current, and adopting spectre software to build a novel circuit.
Second, verification method
Pulse current generated by a heavy ion incidence turn-off device is simulated by utilizing sentaurus software, and the pulse current is added to a storage node corresponding to a reinforcing circuit in an ipwl current source mode.
Third, verification process
When the storage logic X1X2X3X4 is 1010, the transistor N1N5N3P4 connected to the storage node is in an off state, and a pulse current generated by a single-event-incident turn-off device is added to the corresponding storage node at a moment of 32ns, wherein the pulse current is a current generated by FDSOI turned off under the worst condition and when a single-event LET value is 0.8pc/um, and since X2 is 0 and the node is a connection point of two NMOS devices, X2 is not a sensitive node, and an electron current is added to X1 and X3, and a hole current is added to X4, so that the single-node-upset resistance of the storage unit is verified; for the verification of the double-node resistance, because X2 is not a sensitive node and the cell has complete single-node upset resistance, the double-node including X2 has the double-node resistance, and for the single-event resistance research of the invention, the remaining double-nodes X1X3, X1X4 and X3X4 need to be verified, and corresponding pulse currents are added into corresponding storage nodes.
Verification results and analysis
In order to verify the influence of a single particle on the upset capability of a novel storage unit, pulse current is added to a corresponding storage node at a moment of 32ns, and as shown in fig. 5a to 5c, when a single particle is incident to a single node, it can be found that: all storage nodes cannot be overturned; as shown in fig. 6 a-6 c, which are the single particle incident double node cases, it can be found that: only X1X4 does not have the double-node overturning resistance, and because the invention is a novel storage unit built based on the FDSOI process, the hole current generated by the corresponding cut-off P tube of the storage unit is very small, and X1X4 can be set as a storage node with the farthest distance in a layout, the novel storage unit has complete single-node overturning resistance and basically complete double-node overturning resistance. Simulation research shows that: compared with a DICE unit built by a bulk silicon process, the DICE unit built by adopting the same device size and device structure as those of the DICE unit built by the bulk silicon process has complete single-node overturning resistance, only the double node of 1/2 has double-node overturning resistance, and the double nodes of X1X3, X1X4 and X2X3 do not have double-node overturning resistance. Therefore, the DICE-WD structure for reducing the number of the sensitive nodes well overcomes the defect of poor single particle resistance of the traditional storage circuit.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (5)

1. A single event upset resistant reinforcement circuit based on a static memory is characterized by comprising: a first transistor (N1), a second transistor (N2), a third transistor (N3), a fourth transistor (N4), a fifth transistor (N5), a sixth transistor (N6), a seventh transistor (N7), an eighth transistor (N8), a ninth transistor (N9), a tenth transistor (N10), an eleventh transistor (P1), a twelfth transistor (P2), a thirteenth transistor (P3), and a fourteenth transistor (P4), wherein a gate of the first transistor (N1) is connected to a source of the fifth transistor (N5), a drain of the second transistor (N2), a drain of the eighth transistor (N8), and a gate of the thirteenth transistor (P3), respectively, and substrates of the first transistor (N1), the second transistor (N2), the third transistor (N3), and the fourth transistor (N4) are connected to respective sources, and then the fifth transistor (N5) is connected to the common substrate of the first transistor (N5), and the third transistor (N2), the fourth transistor (N4) is connected to the respective sources, Substrates of a sixth transistor (N6), a seventh transistor (N7), an eighth transistor (N8), a ninth transistor (N9) and a tenth transistor (N10) are connected in parallel to a power Ground (GND), a drain of the first transistor (N1) is connected to a gate of the fourth transistor (N4), a drain of the seventh transistor (N7), a gate of the second transistor (N2), a drain of the eleventh transistor (P1) and a gate of the sixth transistor (N6), a gate of the third transistor (N3) is connected to a drain of the fourth transistor (N4), a drain of the tenth transistor (N10), a drain of the fourteenth transistor (P4), a gate of the eleventh transistor (P1) and a gate of the fifth transistor (N5), a drain of the third transistor (N3) is connected to a source of the sixth transistor (N6), a source of the twelfth transistor (N2) and a gate of the ninth transistor (N9) respectively, a drain of the fifth transistor (N5) is connected to a drain of the twelfth transistor (P2), a drain of the sixth transistor (N6) is connected to a drain of the thirteenth transistor (P3) and a gate of the fourteenth transistor (P4), respectively, a source of the seventh transistor (N7) is connected to a source of the ninth transistor (N9), and then the Bit Line (BL) is connected thereto, a gate of the seventh transistor (N7) is connected to a gate of the eighth transistor (N8), a gate of the ninth transistor (N9), and a gate of the tenth transistor (N10), respectively, and then the Word Line (WL) is connected thereto, a source of the eighth transistor (N8) is connected to a source of the tenth transistor (N10), and then the Bit Line (BLN) is connected thereto, and then respective substrates of the eleventh transistor (P1), the twelfth transistor (P2), the thirteenth transistor (P3), and the fourteenth transistor (P4) are connected to respective sources, the power supply Voltage (VDD) is connected in common.
2. The reinforcement circuit according to claim 1, characterized in that the first transistor (N1), the second transistor (N2), the third transistor (N3), the fourth transistor (N4), the fifth transistor (N5), the sixth transistor (N6), the seventh transistor (N7), the eighth transistor (N8), the ninth transistor (N9) and the tenth transistor (N10) are NMOS transistors, and the eleventh transistor (P1), the twelfth transistor (P2), the thirteenth transistor (P3) and the fourteenth transistor (P4) are PMOS transistors.
3. The reinforcement circuit according to claim 1, wherein a storage node between a drain of the eleventh transistor (P1) and a drain of the first transistor (N1) is X1, a storage node between a drain of the second transistor (N2) and a source of the fifth transistor (N5) is X2, a connection storage node between a drain of the third transistor (N3) and a source of the sixth transistor (N6) is X3, a storage node between a drain of the fourteenth transistor (P4) and a drain of the fourth transistor (N4) is X4, the twelfth transistor (P2), the thirteenth transistor (P3), the second transistor (N2), and the third transistor (N3) form a stable structure, the storage node X2 and the storage node X3 are change points of the stable structure, the storage node X1 and the storage node X4 are redundant points of the stable structure, the eleventh transistor (P1), the fourteenth transistor (P4), the first transistor (N1), and the fourth transistor (N4) form a part of a DICE cell, and when logic levels of a Bit Line (BL), a Word Line (WL), and a bit Bar Line (BLN) are changed, the storage nodes X1, X2, X3, and X4 have corresponding logic changes in different states.
4. The reinforcement circuit of claim 1, wherein the eleventh transistor (P1), the twelfth transistor (P2), the thirteenth transistor (P3), and the fourteenth transistor (P4) are pull-up transistors, the first transistor (N1), the second transistor (N2), the third transistor (N3), and the fourth transistor (N4) are pull-down transistors, the seventh transistor (N7), the eighth transistor (N8), the ninth transistor (N9), and the tenth transistor (N10) are pass transistors, and pass transistor sizes are smaller than the pull-down transistor sizes and larger than the pull-up transistor sizes.
5. The ruggedized circuit of claim 4, wherein each transistor has a length of 28nm, a pull-down transistor has a transistor width of 190nm, a pull-up transistor has a transistor width of 80nm, and a pass transistor has a transistor width of 140 nm.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336362A (en) * 2015-12-10 2016-02-17 中北大学 Radiation hardened static random access memory
CN105448327A (en) * 2015-11-16 2016-03-30 哈尔滨工业大学 Storage unit resistant to multi-node inversion
US9748955B1 (en) * 2016-04-05 2017-08-29 Stmicroelectronics (Crolles 2) Sas Radiation-hardened CMOS logic device
CN108492843A (en) * 2018-04-04 2018-09-04 安徽大学 A kind of 14T Flouride-resistani acid phesphatases static storage cell
CN108766492A (en) * 2017-12-28 2018-11-06 北京时代民芯科技有限公司 A kind of anti-SEU storage unit circuits of low single-particle sensibility

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448327A (en) * 2015-11-16 2016-03-30 哈尔滨工业大学 Storage unit resistant to multi-node inversion
CN105336362A (en) * 2015-12-10 2016-02-17 中北大学 Radiation hardened static random access memory
US9748955B1 (en) * 2016-04-05 2017-08-29 Stmicroelectronics (Crolles 2) Sas Radiation-hardened CMOS logic device
CN108766492A (en) * 2017-12-28 2018-11-06 北京时代民芯科技有限公司 A kind of anti-SEU storage unit circuits of low single-particle sensibility
CN108492843A (en) * 2018-04-04 2018-09-04 安徽大学 A kind of 14T Flouride-resistani acid phesphatases static storage cell

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
A novel highly reliable and low-power radiation hardened SRAM bit-cell design;Dianpeng Lin;《IEICE Electronics Express》;20180116;全文 *
We-Quatro: Radiation-Hardened SRAM Cell With Parametric Process Variation Tolerance;Le Dinh Trang Dang;《IEEE TRANSACTIONS ON NUCLEAR SCIENCE》;20170718;全文 *

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