CN116741228A - 14T radiation-resistant SRAM memory unit and circuit module, structure and chip based on same - Google Patents

Abstract

The invention relates to a 14T radiation-resistant SRAM memory cell, and a circuit module, a structure and a chip based on the same. The SRAM memory cell includes 6 NMOS transistors N1 to N6 and 8 PMOS transistors P1 to P8. P1, P2, P5 and P6 are used as pull-up tubes, P3 and P4 are used as pull-down tubes, and their states are controlled by storage nodes Q and QN, respectively. Q and QN are electrically connected to bit line BL and bit line BLB through N5 and N6, respectively. The redundant storage nodes S0 and S1 are electrically connected to the bit line BL and the bit line BLB through P7 and P8, respectively. The invention adopts the polarity reinforcing principle to design, ensures the stability of redundant storage nodes S0 and S1, and improves the stability of the storage node Q, QB by utilizing the source isolation technology. In the process of writing data, the bit lines write data into the internal nodes Q\QB and S0\S1 through N5, N6, P7 and P8, so that the data writing speed and the noise margin of the SRAM memory cell are greatly improved, and the power consumption of the memory cell is reduced.

Description

14T radiation-resistant SRAM memory unit and circuit module, structure and chip based on same

Technical Field

The present invention relates to an SRAM memory cell, and more particularly, to a 14T irradiation-resistant SRAM memory cell, a circuit module based on the 14T irradiation-resistant SRAM memory cell, a circuit structure based on the 14T irradiation-resistant SRAM memory cell, and a circuit chip based on the 14T irradiation-resistant SRAM memory cell.

Background

The radiation effect in space causes a single event effect (Single Event Effect, abbreviated SEE) on the static random access memory (Static Random Access Memory, abbreviated SRAM) that is in operation. The single event effect can cause hard and soft errors to the electronic device. Hard errors can occur resulting in physical-level damage to the device, with catastrophic consequences; soft errors, however, mainly affect the operating state of the device, making it impossible to deliver the correct information. Due to the limited energy of the spatially radiating particles, the probability of soft errors of the device is far greater than the probability of hard errors of the device. Whereas in soft errors, single event upset (Single Event Upset, abbreviated SEU) occurs with a much greater probability than other types of errors. In order to improve the SEU resistance of the unit, the prior art mainly comprises the following schemes:

1) As shown in FIG. 1, the structure of a DICE12T circuit for single event upset resistance is proposed by T.Calin, M.Nicolaidis and R.Velazco in 1996. It has 4 storage nodes and 4 transport pipes. When an SEU occurs on each single storage node, that node is eventually restored by the remaining nodes. However, when SEU occurs in any two storage nodes, the storage information of the circuit node will flip and cannot recover itself, thus causing erroneous data.

2) Fig. 2 shows a schematic structure of a Soft Error Tolerant T SRAM Bit-Cell (QUATRO 10T) circuit proposed by Shah m. It has better resistance to SEU than a conventional six-pipe cell structure, but the cell has poorer write capability and it maintains poorer noise margin (Hold Static Noise Margin, abbreviated as HSNM) and read static noise margin (Read Static Noise Margin, abbreviated as RSNM).

3) As shown in fig. 3, the SAR14T circuit proposed by Soumitra Pal in 2021 is a schematic structure, which uses 4 NMOS transistors to write data into the cell, but uses 2 NMOS transistors to read through the external node, thereby resulting in a larger read delay time of the cell.

4) As shown in fig. 4, the RSP14T circuit proposed by Chunyu pen in 2019 is a schematic structure of the circuit, which uses the source isolation technology, and when the cell stores "1", the stacked PMOS structure connects the transistor P2 with a weak signal "1", so that the drain collecting charge of the transistor P2 will be reduced, the resistance of the node QB to SEU is improved, and the cell becomes more stable.

5) A schematic structure of a Radiation Hardened By Design SRAM bit-cell (RHBD 14T) circuit proposed by Naga Raghuram CH in 2021 is shown in fig. 5. The circuit adopts a polarity reinforcement technology, and reduces the number of sensitive nodes, but leads to larger read-write delay and lower noise margin (SNM) value.

In summary, it is difficult to improve the read-write efficiency of the conventional SRAM memory cell while maintaining the good SEU resistance, resulting in higher power consumption of the SRAM memory cell.

Disclosure of Invention

Based on this, it is necessary to provide a 14T irradiation-resistant SRAM memory cell, and a circuit module, structure and chip based thereon, aiming at the problem that the conventional SRAM memory cell is difficult to achieve both SEU resistance and low power consumption.

The invention is realized by the following technical scheme: A14T irradiation-resistant SRAM memory cell includes 6 NMOS transistors N1-N6 and 8 PMOS transistors P1-P8.

The drain electrode of P1 is electrically connected to the source electrodes of P3 and P6, the drain electrode of P7, and the gates of P2, P6, and N4, respectively, to form a storage node S0. The gate of P1 is electrically connected to the drains of P2 and P8, the sources of P4 and P5, and the gates of P5 and N3, respectively, to form a storage node S1. The sources of P1 and P2 are electrically connected to the power supply VDD. The sources of N1, N2, N3, N4 are electrically grounded. The drains of N1 are electrically connected with the gates of P3 and N2, and the drains of P5 and N5, respectively, to form a storage node Q. The grid electrode of N1 is respectively and electrically connected with the drain electrodes of N2, P6 and N6 and the grid electrode of P4 to form a storage node QB. The gates of N5, N6 are electrically connected to the word line WL. The gates of P7, P8 are electrically connected to word line WLB. The sources of N5, N7 are electrically connected to the bit line BL. The sources of N6, N8 are electrically connected to bit line BLB. The drain of P3 is electrically connected to the drain of N3. The drain of P4 is electrically connected to the drain of N4.

The RHDS-14T anti-irradiation SRAM memory unit is designed by adopting the polarity reinforcing principle that different types of transistors have single turning characteristics under space heavy ion bombardment, so that the stability of redundant memory nodes S0 and S1 is ensured, and the anti-turning capacity of the internal nodes of a circuit is further enhanced. And secondly, the stability of the storage node Q, QB is improved by multiplexing the pull-up PMOS tubes and utilizing a source isolation technology. In the process of writing data, the bit lines write data into the internal nodes Q\QB and S0\S1 through the transmission transistors N5, N6, P7 and P8, so that the storage nodes are easier to write data, the data writing speed and the noise margin of the unit are greatly improved, and the power consumption of the storage unit is reduced.

In one embodiment, the SRAM memory cell is in a hold phase, both the bit line BL and the bit line BLB are precharged to a high level, the word line WL is low, and the word line WLB is high.

In one embodiment, the SRAM memory cell is precharged to a high level for both the bit line BL and the bit line BLB, a high level for the word line WL, and a low level for the word line WLB, with N5, N6, P7, and P8 open during the read phase.

In one embodiment, when the data stored in the SRAM memory cell is '0', then "q=s0=0, qb=s1=1"; the bit line BL discharges to the ground through a discharge path 1 and a discharge path 2, so that the bit line generates a voltage difference, and then data is read out through a sense amplifier; the discharge path 1 discharges to the ground through P7, P3 and N3: the discharge path 2 discharges to the ground through N5 and N1; when the data stored in the SRAM memory cell is '1', then "q=s0=1, qb=s1=0"; the bit line BLB is discharged to the ground through the discharge path 3 and the discharge path 4 so that the bit line generates a voltage difference and then reads out data through the sense amplifier; wherein the discharge path 3 discharges to the ground through P8, P4 and N4; the discharge path 4 discharges to the ground through N6 and N2.

In one embodiment, in the writing stage, the word line WL is high, the word line WLB is low, and when the bit line BL is high and the bit line BLB is low, the '1' is written to the storage node Q point and the S0 point through N5 and P7, respectively; when the bit line BL is at a low level and the bit line BLB is at a high level, '0' is written to the storage node QB and S1 through N6 and P8, respectively.

In one embodiment, the NMOS transistors N1-N6 and the PMOS transistors P1-P8 are 65nm long; wherein, the widths of P1, P2, P5 and P6 are 80nm, and the widths of P3, P4, N1, N2, N3 and N4 are 280nm; all other transistors were 140nm wide.

The invention also provides a circuit module based on the 14T radiation-resistant SRAM memory cell, which adopts the circuit layout of the 14T radiation-resistant SRAM memory cell.

The invention also provides a circuit structure of the 14T radiation-resistant SRAM memory cell, which comprises a plurality of 14T radiation-resistant SRAM memory cells, and a plurality of SRAM memory cell arrays are arranged.

In one embodiment, in the circuit structure, in the SRAM memory cells located in the same row, gates of all N5 and N6 are electrically connected to a word line WL; the grid electrodes of all P7 and P8 are electrically connected with a word line WLB; the sources of all P1 and P2 are electrically connected with a power supply VDD; all sources of N1, N2, N3 and N4 are electrically grounded;

in the SRAM memory cells in the same column, the sources of all N5 and N7 are electrically connected with a bit line BL; the sources of all N6, N8 are electrically connected to bit line BLB.

The invention also provides a circuit chip based on the 14T radiation-resistant SRAM memory cell, which is packaged by adopting the circuit structure based on the 14T radiation-resistant SRAM memory cell.

Compared with the prior art, the invention has the following beneficial effects:

the invention adopts the polarity reinforcing principle that different types of transistors have single turning characteristic under space heavy ion bombardment to design, ensures the stability of redundant storage nodes S0 and S1, and further enhances the anti-turning capability of the nodes in the circuit. And secondly, the stability of the storage node Q, QB is improved by multiplexing the pull-up PMOS tubes and utilizing a source isolation technology. In the process of writing data, the bit lines write data into the internal nodes Q\QB and S0\S1 through the transmission transistors N5, N6, P7 and P8, so that the storage nodes are easier to write data, the data writing speed and the noise margin of the unit are greatly improved, and the power consumption of the storage unit is reduced.

Drawings

FIG. 1 is a schematic diagram of a DICE circuit according to the background of the invention;

FIG. 2 is a schematic diagram of a QUATRO10T circuit in accordance with the background of the invention;

FIG. 3 is a schematic diagram of a SAR14T circuit in the prior art;

FIG. 4 is a schematic diagram of an RSP14T circuit in the background of the invention;

FIG. 5 is a schematic diagram of RHbD14T circuit according to the background of the invention;

FIG. 6 is a schematic diagram of a 14T irradiation-resistant SRAM memory cell in accordance with embodiment 1 of the present invention;

FIG. 7 is a timing waveform diagram of a 14T irradiation-resistant SRAM cell circuit of embodiment 1;

FIG. 8 is a simulation diagram of transient waveforms of the 14T anti-irradiation SRAM memory cell circuit of embodiment 1 of the present invention, wherein different nodes are subjected to pulse injection of a double exponential current source at different times;

FIG. 9 is a HSNM, RSNM, WSNM comparison chart of the SRAM cell of the prior art in example 1 of the present invention and the 14T irradiation-resistant SRAM cell of the present example;

FIG. 10 is a schematic diagram of a circuit module based on a 14T irradiation-resistant SRAM memory cell in accordance with embodiment 2 of the present invention;

fig. 11 is a schematic structural diagram of a circuit structure based on a 14T irradiation-resistant SRAM memory cell according to embodiment 3 of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It is noted that when an element is referred to as being "mounted to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "secured to" another element, it can be directly secured to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or/and" as used herein includes any and all combinations of one or more of the associated listed items.

Example 1

Please refer to fig. 6, which is a schematic diagram illustrating a structure of a 14T irradiation-resistant SRAM memory cell according to the present embodiment. The 14T irradiation-resistant SRAM memory cell includes 6 NMOS transistors N1-N6 and 8 PMOS transistors P1-P8.

Wherein PMOS transistors P1 and P2 are cross-coupled. PMOS transistors P1, P2, P5 and P6 serve as pull-up transistors, PMOS transistors P3 and P4 serve as pull-down transistors, their states being controlled by storage nodes Q and QN, respectively. Transistors P1 and N3, P2 and N4 constitute inverters, respectively, and PMOS transistors P3 and P4 are interposed between the two inverters, respectively. The two main storage nodes Q and QN are electrically connected to the bit line BL and the bit line BLB through the two NMOS transistors N5 and N6, respectively, and the two redundant storage nodes S0 and S1 are electrically connected to the bit line BL and the bit line BLB through the two PMOS transistors P7 and P8, respectively. Wherein, the two NMOS transistors N5, N6 are controlled by the word line WL, and the two PMOS transistors P7 and P8 are controlled by the word line WLB.

The connection relationship between the transistors of the SRAM memory cell is specifically as follows:

the drain electrode of P1 is electrically connected to the source electrodes of P3 and P6, the drain electrode of P7, and the gates of P2, P6, and N4, respectively, to form a storage node S0. The gate of P1 is electrically connected to the drains of P2 and P8, the sources of P4 and P5, and the gates of P5 and N3, respectively, to form a storage node S1. The sources of P1 and P2 are electrically connected to the power supply VDD. The sources of N1, N2, N3, N4 are electrically grounded. The drains of N1 are electrically connected with the gates of P3 and N2, and the drains of P5 and N5, respectively, to form a storage node Q. The grid electrode of N1 is respectively and electrically connected with the drain electrodes of N2, P6 and N6 and the grid electrode of P4 to form a storage node QB. The gates of N5, N6 are electrically connected to the word line WL. The gates of P7, P8 are electrically connected to word line WLB. The sources of N5, N7 are electrically connected to the bit line BL. The sources of N6, N8 are electrically connected to bit line BLB. The drain of P3 is electrically connected to the drain of N3. The drain of P4 is electrically connected to the drain of N4.

Specifically, in the present embodiment, the circuit connection relationship of the 14T irradiation-resistant SRAM cell can be summarized as:

bit line BL is electrically connected to the sources of pass transistors N5 and P7. Bit line BLB is electrically connected to the sources of transistors N6 and P8. The word line WL is electrically connected to the gates of pass transistors N5 and N6. Word line WLB is electrically connected to the gates of pass transistors P7 and P8. The power supply VDD is electrically connected to the sources of the PMOS transistors P1 and P2. The sources of the NMOS transistors N1, N2, N3, N4 are electrically grounded.

The drain of the PMOS transistor P1 is electrically connected to the sources of the PMOS transistors P3 and P6, the gates of the PMOS transistors P2 and P6, and the gate of the NMOS transistor N4, and the gate of the PMOS transistor P1 is electrically connected to the drain of the PMOS transistor P2, the sources of the PMOS transistors P4 and P5, the gate of the PMOS transistor P5, and the gate of the NMOS transistor N3.

The drain of the PMOS transistor P2 is electrically connected to the sources of the PMOS transistors P4 and P5, the gates of the PMOS transistors P1 and P5, and the gate of the NMOS transistor N3, and the gate of the PMOS transistor P2 is electrically connected to the drain of the PMOS transistor P1, the sources of the PMOS transistors P3 and P6, the gate of the PMOS transistor P6, and the gate of the NMOS transistor N4.

The drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N3, and the gate of the PMOS transistor P3 is electrically connected to the gate of the NMOS transistor N2, the drain of the NMOS transistor N1, and the drain of the PMOS transistor P5.

The drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N4, and the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N1, the drain of the NMOS transistor N2, and the drain of the PMOS transistor P6.

The source of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P2, the source of the PMOS transistor P4, the gates of the PMOS transistors P1 and P5, and the gate of the NMOS transistor N3, the gate of the PMOS transistor P5 is electrically connected to the sources of the PMOS transistors P4 and P5, the gate of the PMOS transistor P1, and the gate of the NMOS transistor N3, and the drain of the PMOS transistor P5 is electrically connected to the gate of the NMOS transistor N2, the drain of the NMOS transistor N1, and the gate of the PMOS transistor P3.

The source of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P3, the drain of the PMOS transistor P1, the gates of the PMOS transistors P2 and P6, and the gate of the NMOS transistor N4, the gate of the PMOS transistor P6 is electrically connected to the sources of the PMOS transistors P3 and P6, the drain of the PMOS transistor P1, the gate of the PMOS transistor P2, and the gate of the NMOS transistor N4, and the drain of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N1, the drain of the NMOS transistor N2, and the gate of the PMOS transistor P4.

The drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P5, the gate of the PMOS transistor P3, and the gate of the NMOS transistor N2, and the gate of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N2, the drain of the PMOS transistor P6, and the gate of the PMOS transistor P4.

The drain of the NMOS transistor N2 is electrically connected to the gate of the NMOS transistor N1, the gate of the PMOS transistor P4, and the drain of the PMOS transistor P6, and the gate of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N1, the drain of the PMOS transistor P5, and the gate of the PMOS transistor P3.

The drain of the NMOS transistor N3 is electrically connected to the drain of the PMOS transistor P3, and the gate of the NMOS transistor N3 is electrically connected to the sources of the PMOS transistors P4 and P5, the gates of the PMOS transistors P1, P5, and the drain of the PMOS transistor P2.

The drain of the NMOS transistor N4 is electrically connected to the drain of the PMOS transistor P4, and the gates of the NMOS transistor N4, the PMOS transistors P3 and P6, the gates of the PMOS transistors P2, P6, and the drain of the PMOS transistor P1 are electrically connected.

The drain of the pass transistor N5 is electrically connected to the drain of the NMOS transistor N1. The drain of the pass transistor N6 is electrically connected to the drain of the NMOS transistor N2. The drain of the pass transistor P7 is electrically connected to the drain of the PMOS transistor P1. The drain of the pass transistor P8 is electrically connected to the drain of the PMOS transistor P2.

Please refer to fig. 7, which is a timing waveform diagram of the 14T irradiation-resistant SRAM memory cell circuit of the present embodiment. Wherein, the simulation conditions are: corner: TT; temperature:27 ℃; VDD:1.2V. The principle of the RHDS-14T irradiation-resistant SRAM memory cell of the embodiment is as follows:

in the hold phase, both bit line BL and bit line BLB are precharged to a high level, word line WL is low, word line WLB is high, and the circuit is held in an initial state and does not operate.

When both bit line BL and bit line BLB are precharged to a high level during the read data phase, word line WL is high, word line WLB is low, and pass transistors N5, N6, P7 and P8 are open. If the data stored in the SRAM memory cell is '0', then "q=s0=0, qb=s1=1", then BL is discharged to ground through the discharge path 1 and the discharge path 2, so that the bit line generates a voltage difference, and then the data is read out through the sense amplifier. Wherein, the discharge path 1 is: and discharge to ground through transistors P7, P3 and N3. The discharge path 2 is: and discharged to ground through transistors N5, N1. If the data stored in the SRAM memory cell is '1', then "q=s0=1, qb=s1=0". Then BLB is discharged to ground through discharge path 3 and discharge path 4 so that the bit lines generate a voltage difference and then data is read out through the sense amplifier. Wherein, the discharge path 3 is: and discharge to ground through transistors P8, P4 and N4. The discharge path 4 is: and discharged to ground through transistors N6, N2.

In the write data phase, the word line WL is high and the word line WLB is low. If the bit line BL is high and the bit line BLB is low, then '1' is written to storage nodes Q and S0 through pass transistors N5 and P7, respectively. If the bit line BL is low and the bit line BLB is high, a '1' is written to the storage nodes QB and S1 through the pass transistors N6 and P8, respectively. In the writing process, since data is written into the internal nodes q\s0 and qb\s1 through the transmission transistors N5 and P7 and N6 and P8 at the same time, the storage node is easier to be written with data, the writing speed is greatly improved, and meanwhile, the power consumption of the circuit is reduced due to the great improvement of the writing speed.

As shown in fig. 7, the 14T irradiation-resistant SRAM memory cell of the present embodiment can still perform read and write operations normally even if the voltages of the bit line BL and the bit line BLB are bombarded by single particles, and can be restored to the initial state by the node Q, QB even if the storage nodes S0 and S1 are flipped.

Please refer to fig. 8, which is a schematic diagram of a transient waveform of the 14T anti-irradiation SRAM memory cell circuit of the present embodiment, in which different nodes are subjected to pulse injection of a dual exponential current source at different times. Wherein, the simulation conditions are: corner: TT; temperature:27 ℃; VDD:1.2V.

When only considering the improvement of the irradiation resistance of the circuit structure, if the storage nodes of the circuit are bombarded by particles, as the storage nodes S0 and S1 are surrounded by PMOS transistors, according to the polarity reinforcing principle, the space particles bombard the PMOS transistors of the sensitive nodes, and only a voltage pulse of 0-1 is generated at the nodes, and the state of other transistors cannot be influenced by the pulse due to the existence of the gate capacitor, so that the external nodes S0 and S1 are effectively prevented from overturning. Meanwhile, the stability of the S0 and S1 node data ensures that the internal storage nodes Q and QB can be restored to the initial state after being overturned, so that the SEU resistance of the circuit is improved. The storage nodes Q and QB are reinforced by a source isolation technology, so that the SEU resistance of the circuit is improved. If other non-critical nodes are bombarded with particles, the memory cell is less susceptible.

Simulation verification

1. Simulation conditions

The simulation conditions are as follows: comer: TT; temperature:27 ℃; VDD:1.2V.

2. Simulation object

Control group: DICE circuit, QUATRO10T circuit, SAR14T circuit, RSP14T circuit, RHBDL4T circuit.

Experimental group: the RHDS-14T irradiation-resistant SRAM memory cell (RHDS-14T circuit) of the present embodiment.

3. Simulation process and simulation result

Five circuits in the control group and the circuit in the experimental group are respectively connected into VDD of 1.2V, then read operation and write operation are respectively carried out, corresponding delay time, power consumption and critical charge are recorded, simulation results are shown in table 1 and table 2, table 1 is a circuit area, read-write time and power consumption simulation comparison table of the SRAM memory cell in the prior art and the 14T anti-irradiation SRAM memory cell in the embodiment, and table 2 is a critical charge comparison table of the SRAM memory cell in the prior art and the 14T anti-irradiation SRAM memory cell in the embodiment.

TABLE 1

Unit cell	Area (μm) 2 )	Reading delay (ps)	Write delay (ps)	Power consumption (mu W)
					DICE	8.97	24.97	31.4	8
Quatro	7.48	252.4	48.48	7.664
					SAR14T	11.03	19.5	30.97	7.968
RSP14T	10.96	21.1	32	7.928
					RHBD14T	9.85	61.4	36.3	7.84
RHDS-14T	10.44	31.56	24	6.8

TABLE 2

As can be seen from table 1, the write delay of the rhds→14t irradiation-resistant SRAM memory cell of the present embodiment is significantly lower than that of the other five circuits, and the power consumption is also lower than that of the other five circuits. As can be seen from table 2, the critical charge of the RHDS-14T irradiation-resistant SRAM memory cell and the critical charge of the dic circuit, the SAR14T circuit, and the RHBD14T circuit in this embodiment are all higher than 50fC, that is, the RHDS-14T irradiation-resistant SRAM memory cell can not generate single event upset in an environment lower than 50fC, and has a strong SEU resistance.

Please refer to fig. 9, which is a HSNM, RSNM, WSNM comparison diagram of the SRAM memory cell of the prior art in embodiment 1 of the present invention and the 14T irradiation-resistant SRAM memory cell of the present embodiment. As can be seen from fig. 9, the 14T irradiation-resistant SRAM memory cell of the present embodiment has a higher noise margin (SNM) compared to the conventional SRAM memory cell.

Therefore, the RHDS-14T anti-irradiation SRAM memory cell provided by the embodiment can improve the SEU resistance of the SRAM memory cell circuit, greatly improve the speed of the cell under the condition of sacrificing a smaller cell area, and reduce the power consumption of the SRAM memory cell.

Example 2

To realize the application of the 14T irradiation-resistant SRAM memory cell of embodiment 1, the present embodiment provides a circuit module based on the 14T irradiation-resistant SRAM memory cell. Please refer to fig. 10, which is a schematic diagram of a circuit module based on a 14T irradiation-resistant SRAM memory cell of the present embodiment. The circuit module employs the circuit layout of the 14T irradiation-resistant SRAM memory cell in embodiment 1. Specifically, the circuit module includes 6 connection terminals.

The first connection terminal 1 is electrically connected to the word line WL through gates of N5 and N6. The second connection terminal 2 is electrically connected to the word line WLB through the gates of P7, P8. The third connection terminal 3 is electrically connected to the power supply VDD through the sources of P1 and P2. The fourth connection terminal 4 is electrically grounded through the sources of N1, N2, N3, N4. The fifth connection terminal 5 is electrically connected to the bit line BL through the sources of N5, N7. The sixth connection terminal 6 is electrically connected to the bit line BLB through the sources of N6, N8.

Example 3

The embodiment provides a circuit structure of an SRAM memory cell based on 14T irradiation resistance. Please refer to fig. 11, which is a schematic diagram of a circuit structure based on a 14T irradiation-resistant SRAM memory cell according to the present embodiment. In FIG. 11, the RHDS-14T cell is a 14T irradiation-resistant SRAM memory cell. The circuit structure comprises a plurality of 14T radiation-resistant SRAM memory cells provided in embodiment 1, and a plurality of SRAM memory cell arrays are arranged to realize the integrated application of the SRAM memory cells.

In the circuit structure of the present embodiment, in the SRAM memory cells in the same row, the gates of all N5 and N6 are electrically connected to the word line WL. The gates of all P7, P8 are electrically connected to word line WLB. The sources of all P1 and P2 are electrically connected to the power supply VDD. All sources of N1, N2, N3, N4 are electrically grounded. That is, the SRAM memory cells of the same row are controlled by the same word line WL and the same word line WLB.

In the SRAM memory cells in the same column, the sources of all N5 and N7 are electrically connected to the bit line BL. The sources of all N6, N8 are electrically connected to bit line BLB. I.e. the SRAM memory cells of the same column are controlled by the same bit line BL and the same bit line BLB.

Example 4

The embodiment provides a circuit chip based on a 14T irradiation-resistant SRAM memory cell. The circuit chip is packaged by adopting the circuit structure of the 14T radiation-resistant SRAM memory cell in the embodiment 3. The packaging into a chip mode is easier to popularize and apply the 14T radiation-resistant SRAM memory cell.

In the circuit chip of the present embodiment, the gates of all N5 and N6 are electrically connected to the word line WL in the SRAM memory cells located in the same row, thereby leading out the first pin. The gates of all P7, P8 are electrically connected to word line WLB, thereby leading out the second pin. The sources of all P1 and P2 are electrically connected with the power supply VDD, thereby leading out the third pin. All sources of N1, N2, N3 and N4 are electrically grounded, so that a fourth pin is led out.

The sources of all N5 and N7 of the SRAM memory cells in the same column are electrically connected with the bit line BL, so that a fifth pin is led out. The sources of all N6, N8 are electrically connected to the bit line BLB, thereby extracting the sixth pin.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1. A 14T irradiation-resistant SRAM memory cell comprising 6 NMOS transistors N1-N6 and 8 PMOS transistors P1-P8;

the drain electrode of P1 is respectively and electrically connected with the source electrodes of P3 and P6, the drain electrode of P7 and the grid electrodes of P2, P6 and N4 to form a storage node S0;

the grid electrode of P1 is respectively and electrically connected with the drain electrodes of P2 and P8, the source electrodes of P4 and P5 and the grid electrodes of P5 and N3 to form a storage node S1;

the sources of P1 and P2 are electrically connected with a power supply VDD;

the sources of N1, N2, N3 and N4 are electrically grounded;

the drain electrode of N1 is electrically connected with the drain electrodes of P3 and N2 and the drain electrodes of P5 and N5 respectively to form a storage node Q;

the grid electrode of N1 is respectively and electrically connected with the drain electrodes of N2, P6 and N6 and the grid electrode of P4 to form a storage node QB;

the grid electrodes of N5 and N6 are electrically connected with a word line WL;

the gates of P7 and P8 are electrically connected with a word line WLB;

the sources of N5 and N7 are electrically connected with the bit line BL;

sources of N6, N8 are electrically connected to bit line BLB;

the drain electrode of the P3 is electrically connected with the drain electrode of the N3; the drain of P4 is electrically connected to the drain of N4.

2. The 14T irradiation resistant SRAM memory cell of claim 1, wherein said SRAM memory cell is precharged to a high level for both said bit line BL and said bit line BLB, a low level for said word line WL, and a high level for said word line WLB during a hold phase.

3. The 14T irradiation resistant SRAM cell of claim 1, wherein during a read phase, said SRAM cell is precharged to a high level for both said bit line BL and said bit line BLB, a high level for said word line WL, a low level for said word line WLB, and open for N5, N6, P7 and P8.

4. The 14T irradiation resistant SRAM cell of claim 3, wherein when said SRAM cell stores data of '0', then "q=s0=0, qb=s1=1"; the bit line BL discharges to the ground through a discharge path 1 and a discharge path 2, so that the bit line generates a voltage difference, and then data is read out through a sense amplifier; the discharge path 1 discharges to the ground through P7, P3 and N3: the discharge path 2 discharges to the ground through N5 and N1; when the data stored in the SRAM memory cell is '1', then "q=s0=1, qb=s1=0"; the bit line BLB is discharged to the ground through the discharge path 3 and the discharge path 4 so that the bit line generates a voltage difference and then reads out data through the sense amplifier; wherein the discharge path 3 discharges to the ground through P8, P4 and N4; the discharge path 4 discharges to the ground through N6 and N2.

5. The 14T irradiation-resistant SRAM memory cell of claim 1, wherein said SRAM memory cell is in a write phase, word line WL is high, word line WLB is low, and when said bit line BL is high and BLB is low, writing '1' to storage node Q and S0 through N5 and P7, respectively; when the bit line BL is at a low level and the bit line BLB is at a high level, '0' is written to the storage node QB and S1 through N6 and P8, respectively.

6. The 14T irradiation resistant SRAM memory cell of claim 1 wherein NMOS transistors N1-N6 and PMOS transistors P1-P8 are each 65nm long; wherein, the widths of P1, P2, P5 and P6 are 80nm, and the widths of P3, P4, N1, N2, N3 and N4 are 280nm; all other transistors were 140nm wide.

7. A circuit module based on 14T irradiation-resistant SRAM memory cells, characterized in that it employs a circuit layout of 14T irradiation-resistant SRAM memory cells as claimed in any one of claims 1 to 6.

8. A circuit structure based on 14T irradiation-resistant SRAM memory cells, characterized in that it comprises a plurality of 14T irradiation-resistant SRAM memory cells as claimed in any one of claims 1 to 6, a plurality of said SRAM memory cell arrays being arranged.

9. The circuit structure of the 14T irradiation-resistant SRAM memory cell of claim 8, wherein in the SRAM memory cells located in the same row, gates of all N5 and N6 are electrically connected to a word line WL; the grid electrodes of all P7 and P8 are electrically connected with a word line WLB; the sources of all P1 and P2 are electrically connected with a power supply VDD; all sources of N1, N2, N3 and N4 are electrically grounded;

in the SRAM memory cells in the same column, the sources of all N5 and N7 are electrically connected with a bit line BL; the sources of all N6, N8 are electrically connected to bit line BLB.

10. A circuit chip based on a 14T irradiation-resistant SRAM memory cell, characterized in that it is packaged by adopting the circuit structure based on a 14T irradiation-resistant SRAM memory cell as claimed in any one of claims 8 to 9.