CN111141397B - Nonuniformity correction circuit for APD detector array - Google Patents
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Abstract
The invention discloses a non-uniformity correction circuit facing an APD detector array, which comprises: the APD array module is used for carrying out current induction and shaping processing on the second input signal after resetting according to the first input signal to obtain a first digital signal; the reference module is used for carrying out current induction and shaping processing on the fourth input signal after resetting according to the third input signal to obtain a second digital signal; the phase discriminator is connected with the APD array module and the reference module and used for comparing the phase difference of the first digital signal and the second digital signal to obtain a first phase difference signal and a second phase difference signal; and the charge pump is connected with the phase discriminator and used for charging and discharging the charge pump according to the first phase difference signal and the second phase difference signal to obtain a first processing signal. The reference module is used as the standard response speed corresponding to the single photon response speed in the APD array module, so that the response speed of the APD array module is consistent with that of the reference module, and the problem of non-uniformity of the APD array in the traditional APD detector is solved.
Description
Technical Field
The invention belongs to the technical field of APD detectors, and particularly relates to a non-uniformity correction circuit for an APD detector array.
Background
An Avalanche Photodiode (APD for short) working in a Geiger mode can quickly detect and respond to single photon signals, has the characteristics of small volume, high gain, high sensitivity and the like, and is widely applied to the fields of optical communication, medical detection, military investigation, automobile radar and the like.
In recent years, a single photon detection technology based on an APD array has made great research progress, however, limited by a preparation process and an application environment, uniformity of APD pixels in an area array is difficult to keep consistent, even if each APD pixel has the same external bias voltage and the same illumination, photocurrent generated by single photon response for avalanche is different, so that response speeds of APD interface circuits are different, output digital pulses generate corresponding phase differences, and non-uniformity of the APD array has a serious influence on detection accuracy. Therefore, the problem of array uniformity becomes one of the important research directions of the APD detector, and in practical application, it should be ensured that each APD pixel in the APD array has consistent input and output characteristics as much as possible. To address the non-uniformity of APD arrays, there are two conventional approaches: the first is from the design and process manufacturing angle of APD device, the second is that external DSP/FPGA adopts algorithm adjustment.
However, the first method cannot completely avoid the non-uniformity, and the second method can solve the non-uniformity problem of the APD array, but the system is large in size, high in power consumption and not easy to integrate due to the addition of the DSP/FPGA.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a non-uniformity correction circuit for an APD detector array.
The embodiment of the invention provides a non-uniformity correction circuit facing an APD detector array, which comprises:
an APD array module, a reference module, a phase discriminator and a charge pump, wherein,
the APD array module is used for carrying out current induction and shaping processing on a second input signal after carrying out reset processing according to a first input signal to obtain a first digital signal;
the reference module is used for carrying out current induction and shaping processing on a fourth input signal after carrying out reset processing according to a third input signal to obtain a second digital signal;
the phase discriminator is connected with the APD array module and the reference module and used for comparing the phase difference between the first digital signal and the second digital signal to obtain a first phase difference signal and a second phase difference signal;
the charge pump is connected with the phase discriminator and used for carrying out charge-discharge processing on the charge pump according to the first phase difference signal and the second phase difference signal to obtain a first processing signal.
In an embodiment of the present invention, the charge pump is further connected to the APD array module, and is configured to input the first processing signal to the APD array module.
In one embodiment of the invention, the apparatus further comprises an inverted bias voltage adjustment module, wherein,
the reverse bias voltage adjusting module is connected to the charge pump and the APD array module, and is configured to buffer the first processing signal to obtain a second processing signal, and input the second processing signal to the APD array module.
In one embodiment of the present invention, the APD array module includes a number of APD array cells, each APD array cell including a first current sensing module, a first pulse shaping module, wherein,
the first current sensing module is used for carrying out current sensing processing on the second input signal after carrying out reset processing according to the first input signal to obtain a first induced current signal;
the first pulse shaping module is connected with the first current sensing module and the phase discriminator, and is used for rectifying the first induced current signal to obtain the first digital signal and inputting the first digital signal to the phase discriminator.
In one embodiment of the invention, the reference module comprises a second current sensing module, a second pulse shaping module, wherein,
the second current sensing module is used for carrying out current sensing processing on the fourth input signal after carrying out reset processing according to the third input signal to obtain a second induced current signal;
the second pulse shaping module is connected with the second current sensing module and the phase detector, and is used for rectifying the second sensing current signal to obtain a second digital signal and inputting the second digital signal to the phase detector.
In one embodiment of the invention, the phase detector is a dynamic phase detector.
In one embodiment of the invention, the reverse bias voltage adjustment module comprises a start-up circuit, a bias circuit, and a buffer circuit, wherein,
the starting circuit is used for self-starting to generate a self-starting signal;
the bias circuit is connected with the starting circuit and used for generating a bias voltage signal according to the self-starting signal;
the buffer circuit is connected to the bias circuit, the charge pump and the APD array module, and configured to buffer the first processing signal according to the bias voltage signal to obtain the second processing signal, and input the second processing signal to the APD array module.
Compared with the prior art, the invention has the beneficial effects that:
the reference module is used as a standard response speed corresponding to the single photon response speed in the APD array module, so that the response speed of each APD array unit in the APD array module is consistent with the response speed of the reference module, and the problem of non-uniformity of an APD array in a traditional APD detector is solved; the correction circuit of the invention is composed of modules such as a phase discriminator, a charge pump and the like, has small system scale and low power consumption, can realize monolithic integration with a large array APD, and provides an effective technical approach for single photon detection.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic structural diagram of a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a non-uniformity correction circuit for an APD detector array according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a non-uniformity correction circuit for an APD detector array according to another embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of an APD array unit in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a reference module in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of a phase detector in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
FIG. 8 is a schematic circuit diagram of a charge pump in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
FIG. 9 is a schematic circuit diagram of an inverse bias voltage adjustment module in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
FIG. 10 is a diagram illustrating simulation results of APD array unit outputs in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
fig. 11 is a schematic diagram showing comparison of simulation results output by an APD array unit and a reference module in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
FIG. 12 is a diagram illustrating simulation results of the output of a charge pump in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention;
fig. 13 is a schematic diagram of a simulation result output by the APD array unit and the reference module after passing through the reverse bias voltage adjusting module in the non-uniformity correction circuit for the APD detector array according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention. The present embodiment provides a non-uniformity correction circuit for an APD detector array, the correction circuit including an APD array module, a reference module, a phase detector, and a charge pump, wherein,
the APD array module is used for carrying out current induction and shaping processing on the second input signal after carrying out reset processing according to the first input signal to obtain a first digital signal;
the reference module is used for carrying out current induction and shaping processing on the fourth input signal after carrying out reset processing according to the third input signal to obtain a second digital signal;
the phase discriminator is connected with the APD array module and the reference module and used for comparing the phase difference between the first digital signal and the second digital signal to obtain a first phase difference signal and a second phase difference signal;
and the charge pump is connected with the phase discriminator and used for carrying out charge-discharge processing on the charge pump according to the first phase difference signal and the second phase difference signal to obtain a first processing signal.
Further, the charge pump of this embodiment is further connected to the APD array module, and configured to input the first processing signal to the APD array module.
Specifically, at present, uniformity of APD pixels in an area array is difficult to be kept consistent, and in order to solve the problem of non-uniformity of the APD array, there are two conventional methods: the first is from the design and process manufacturing angle of APD device, the second is that external DSP/FPGA adopts algorithm adjustment. However, the first method cannot completely avoid the non-uniformity, and the second method can solve the non-uniformity problem of the APD array, but the system is large in size, high in power consumption and not easy to integrate due to the addition of the DSP/FPGA.
Based on the above existing problems, the present embodiment provides a non-uniformity correction circuit facing an APD detector array, wherein an APD array module of the present embodiment includes a plurality of APD array units, one APD array unit is selected from the APD array units as a reference module, a single photon response speed in the reference module is used as a standard response speed, and as long as the response speeds of other APD array units in the APD array module are adjusted to be consistent with the response speed of the reference module, the non-uniformity problem of the conventional APD array can be solved. Specifically, in this embodiment, each APD array cell first performs reset processing according to a first input signal Vreset, then performs current sensing and shaping processing on a second input signal Vphoton to output a first digital signal V1, the reference module first performs reset processing according to a third input signal Vreset1, then performs current sensing and shaping processing on a fourth input signal Vphoton1 to output a second digital signal V2, and inputs the first digital signal V1 and the second digital signal V2 to the phase discriminator, and obtains a digital pulse phase difference between the first digital signal V1 and the second digital signal V2 through the phase discriminator, where the digital pulse phase difference includes a first phase difference signal VUP and a second phase difference signal VDN, and then the phase discriminator transmits the first phase difference signal VUP and the second phase difference signal V2 to the charge pump, controls charging and discharging of an output capacitor of the charge pump, and outputs a first processed Vout signal, and feeding back the first processing signal Vout to the APD array module. In the present embodiment, the first input signal Vreset and the third input signal Vreset1 are both reset signals, preferably, the first input signal Vreset and the third input signal Vreset1 are reset signals generated in synchronization, and the second input signal vpHOton and the fourth input signal vpHOton1 are both single-photon signals. In the embodiment, the reference module is used as a standard response speed corresponding to a single photon response speed in the APD array module, so that the response speed of each APD array unit in the APD array module is consistent with the response speed of the reference module, and the problem of non-uniformity of an APD array in a traditional APD detector is solved.
In this embodiment, the first digital signal V1 output by each APD array unit and the second digital signal V2 output by the reference module are simultaneously input to the phase detector for phase comparison, and the phases of the first digital signal V1 and the second digital signal V2 are compared to output the corresponding first phase difference signal VUP and the second phase difference signal VDN. For example, the first digital signal V1 input by the phase detector leads the second digital signal V2 by 0.1 cycle, the first phase difference signal VUP output by the phase detector outputs a high level in the corresponding 0.1 cycle, and the second digital signal V2 output by the phase detector keeps a low level unchanged; similarly, if the second digital signal V2 input by the phase detector leads the first digital signal V1 by 0.1 period, the second digital signal V2 output by the phase detector outputs a high level within the corresponding 0.1 period, and the first phase difference signal VUP output by the phase detector keeps the low level unchanged.
Preferably, the phase detector is a dynamic phase detector.
The input signal of the charge pump controls charging and discharging of a load capacitor of the charge pump, specifically, the first phase difference signal VUP and the second phase difference signal VDN control charging and discharging of the load capacitor of the charge pump, when the first phase difference signal VUP is at a high level, the load capacitor is charged, a first processing signal Vout is output, when the second phase difference signal VDN is at a high level, the load capacitor is discharged, the first processing signal Vout is output, when the first phase difference signal VUP and the second phase difference signal VDN are at a high level or a low level, the load capacitor is neither charged nor discharged, and the output voltage keeps the last first processing signal Vout unchanged. The charge pump can effectively overcome the problem of mismatching between a current source and a current drain caused by charge sharing and channel modulation.
The correction circuit of the embodiment is composed of modules such as a phase discriminator, a charge pump and the like, has small system scale and low power consumption, can realize monolithic integration with a large array APD, and provides an effective technical approach for single photon detection.
Further, referring to fig. 2, fig. 2 is a schematic structural diagram of another non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention. The APD array module of this embodiment includes a plurality of APD array units, each APD array unit includes a first current sensing module and a first pulse shaping module.
Specifically, in this embodiment, the first current sensing module is configured to perform a reset process on the first input signal Vreset and then perform a current sensing process on the second input signal vphot to obtain a first sensing current signal. When a single photon signal (a second input signal vphot) is detected inside the APD array module, an avalanche photocurrent is generated and input to the first current sensing module, and the first current sensing module outputs a high level and feeds back to an anode inside the APD array module to complete quenching and resetting.
The first pulse shaping module is connected with the first current sensing module and the phase detector, and is used for rectifying the first sensing current signal to obtain a first digital signal V1 and inputting the first digital signal V1 into the phase detector. Since the output of the first current sensing module is not a standard digital pulse and cannot meet the requirement of a subsequent circuit on digital signal processing, the first pulse shaping module is added to shape the output of the first current sensing module in the present embodiment, so that the first pulse shaping module inputs a non-standard digital pulse and outputs a standard digital pulse, that is, the first digital signal V1.
Further, the reference module comprises a second current sensing module and a second pulse shaping module.
Specifically, referring to fig. 2 again, in the present embodiment, the second current sensing module is configured to perform a reset process on the third input signal Vreset1 and then perform a current sensing process on the fourth input signal Vphoton1 to obtain a second sensing current signal. When a single photon signal (a fourth input signal vphot 1) is detected inside the APD array module, the avalanche photocurrent is generated and input to the second current sensing module, and the second current sensing module outputs a high level and feeds back to the anode inside the reference module to complete quenching and resetting. Preferably, the first current sensing module and the second current sensing module are implemented in the same circuit.
And the second pulse shaping module is connected with the second current sensing module and the phase detector, and is used for rectifying the second sensing current signal to obtain a second digital signal V2 and inputting the second digital signal V2 into the phase detector. Like the second pulse shaping module, because the output of the second current sensing module is not a standard digital pulse, and cannot meet the requirement of a subsequent circuit on digital signal processing, the second pulse shaping module is added to shape the output of the second current sensing module, so that the second pulse shaping module inputs a non-standard digital pulse and outputs a standard digital pulse, namely, a second digital signal V2. Preferably, the first pulse shaping module and the second pulse shaping module are implemented identically.
In summary, in the present embodiment, the reference module is used as a flag response speed corresponding to a single photon response speed in the APD array module, so that the response speed of each APD array unit in the APD array module is consistent with the response speed of the reference module, thereby solving the non-uniformity problem of the APD array in the conventional APD detector; the correction circuit of the embodiment is composed of modules such as a phase discriminator and a charge pump, has small system scale and low power consumption, can realize monolithic integration with a large array APD, and provides an effective technical approach for single photon detection.
Example two
On the basis of the first embodiment, please refer to fig. 3, and fig. 3 is a schematic structural diagram of another non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention, it can be seen that the present embodiment further includes an inverse bias voltage adjusting module on the basis of the non-uniformity correction circuit for an APD detector array according to the first embodiment.
Specifically, the reverse bias voltage adjusting module in this embodiment is connected to the charge pump and the APD array module, and configured to buffer the first processing signal to obtain the second processing signal Vo, and input the second processing signal to the APD array module. Since the first processing signal Vout output by the charge pump has no large-current driving capability, if the output voltage of the charge pump is directly connected to the anode of the APD array unit, the output voltage of the charge pump may vary with the current of the APD anode, and the APD array unit has no stability and cannot be accurately adjusted in terms of the anode potential. This process is a negative feedback mechanism, and the feedback system is stable until the phase difference between the first digital signal V1 output by each APD array cell and the second digital signal V2 output by the reference module is zero.
Further, referring to fig. 4, fig. 4 is a schematic structural diagram of another non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention, which includes a start circuit of an inverse bias voltage adjustment module, a bias circuit, and a buffer circuit.
Specifically, the start circuit of the present embodiment is used for self-starting to generate a self-starting signal. The starting circuit can accelerate the process of electrifying the interior of the subsequent circuit, so that the output of the subsequent circuit is quickly stabilized.
The bias circuit is connected with the starting circuit and used for quickly generating a bias voltage signal according to the self-starting signal. The bias circuit provides stable bias voltage for the subsequent circuit, and ensures that the subsequent circuit has good power supply rejection ratio.
The buffer circuit is connected with the bias circuit, the charge pump and the APD array module, and is used for buffering the first processing signal Vout according to the bias voltage signal to obtain a second processing signal Vo, and inputting the second processing signal Vo to the APD array module. Specifically, the present embodiment adopts a connection form of unity gain negative feedback to form a buffer stage, in the connection of unity gain negative feedback, the inverting terminal is connected to the output terminal, the non-inverting terminal is connected to the output signal terminal of the charge pump, the output terminal of the buffer circuit is connected to the anode of each APD array unit in the APD array module, and the buffer circuit has a capability of driving a large current, so that the anode potential of the APD array unit can be accurately and stably adjusted.
In this embodiment, a negative feedback adjustment mechanism is utilized, a method of matching a reference module with each APD array unit in an APD array module is adopted, and then, the capacitor voltage output by the charge pump is adjusted by the reverse bias adjustment module and then fed back to the anode of the APD array unit, so that the anode potential of the APD array unit is adaptively adjusted, the consistency of the output characteristics of the APD array unit is ensured, the phase difference between the APD array unit and the reference module is zero, and the feedback system is stable.
The present embodiment can implement the embodiments in the first embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.
EXAMPLE III
On the basis of the second embodiment, the following detailed design is performed on the circuits of each APD array unit, the reference module, the phase discriminator, the charge pump, and the reverse bias voltage adjusting module in the APD array module, but not limited to this design, which further illustrates that the non-uniformity correction circuit for the APD detector array provided in this embodiment can solve the problem of non-uniformity of the conventional APD array, and meanwhile, the correction circuit in this embodiment is composed of modules such as the phase discriminator and the charge pump, and has small system scale and low power consumption, and can implement monolithic integration with a large array APD, specifically:
referring to fig. 5, fig. 5 is a schematic circuit diagram of an APD array cell in a non-uniformity correction circuit facing an APD detector array according to an embodiment of the present invention, in this embodiment, each APD array cell in an APD array module includes an APD detector D1, a transistor Mn1, a transistor Mn2, a transistor Mp1, a comparator comp1, an inverter INV1, and an inverter INV2, wherein,
the cathode of the APD detector D1 is connected to Vpower1, the anode of the APD detector D1 is connected to the drain of the transistor Mn1, the drain of the transistor Mp1, the drain of the transistor Mn2 and the positive input terminal of the comparator comp1, the gate of the transistor Mn1 is connected to the signal input terminal of the first input signal, the source of the transistor Mn1, the source of the transistor Mn2 and the negative input terminal of the comparator comp1 are connected to Vf1, the gate of the transistor Mn2 is connected to the output terminal of the inverter INV1, the source of the transistor Mp1 is connected to Vdd1, the gate of the transistor Mp1 is connected to the output terminal of the inverter INV1, the output terminal of the comparator comp1 is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is also connected to the input terminal of the inverter INV2, and the output terminal of the inverter INV2 is connected to the first. The transistor Mn1 and the transistor Mn2 are a reset transistor and a holding transistor respectively, the transistor Mp1 is a quenching transistor, current sensing is realized by charging a parasitic capacitor at the node X, the comparator comp1 can accelerate avalanche current sensing speed, and finally a signal output by the first current sensing module is shaped by the inverter INV1 and the inverter INV2, so that a standard digital signal, namely a first digital signal V1, is output.
Preferably, the transistors Mn1 and Mn2 are N-type MOS transistors, and the transistor Mp1 is a P-type MOS transistor.
Referring to fig. 6, fig. 6 is a schematic circuit diagram of a reference module in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention. In this embodiment, the reference module comprises an APD detector D2, a transistor Mn3, a transistor Mn4, a transistor Mp2, a comparator comp2, an inverter INV3, an inverter INV4, the cathode of the APD detector D2 is connected to Vpower2, the anode of the APD detector D2 is connected to the drain of the transistor Mn3, the drain of the transistor Mp2, the drain of the transistor Mn4 and the positive input terminal of the comparator comp2, the gate of the transistor Mn3 is connected to the signal input terminal of the first input signal, the source of the transistor Mn3, the source of the transistor Mn4 and the negative input terminal of the comparator comp2 are connected to Vf2, the gate of the transistor Mn4 is connected to the output terminal of the inverter INV3, the source of the transistor Mp2 is connected to Vdd2, the gate of the transistor Mp2 is connected to the output terminal of the inverter INV3, the output terminal of the comparator comp2 is connected to the input terminal of the inverter INV3, the output terminal of the inverter INV3 is further connected to the input terminal of the inverter INV4, and the output terminal of the inverter INV4 is connected to the second input terminal. In the APD array cell, the transistor Mn3 and the transistor Mn4 are a reset transistor and a holding transistor respectively, the transistor Mp2 is a quenching transistor, current sensing is realized by charging a parasitic capacitor of the node X1, the comparator comp2 can accelerate avalanche current sensing speed, and finally, a signal output by the second current sensing module is shaped by the inverter INV3 and the inverter INV4, so as to output a standard digital signal, i.e., the second digital signal V2.
Preferably, the transistors Mn3 and Mn4 are N-type MOS transistors, and the transistor Mp2 is a P-type MOS transistor.
Referring to fig. 7 and 8, fig. 7 is a schematic circuit diagram of a phase detector in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention, fig. 8 is a schematic circuit diagram of a charge pump in the non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention, a detailed connection relationship between corresponding circuits of the phase detector and the charge pump is not specifically described herein, and the connection relationship between the phase detector and the charge pump is shown in fig. 7 and 8, respectively.
Referring to fig. 9, fig. 9 is a schematic circuit diagram of an inverse bias voltage adjusting module in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention. The reverse bias voltage adjusting module of the present embodiment comprises a start-up circuit, a bias circuit, and a buffer circuit, wherein,
the starting circuit comprises a transistor Mp4d, a transistor Mp5d and a capacitor C2, wherein the drain of the transistor Mp4d is connected with the gate of the transistor Mp5d and one end of the capacitor C2, the drain of the transistor Mp5d is connected with the input end of the biasing circuit, the other end of the capacitor C2 and the gate of the transistor Mp4d are connected with GND, and the source of the transistor Mp4d and the source of the transistor Mp5d are connected with VDD. The starting circuit of the embodiment generates the self-starting signal according to the power supply voltage VDD, so that the power-on process inside the subsequent circuit is accelerated, the output of the subsequent circuit is quickly stabilized, and the problem of unstable output caused by slow charging in the power supply voltage power-on process inside the circuit is avoided.
Preferably, the transistors Mp4d and Mp5d are P-type MOS transistors.
The bias circuit comprises a transistor Mp3d, a transistor Mp2d, a transistor Mn3d, a transistor Mn4d, a transistor Mn5d, and a resistor R1, wherein the drain of the transistor Mp3d is connected to the drain of the transistor Mp5d, one end of the resistor R1, the gate of the transistor Mn4d, and the gate of the transistor Mn5d, the gate of the transistor Mp3d is connected to the gate of the transistor Mp2d, the drain of the transistor Mp2d, the drain of the transistor Mn5d, and the bias input terminal of the buffer circuit, the source of the transistor Mn5d is connected to the drain of the transistor Mn3d, the gate of the transistor Mn3d is connected to the other end of the resistor R1 and the drain of the transistor Mn4d, the source of the transistor Mp3d, the source of the transistor Mp2 82vdd, and the source of the transistor Mn3d and the source of the transistor Mn4d are connected to GND. According to the embodiment, the bias voltage signal is quickly generated according to the self-starting signal generated by the starting circuit, so that stable bias voltage is provided for the subsequent buffer circuit, and the subsequent circuit is ensured to have good power supply rejection ratio.
Preferably, the transistors Mp3d and Mp2d are P-type MOS transistors, and the transistors Mn3d, Mn4d and Mn5d are N-type MOS transistors.
The buffer circuit comprises a transistor Mp0d, a transistor Mp1d, a transistor Mn0d, a transistor Mn1d, a transistor Mn2d, a transistor Mp6d, a transistor Mp7d, and a capacitor C1, wherein the gate of the transistor Mp1d is connected to the gate of the transistor Mp2d, the drain of the transistor Mn5d, and the gate of the transistor Mp0d, the drain of the transistor Mp1d is connected to the source of the transistor Mp6d and the source of the transistor Mp7d, the drain of the transistor Mp0d is connected to the gate of the transistor Mp7d, one end of the capacitor C d, the drain of the transistor Mn0d, the anode of each APD array cell, the gate of the transistor Mp0d is connected to the other end of the capacitor C d, the drain of the transistor Mn1d and the drain of the transistor Mp6d, the gate of the transistor Mp1d is connected to the gate of the transistor Mp2, the source of the transistor Mn2 Mp6d, the drain of the transistor Mp7 and the drain of the transistor Mp 72, the transistor Mp7d are connected to the drain of the transistor Mp 72, the transistor Mp6d, the drain of the transistor Mp 72, The source of the transistor Mp1d is connected to VDD, the source of the transistor Mn0d, the source of the transistor Mn1d, and the source of the transistor Mn2d are connected to GND. In the embodiment, a buffer stage is formed by unit gain negative feedback formed by connecting two stages of amplifiers, the transistor Mp7d at the inverting terminal is connected with the output terminal of the buffer circuit, the transistor Mp6d at the non-inverting terminal is connected with the output terminal of the charge pump, the output terminal of the buffer circuit is also connected with the anode of each APD array unit in the APD array module, and the buffer circuit has the capability of driving large current, so that the anode potential of the APD array unit can be accurately and stably adjusted. The width-length ratio of the transistor Mp0d is greater than the width-length ratios of the transistor Mp1d, the transistor Mp6d and the transistor Mp7d, the width-length ratio of the transistor Mn0d is greater than the width-length ratios of the transistor Mn1d and the transistor Mn2d, and the transistor Mp0d and the transistor Mp0d are of larger sizes, so that large current in a circuit can be absorbed, and the output voltage of a buffer circuit can be ensured to closely follow the input voltage of the charge pump.
Preferably, the transistors Mp0d, Mp1d, Mp6d and Mp7d are P-type MOS transistors, and the transistors Mn0d, Mn1d and Mn2d are N-type MOS transistors.
Referring to fig. 10, fig. 10 is a schematic diagram illustrating simulation results of APD array unit output in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention. In fig. 10, the lowermost edge shows the input of the second input signal Vphoton, the middle edge shows the input of the first input signal Vreset, and the uppermost edge shows the output of the first digital signal V1 output from the APD array cell, and it can be seen that when the first input signal Vreset arrives, the first digital signal V1 output from the APD array cell is changed to a low level to complete the reset, and then when the second input signal Vphoton arrives, the output of the first digital signal V1 output from the APD array cell is changed to a high level to complete the quenching. In this embodiment, the reset operation is performed on the APD array cell before each next detection cycle, so as to prepare for the next detection.
Referring to fig. 11, fig. 11 is a schematic diagram illustrating comparison of simulation results output by the APD array unit and the reference module in the non-uniformity correction circuit for the APD detector array according to the embodiment of the present invention. In fig. 11, V1 is the first digital signal output by the APD array cell, and V2 is the second digital signal output by the reference block. The APD detector may cause the avalanche photocurrent to be inconsistent due to process variations and environmental variations, and there may be a phase difference between the first digital signal V1 output by the APD array unit and the second digital signal V2 output by the reference module as shown in fig. 11.
Referring to fig. 12, fig. 12 is a schematic diagram illustrating simulation results of the output of a charge pump in a non-uniformity correction circuit for an APD detector array according to an embodiment of the present invention. In fig. 12, the top side represents the first processed signal Vout of the charge pump, the middle side represents the first digital signal V1 output by the APD array unit, and the bottom side represents the second digital signal V2 output by the reference block. The signal adjusted by the reverse bias voltage adjusting module is input to the APD array unit again, processed by the APD array unit and input to the phase discriminator, and then input to the charge pump by the phase discriminator, and the first processed signal Vout is output by the charge pump, as can be seen from fig. 12, since the phase difference between the first digital signal V1 and the second digital signal V2 corresponding to the first processed signal Vout when the first processed signal Vout is output stably is zero, the sizes of the avalanche photocurrents are made to be the same.
Referring to fig. 13, fig. 13 is a schematic diagram of simulation results output by the APD array unit and the reference module after passing through the reverse bias voltage adjusting module in the non-uniformity correction circuit for the APD detector array according to the embodiment of the present invention. In fig. 13, V1 is the first digital signal output by the APD array cell, and V2 is the second digital signal output by the reference block. It can be seen that in this embodiment, under the negative feedback adjustment, the voltage of the first processing signal Vout gradually increases, the response speed of the APD array unit gradually keeps consistent with the response speed of the reference module, the phase difference between the first digital signal V1 and the second digital signal V2 is zero, and the anode potential in the APD array unit keeps constant, so that the magnitudes of the avalanche photocurrents are consistent.
The present embodiment can implement the embodiments in the first and second embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (6)
1. A nonuniformity correction circuit facing an APD detector array is characterized by comprising an APD array module, a reference module, a phase discriminator and a charge pump, wherein,
the APD array module is used for carrying out current induction and shaping processing on a second input signal after carrying out reset processing according to a first input signal to obtain a first digital signal;
the reference module is used for carrying out current induction and shaping processing on a fourth input signal after carrying out reset processing according to a third input signal to obtain a second digital signal;
the phase discriminator is connected with the APD array module and the reference module and used for comparing the phase difference between the first digital signal and the second digital signal to obtain a first phase difference signal and a second phase difference signal;
the charge pump is connected with the phase discriminator and used for carrying out charge-discharge processing on the charge pump according to the first phase difference signal and the second phase difference signal to obtain a first processing signal;
the charge pump is further connected with the APD array module and used for inputting the first processing signal to the APD array module.
2. The non-uniformity correction circuit for an APD detector array of claim 1, further comprising a reverse bias voltage adjustment module, wherein,
the reverse bias voltage adjusting module is connected to the charge pump and the APD array module, and is configured to buffer the first processing signal to obtain a second processing signal, and input the second processing signal to the APD array module.
3. The APD detector array-facing non-uniformity correction circuit of claim 1 or 2, wherein the APD array module comprises a number of APD array cells, each of the APD array cells comprising a first current sensing module, a first pulse shaping module, wherein,
the first current sensing module is used for carrying out current sensing processing on the second input signal after carrying out reset processing according to the first input signal to obtain a first induced current signal;
the first pulse shaping module is connected with the first current sensing module and the phase discriminator, and is used for rectifying the first induced current signal to obtain the first digital signal and inputting the first digital signal to the phase discriminator.
4. The APD detector array-oriented non-uniformity correction circuit of claim 1 or 2, wherein the reference module comprises a second current sensing module, a second pulse shaping module, wherein,
the second current sensing module is used for carrying out current sensing processing on the fourth input signal after carrying out reset processing according to the third input signal to obtain a second induced current signal;
the second pulse shaping module is connected with the second current sensing module and the phase detector, and is used for rectifying the second sensing current signal to obtain a second digital signal and inputting the second digital signal to the phase detector.
5. The non-uniformity correction circuit for an APD detector array of claim 1 or claim 2, wherein the phase detector is a dynamic phase detector.
6. The APD detector array-facing non-uniformity correction circuit of claim 2, wherein the reverse bias voltage adjustment module comprises a start-up circuit, a bias circuit, and a buffer circuit, wherein,
the starting circuit is used for self-starting to generate a self-starting signal;
the bias circuit is connected with the starting circuit and used for generating a bias voltage signal according to the self-starting signal;
the buffer circuit is connected to the bias circuit, the charge pump and the APD array module, and configured to buffer the first processing signal according to the bias voltage signal to obtain the second processing signal, and input the second processing signal to the APD array module.
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| US7151413B2 (en) * | 2004-12-02 | 2006-12-19 | Via Technologies Inc. | Low noise charge pump for PLL-based frequence synthesis |
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| CN103297042A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Charge pump phase-locked loop circuit capable of being locked quickly |
| CN104266767A (en) * | 2014-09-22 | 2015-01-07 | 电子科技大学 | Substrate temperature compensation's infrared focal plane array detector read-out circuit |
| CN106291512B (en) * | 2016-07-29 | 2018-11-27 | 中国科学院光电研究院 | A kind of method of array push-broom type laser radar range Nonuniformity Correction |
| CN106441597B (en) * | 2016-09-26 | 2018-10-30 | 东南大学 | A kind of reversed bias voltage applied to array avalanche diode adjusts circuit |
| CN107197175B (en) * | 2017-05-31 | 2020-02-14 | 北京空间机电研究所 | High-rail area array staring infrared camera imaging circuit system |
| CN107449516B (en) * | 2017-07-06 | 2019-07-23 | 东南大学 | A kind of the photon counting linear array reading circuit and method of self-adaptive detection mode |
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