CN107197175B - High-rail area array staring infrared camera imaging circuit system - Google Patents
High-rail area array staring infrared camera imaging circuit system Download PDFInfo
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- CN107197175B CN107197175B CN201710401024.1A CN201710401024A CN107197175B CN 107197175 B CN107197175 B CN 107197175B CN 201710401024 A CN201710401024 A CN 201710401024A CN 107197175 B CN107197175 B CN 107197175B
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Abstract
The invention discloses a high-rail area array staring infrared camera imaging circuit system which comprises an area array infrared detector, a bias driving module, a signal processing module, a data storage module, a locking current-limiting monitoring module and a high-speed clock management module. In the bias driving module and the signal processing module, a device with high performance and high radiation resistance is adopted to generate bias driving voltage and time sequence required by the work of the area array infrared detector; the data storage module adopts a magnetic memory array with flexible read-write control and single event upset immunity to store large-scale non-uniformity correction coefficients of the area array infrared detector, so that the single event upset effect is effectively prevented; for devices sensitive to single particle locking in the system, a locking current-limiting control technology is adopted to protect the locking devices from being burnt by large current, and the single particle locking resistance of the devices is improved; the high-speed clock management module provides high-quality clocks for the modules. The invention has the characteristics of high speed, high reliability and high radiation resistance.
Description
Technical Field
The invention belongs to the technical field of imaging of infrared cameras, and particularly relates to a high-rail area array staring infrared camera imaging circuit system.
Background
In recent years, the area-array infrared camera is widely applied to the military and civil remote sensing fields due to the advantages of high sensitivity, no need of an optical machine scanning mechanism, small volume, light weight and the like. When the area-array infrared camera is applied to the geosynchronous orbit remote sensing satellite, the geosynchronous orbit remote sensing satellite is synchronous with the earth and is static relative to the earth, so that the area-array infrared camera can perform long-term 'staring' on a target area, perform high-frequency shooting on the target area at intervals of minutes and even seconds, acquire data of a dynamic change process of the target area, and have extremely high time resolution.
Although the geosynchronous orbit area array staring infrared camera has a plurality of advantages, the orbit is a geosynchronous orbit which is 3.6 kilometers away from the earth, the orbit height is nearly 600 times higher than that of the low orbit remote sensing camera, the space irradiation environment is much worse than that of the low orbit space environment, a large amount of charged particles and various rays can damage and age electronic components, and the stable work of the camera is influenced. The high-orbit array staring infrared imaging circuit system is a core circuit of a high-orbit array staring infrared camera, the performance of the high-orbit array staring infrared imaging circuit system directly affects the imaging quality of the camera, the reliability of the high-orbit array staring infrared imaging circuit system directly determines the success or failure of the imaging task of the camera, and therefore when the high-orbit array staring infrared imaging circuit system is designed, the anti-irradiation capacity of the circuit system needs to be improved besides the design of low noise, high precision and low jitter.
Disclosure of Invention
The technical problem of the invention is solved: the defects of the prior art are overcome, and a high-rail area array staring infrared camera imaging circuit system is provided, so that the practical requirements of high speed, high reliability and high radiation resistance are met.
In order to solve the technical problem, the invention discloses a high-rail area array staring infrared camera imaging circuit system, which comprises: the system comprises a bias driving module, an area array infrared detector, a signal processing module, a data storage module, a locking current-limiting monitoring module and a high-speed clock management module;
the bias driving module is used for generating various bias voltages required by the work of the area array infrared detector; driving the detector time sequence signal output by the signal processing module to obtain a driving time sequence signal matched with the requirements of the area array infrared detector;
the area array infrared detector is used for converting the optical signal into 4 paths of analog electric signals under the drive of the bias drive module and outputting the analog electric signals;
the signal processing module is used for processing 4 paths of analog electric signals output by the area array infrared detector to obtain 1 path of high-speed serial image data and transmitting the 1 path of high-speed serial image data to image acquisition equipment;
the data storage module is used for storing large-scale pixel response non-uniformity correction coefficients of the area array infrared detector;
the locking current-limiting monitoring module is used for cutting off the power supply of the single-event locking sensitive device when the single-event locking sensitive device is subjected to single-event locking, so that the locking device is protected from being burnt by large current;
the high-speed clock management module is used for providing a high-quality clock.
In the above-mentioned high-rail area array staring infrared camera imaging circuit system, the bias driving module includes: the bias voltage generation submodule and the time sequence driving submodule;
the bias voltage generation submodule is used for generating various bias voltages required by the operation of the area array infrared detector;
and the time sequence driving submodule is used for driving the detector time sequence signal output by the signal processing module to obtain a driving time sequence signal matched with the requirement of the area array detector.
In the imaging circuit system of the high-rail area array staring infrared camera, the bias voltage generation submodule is used for generating various bias voltages required by the work of the area array infrared detector according to the requirements of driving current, noise and tolerance.
In the above high-rail area array staring infrared camera imaging circuit system, the bias voltage generation submodule is configured to: when the noise and tolerance requirements meet a first preset requirement and the photodiode bias voltage needs to be accurately adjusted, generating a high-precision reference voltage signal according to a voltage reference with low noise, low temperature drift and high radiation resistance; dividing the quasi-voltage signal through a voltage dividing resistor network to obtain a divided voltage signal; driving and amplifying the voltage division signal through an operational amplifier with high common mode rejection ratio and low noise to obtain bias voltage;
the voltage division resistor network consists of an adjustable potentiometer and a precision resistor;
the adjustable potentiometer is used for adjusting the voltage dividing resistance value in real time and dividing the reference voltage signal to obtain the optimal photodiode bias voltage;
and the precision resistor is used for determining a precision voltage dividing resistance value according to the resistance value adjusted by the adjustable potentiometer to obtain the bias voltage.
In the above high-rail area array staring infrared camera imaging circuit system, the bias voltage generation submodule is configured to:
when the noise and tolerance requirements meet a second preset requirement and the driving current is larger than or equal to 100mA, a high-current and low-noise voltage signal is generated through the low-dropout linear regulator with low noise and high radiation resistance, and the required power supply voltage is generated through the low-pass filter circuit.
In the above-mentioned high-rail area array staring infrared camera imaging circuit system, the signal processing module includes: the device comprises a conditioning module, a 14bits analog-to-digital converter, an FPGA and a high-speed serial data transmission circuit;
the conditioning module is used for conditioning 4 paths of analog electric signals output by the area array infrared detector to obtain analog signals matched with an input interface of the 14bits analog-to-digital converter;
the 14bits analog-to-digital converter is used for performing analog-to-digital conversion on the conditioned 4 paths of analog signals to obtain 4 paths of 14bits digital data;
the FPGA is used for performing oversampling point selection, mean value filtering, data combining, pixel response non-uniformity correction, blind pixel replacement and data arrangement on 4 paths of 14bits digital data to obtain 1 path of high-speed serial image data;
and the high-speed serial data transmission circuit is used for transmitting the 1-path high-speed serial image data to image acquisition equipment.
In the above high-track area array staring infrared camera imaging circuit system, the high-speed clock management module includes: the circuit comprises a reference clock, a voltage-controlled crystal oscillator, a clock synchronization debouncing chip and a loop filter; the reference clock, the voltage-controlled crystal oscillator, the clock synchronization debouncing chip and the loop filter form a phase-locked loop circuit;
the reference clock is used for generating a reference clock signal;
the clock synchronization debouncing chip is used for carrying out frequency division and phase discrimination on a clock output by the voltage-controlled crystal oscillator and generating control current according to a phase discrimination result;
the loop filter is used for converting the control current into a low-noise control voltage signal; the low-noise control voltage signal is used for controlling the output frequency of the voltage-controlled crystal oscillator;
and the voltage-controlled crystal oscillator is used for locking the phase of an output clock with the phase of a reference clock and removing jitter under the control of the low-noise control voltage signal.
In the above-mentioned high-orbit area array staring infrared camera imaging circuit system, the clock synchronization debouncing chip includes: the device comprises a phase discriminator, a frequency divider and a charge pump;
the frequency divider is used for dividing the frequency of the clock signal output by the voltage-controlled crystal oscillator;
the phase discriminator is used for carrying out phase comparison on the clock signal subjected to frequency division by the frequency divider and the reference clock signal to obtain a comparison result;
the charge pump is used for outputting control current according to a phase comparison result output by the phase discriminator;
the frequency divider is also used for dividing the frequency of the voltage-controlled crystal oscillator after being locked and removed, outputting 4 pairs of 50MHz LVPECL differential clocks to provide conversion clocks for the 4 paths of analog-to-digital converters, and outputting two paths of 100MHz LVCMOS single-ended clocks to provide main clocks for the FPGA and the high-speed serial transmission circuit.
In the high-rail area array staring infrared camera imaging circuit system, the locking current-limiting monitoring module is connected in series between a power supply of the single event locking sensitive device and the device and is used for setting a threshold current I according to the normal working current of the devicethBy means of a shunt RshuntMonitoring working current I of single event lock sensitive device in real timewWhen the single event locking effect of the device occurs on the track, if the working current I of the devicewGreater than a set threshold current IthCutting off the power supply of the device, and removing the single event locking effect of the device; when the preset time interval T is metdAnd then, the power is supplied to the single event locking sensitive device again, and the device is protected from being burnt by large current when the single event locking effect occurs.
The invention has the following advantages:
the invention discloses a high-rail area array staring infrared camera imaging circuit system, which adopts devices with high performance and high anti-irradiation capability in a bias driving module and a signal processing module to generate bias driving voltage and time sequence required by the work of an area array infrared detector according to the characteristics of severe environment, long service life and long-term power-up of a system in an in-rail space, and conditions an analog signal output by the detector to obtain 1-path high-speed serial image data. The data storage module adopts a magnetic memory array with flexible read-write control and single event upset immunity to store large-scale non-uniformity correction coefficients of the area array infrared detector, so that the single event upset effect is effectively prevented; for devices sensitive to single-particle locking in the system, a locking current-limiting control technology is adopted, and when the single-particle locking occurs in the devices, the power supply of the devices is cut off, so that the locking devices are protected from being burnt by large current, and the single-particle locking resistance of the devices is improved; the high-speed clock management module provides high-quality clocks for the modules. Compared with the traditional area array staring infrared camera imaging circuit system, the invention has the characteristics of high speed, high reliability and high radiation resistance.
Drawings
FIG. 1 is a block diagram of an imaging circuit system of a high-track area-array staring infrared camera according to an embodiment of the present invention;
FIG. 2 is a block diagram of a bias driver module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the operation of a bias voltage generation sub-module in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a bias voltage Gpol according to an embodiment of the present invention;
fig. 5 is a block diagram of a signal processing module according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of oversampling of an analog signal of an area array infrared detector according to an embodiment of the present invention;
FIG. 7 is a schematic illustration of a grouping of pixel response non-uniformity correction factors in a magnetic storage array in accordance with an embodiment of the present invention;
fig. 8 is a block diagram of a locked current-limiting monitoring module according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, common embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 1, a block diagram of an imaging circuit system of a high-orbit area-array staring infrared camera in an embodiment of the present invention is shown. In this embodiment, the imaging circuit system of the high-rail area-array staring infrared camera includes: the system comprises a bias driving module 100, an area array infrared detector 200, a signal processing module 300, a data storage module 400, a locking current-limiting monitoring module 500 and a high-speed clock management module 600.
The bias driving module 100 is configured to generate a plurality of bias voltages required by the operation of the area array infrared detector; and driving the detector time sequence signal output by the signal processing module to obtain a driving time sequence signal matched with the requirements of the area array infrared detector.
The area array infrared detector 200 is configured to convert the optical signal into 4 paths of analog electrical signals under the driving of the bias driving module and output the analog electrical signals.
The signal processing module 300 is configured to process 4 paths of analog electrical signals output by the area array infrared detector to obtain 1 path of high-speed serial image data, and transmit the 1 path of high-speed serial image data to the image acquisition device.
The data storage module 400 is used for storing large-scale pixel response non-uniformity correction coefficients of the area array infrared detector.
The locking current-limiting monitoring module 500 is used for cutting off the power supply of the single-event locking sensitive device when the single-event locking sensitive device is subjected to single-event locking, and protecting the locking device from being burnt by large current.
The high-speed clock management module 600 is used for providing a high-quality clock.
(1) Bias driving module
Referring to fig. 2, a block diagram of a bias driving module according to an embodiment of the present invention is shown. In this embodiment, the bias driving module 100 may specifically include: a bias voltage generation submodule 101 and a timing driving submodule 102.
In this embodiment, the bias voltage generation submodule 101 is configured to generate a plurality of bias voltages required by the operation of the area array infrared detector; and the timing driving submodule 102 is configured to drive the detector timing signal output by the signal processing module to obtain a driving timing signal matched with the requirement of the area array detector.
The bias voltage generation submodule 101 may generate, according to the requirements of the driving current, the noise, and the tolerance, a plurality of bias voltages required by the operation of the area array infrared detector:
when the noise and tolerance requirements meet a first preset requirement (high, a specific value can be determined according to actual conditions) and the photodiode bias voltage needs to be accurately adjusted, generating a high-precision reference voltage signal according to the voltage references with low noise, low temperature drift and high radiation resistance; dividing the reference voltage signal through a voltage dividing resistor network to obtain a divided voltage signal; driving and amplifying the voltage division signal through an operational amplifier with high common mode rejection ratio and low noise to obtain bias voltage; the voltage division resistor network consists of an adjustable potentiometer and a precision resistor; the adjustable potentiometer is used for adjusting the voltage dividing resistance value in real time and dividing the reference voltage signal to obtain the optimal photodiode bias voltage; and the precision resistor is used for determining a precision voltage dividing resistance value according to the resistance value adjusted by the adjustable potentiometer to obtain the bias voltage.
When the noise and tolerance requirements meet a second preset requirement (low) and the driving current is larger than or equal to 100mA, a high-current and low-noise voltage signal is generated by the low-dropout linear regulator with low noise and high radiation resistance, and the required power supply voltage is generated by the low-pass filter circuit.
Specifically, in this embodiment, the bias voltage generation sub-module 101 can generate 3 bias voltages (required: noise < 5mV, tolerance < ± 50mV, and driving current < 100mA), VDDD (required: noise < 5mV, tolerance < ± 50mV, and driving current < 100mA), and Gpol (required: noise < 100uV, tolerance < ± 5mV, and driving current < 5mA) required for the 1k × 1k area array infrared detector to operate.
Fig. 3 is a schematic diagram illustrating the operation of a bias voltage generation sub-module according to an embodiment of the present invention. In this embodiment, the bias voltage generation sub-module 101 may generate the bias voltage by different methods according to different requirements on the driving current, noise, tolerance, and the like. Specifically, the method comprises the following steps: the high-current analog power supply VDDA and the high-current digital power supply VDDD are generated by a low-noise linear voltage stabilizer, the total irradiation resisting dose of the linear voltage stabilizer is 300kradSi, and the single-particle locking immunity can meet the high-rail use requirement; the linear voltage stabilizer is fixed to output 5V, the maximum output driving current can reach 2A, the root mean square noise is 40uV, the output precision is 1% (+/-50 mV), and the electrical property meets the requirements of a detector. The adjustable bias voltage Gpol is the photodiode bias voltage of the area array infrared detector, each detector has the optimal Gpol value, and the noise size, precision and stability directly influence the performance of the detector. The Gpol system is generated by adopting a method of high-precision band gap voltage-stabilizing reference, low-temperature drift voltage-dividing resistance, low noise and low-temperature drift operation.
Fig. 4 shows a schematic diagram of generating a bias voltage Gpol according to an embodiment of the present invention. In the embodiment, the high-precision bandgap voltage-stabilizing reference fixed output is 5V, R1, Rc, R2 and R3 form a resistance voltage-dividing network, the Rc is an adjustable potentiometer, the voltage-dividing network is firstly connected to a path 1, the adjustable potentiometer Rc obtains an optimal bias voltage, then the voltage-dividing network disconnects the path 1 from a path 2, and the value of the voltage-dividing resistors R2 and R3 is determined according to the resistance value of the potentiometer Rc to obtain a required bias voltage; the resistor Ro is an output current-limiting resistor, when Gpol is short-circuited to the ground, the short-circuit current of the operational amplifier 201 is limited, the operational amplifier is protected from being damaged, meanwhile, the Ro, the polar tantalum capacitor C1 and the ceramic chip capacitor C2 form a low-pass filter network, and the Gpol bias noise is filtered; r4 is a feedback resistor, one end of which is connected to the inverting input terminal of the operational amplifier 201, and the other end of which is connected to Ro, when the impedance of the Gpol pin at the detector terminal changes, the Gpol bias voltage can be stably output without being affected by the load change; cf is a feedback compensation capacitor to ensure that the operational amplifier 201 does not generate self-oscillation.
Further preferably, the timing driving sub-module 102 is configured to perform timing driving and level conversion on a timing signal generated by a Field-Programmable Gate Array (FPGA) under the signal processing module, so as to meet a timing requirement of the area Array infrared detector.
(2) Signal processing module
Referring to fig. 5, a block diagram of a signal processing module according to an embodiment of the present invention is shown. In this embodiment, the signal processing module 300 may specifically include: a conditioning module 301, a 14bits analog-to-digital converter 302, an FPGA303 and a high-speed serial data transmission circuit 304.
In this embodiment, the conditioning module 301 is configured to condition 4 paths of analog electrical signals output by the area array infrared detector to obtain an analog signal matched with an input interface of the 14bits analog-to-digital converter; the 14bits analog-to-digital converter 302 is configured to perform analog-to-digital conversion on the conditioned 4 paths of analog signals to obtain 4 paths of 14bits digital data; the FPGA303 is used for performing oversampling point selection, mean value filtering, data combining, pixel response non-uniformity correction, blind pixel replacement and data arrangement on 4 paths of 14bits digital data to obtain 1 path of high-speed serial image data; the high-speed serial data transmission circuit 304 is configured to transmit the 1-channel high-speed serial image data to an image capturing device.
Referring to fig. 6, a schematic diagram of oversampling of an analog signal of an area array infrared detector according to an embodiment of the present invention is shown. The pixel reading frequency of the area array infrared detector is 5MHz, the lowest sampling frequency of the selected 14-bit aerospace class analog-to-digital converter is 30MHz, if each pixel is sampled for 1 time, the pixel reading frequency cannot be matched with the sampling frequency of the analog-to-digital converter, the system designs the sampling frequency of the analog-to-digital converter to be 50MHz according to the characteristic that the output signal of each pixel of the 1k multiplied by 1k area array infrared detector keeps a level value after being quickly established, and the analog-to-digital converter can acquire 10 data of the pixel in a pixel reading period; the method comprises the steps of selecting 10 sampling data of each pixel in an FPGA (field programmable gate array), removing 6 (1, 2, 3, 8, 9 and 10) unstable data in the analog signal establishing process, reserving 4 (4, 5, 6 and 7) stable sampling point data, performing accumulation and averaging mean value filtering processing on the sampling point data, reducing quantization noise and circuit thermal noise of an analog-to-digital converter, improving the signal-to-noise ratio of a system, and solving the problem of selection of an aerospace-level analog-to-digital converter.
Further preferably, in this embodiment, the signal processing module 300 may specifically perform sampling processing on the analog signal by using an oversampling scheme according to a characteristic that an output signal of each pixel of the area array infrared detector maintains a level value after being quickly established. Specifically, the pixel reading frequency of the area array infrared detector is set to be Fr, the sampling frequency of a 14bits analog-to-digital converter to each pixel analog signal is NxFr, and in a pixel reading period, the analog-to-digital converter can acquire data of N pixels; the FPGA selects N sampling data of each pixel, removes N-M unstable data in the process of establishing the analog signal, retains M stable sampling point data, and performs sampling on the M sampling point data according to the M stable sampling point dataThe formula (Xi is ith sampling data) is subjected to mean filtering processing, so that the quantization noise and the circuit thermal noise of the analog-to-digital converter are reduced, and the signal-to-noise ratio of the system is improved.
(3) Data storage module
In this embodiment, the pixel response non-uniformity correction is implemented by a real-time correction scheme in which a plurality of sets of correction coefficients are pre-stored on the ground and the correction coefficients are adaptively selected on-track. The scale of the area array infrared detector is 1 Kx 1K pixel, the high-low gain is adjustable, the integral time is adjustable in four sections, and each pixel needs two 16bits correction coefficients of a gain correction coefficient K and an offset correction coefficient B; the pixel response heterogeneity of the area array infrared detector changes along with the integral time and the gain, the invention designs high and low two-grade gain to prestore the change of 4 groups of correction coefficients corresponding to four sections of integral time respectively, prestore 8 groups of pixel correction coefficients totally, prestore data storage module with data volume of 8 MX 32bits adopts 16 single-particle turning immunity and 2 MX 8bits magnetic memory without power loss to form a storage array to prestore 8 groups of pixel response heterogeneity correction coefficients; the 16 pieces of 2 Mx 8bits magnetic memories are firstly grouped into 4 groups for depth expansion to form 4 8 Mx 8bit storage groups, and then the 4 8 Mx 8bit storage groups are subjected to bit width expansion to form an 8 Mx 32bit magnetic storage array, so that the storage of large-scale pixel correction coefficients is realized. When the FPGA in the signal processing module sends a gain and integral time adjusting instruction, the FPGA adaptively judges and selects 1 group of correction coefficients in 8 groups according to a gain parameter and an integral time parameter, and carries out pixel response non-uniformity correction on current image data, thereby realizing a real-time correction scheme for adaptively selecting the correction coefficients in an on-orbit mode.
In other words, in the present embodiment, the area array infrared detector has large pixel response non-uniformity due to large pixel scale and complex process, and the uniformity may change with the change of the detector gain or the integration time. When the area array staring infrared camera is used for on-track ground imaging, the gain and the integration time of the detector are generally required to be adjusted according to different observation targets. Therefore, the invention adopts a real-time pixel response non-uniformity correction scheme of pre-storing a plurality of groups of correction coefficients on the ground and adaptively selecting the correction coefficients on the orbit in consideration of the difficulty degree and the correction effect of the on-orbit realization.
The correction coefficient is obtained by fixing the detector gain and the integration time on the ground and acquiring black body images of a plurality of temperature points. The detector used in the invention has two gain gears, the integral time is 0.1 ms-20 ms (step 2us), if a group of correction coefficients are prestored in each step, a very large storage space is needed, therefore, the hardware is easy to realize, the integral time is divided into four sections of 0.1 ms-1 ms, 1.002 ms-5 ms, 5.002 ms-10 ms and 10.002 ms-20 ms according to the output response curve of the area array infrared detector, and each gain gear obtains 4 groups of correction coefficients which change along with the integral time. And when the gain and the integration time are adjusted on track, the FPGA adaptively judges and selects a corresponding correction coefficient according to the received instruction parameters.
The scale of the area array infrared detector is 1 Kx 1K pixel, each pixel is designed with two 16bits correction coefficients of gain correction coefficient K and bias correction coefficient B, 8 groups of pixel correction coefficients, and the pre-stored data volume is 8 Mx 32 bits.
The traditional remote sensing camera prestores the correction coefficient and mostly adopts PROM (Programmable Read Only Memory) to store, but PROM does not have address line, can Only Read data according to the clock beat sequence, and Read the speed slowly, need to be equipped with SRAM (Static Random Access Memory) to carry on further coefficient cache processing, this not Only increases PCB (Printed Circuit Board) area, and SRAM is apt to take place the single particle and overturns and make the camera reliability reduce. The data storage module of the invention adopts 16 pieces of 2 Mx 8bits magnetic memories with single particle turning immunity and power failure loss to form a storage array to store 8 groups of correction coefficients. Storage array grouping diagram fig. 7 is a diagram illustrating grouping of picture element response non-uniformity correction coefficients in a magnetic storage array according to an embodiment of the present invention. The 16 pieces of magnetic memory are divided into 4 groups, every 4 pieces of 2 Mx 8bits of magnetic memory carry on the chip selection signal CS1, CS2, CS3 and CS4 of the 4 pieces of memory of depth extension as the high four-digit of the address line of 25bits, read enable signal RE, write enable signal WE and 8bits data line share, get 4 groups of 8 Mx 8bits of memory banks; and the bit width of the 8-bit data lines of the 4 groups of 8 Mx 8-bit storage groups is expanded to 32-bit data width, and the 25-bit address lines, the read enable signal RE and the write enable signal WE of the 4 groups of storage groups are shared. A24 bits address line in the memory array is addressed according to CS4& CS3& CS2& CS1& A20-A0, 0200000H-02 FFFFFH stores a correction coefficient under the state of low-gain integration time 0.1 ms-1 ms, 0300000H-03 FFFFFH stores a correction coefficient under the state of low-gain integration time 1.002 ms-5 ms, 0400000H-04 FFFH stores a correction coefficient under the state of low-gain integration time 5.002 ms-10 ms, 0500000H-05 FFFH stores a correction coefficient under the state of low-gain integration time 10.002 ms-20 ms, 0800000H-08 FFFFFH stores a correction coefficient under the state of high-gain integration time 0.1 ms-1 ms, 0900000H 09 FFFH stores a correction coefficient under the state of high-gain integration time 1.002 ms-5 ms, 1000000H-10 FFFH stores a correction coefficient under the state of high-gain integration time 5.002 ms-10 ms, and 1100000H-11 FFFH stores a correction coefficient under the state of high-20.002 ms. And when the gain and the integration time are adjusted on track, the FPGA judges and reads the correction coefficient of the corresponding address space in a self-adaptive manner according to the received instruction parameters.
(4) Locking current limiting monitoring module
Referring to fig. 8, a block diagram of a locked current-limiting monitoring module according to an embodiment of the present invention is shown. In this embodiment, the lock current limiting monitoring module is connected in series between a power supply of the single event lock sensitive device and the device, and is configured to set a threshold current I according to a normal operating current of the devicethBy means of a shunt RshuntMonitoring working current I of single event lock sensitive device in real timewWhen the single event locking effect of the device occurs on the track, if the working current I of the devicewGreater than a set threshold current IthCutting off the power supply of the device, and removing the single event locking effect of the device; when the preset time interval T is metdAnd then, the power is supplied to the single event locking sensitive device again, and the device is protected from being burnt by large current when the single event locking effect occurs.
Wherein, each parameter setting of locking current-limiting monitoring module is as follows:
1) locking threshold current I of current limiting monitoring modulethThe standby operation threshold current I can be setth_rAnd a threshold current Ith_sTwo types of the single-event locking sensitive devices can be protected under different working states;
2) by controlling MODE _ IthSignal, select threshold current, MODE _ IthWhen the current is high level '1', the locking current-limiting monitoring module selects the threshold current Ith_r；MODE_IthWhen the current is high level '0', the locking current-limiting monitoring module selects the threshold current Ith_s；
3)Ith_1And Ith_2By setting a resistor R between the LIM _ s of the locked current-limiting monitoring module and the groundsAnd a resistor R between LIM _ s and LIM _ R of the locking current-limiting monitoring modulerThe specific formula is as follows:
4) power-off restart interval TdDelay capacitor C between ADJ _ RESTART of the locked current-limiting monitoring module and grounddDetermination of TdAnd CdThe relationship of (1) is:
Cd＝26*Td
wherein, TdUnits of ms, CdThe unit is nF.
(5) High-speed clock management module
In this embodiment, the high-speed clock management module may specifically include: the circuit comprises a reference clock, a voltage-controlled crystal oscillator, a clock synchronization debouncing chip and a loop filter. The reference clock, the voltage-controlled crystal oscillator, the clock synchronization debouncing chip and the loop filter form a phase-locked loop circuit.
The reference clock is used for generating a reference clock signal; the clock synchronization debouncing chip is used for carrying out frequency division and phase discrimination on a clock output by the voltage-controlled crystal oscillator and generating control current according to a phase discrimination result; the loop filter is used for converting the control current into a low-noise control voltage signal; the low-noise control voltage signal is used for controlling the output frequency of the voltage-controlled crystal oscillator; the vco 604 is configured to lock an output clock phase with a reference clock phase and remove jitter under the control of the low-noise control voltage signal.
Preferably, the clock synchronization debounce chip specifically may include: phase detector, frequency divider and charge pump.
The frequency divider is used for dividing the frequency of the clock signal output by the voltage-controlled crystal oscillator; the phase discriminator is used for carrying out phase comparison on the clock signal subjected to frequency division by the frequency divider and the reference clock signal to obtain a comparison result; the charge pump is used for outputting control current according to a phase comparison result output by the phase discriminator; the frequency divider is also used for dividing the frequency of the voltage-controlled crystal oscillator after being locked and removed, outputting 4 pairs of 50MHz LVPECL differential clocks to provide conversion clocks for the 4 paths of analog-to-digital converters, and outputting two paths of 100MHz LVCMOS single-ended clocks to provide main clocks for the FPGA and the high-speed serial transmission circuit. The high-speed clock management module outputs 4 pairs of 50MHz LVPECL differential clocks with jitter of only 60ps, so that the aperture jitter and the conversion noise of the analog-to-digital converter are greatly reduced; the jitter of the two 100MHz LVCMOS single-ended clocks is 100ps, so that the working stability of the FPGA and the high-speed serial data transmission chip during long-term power-up is improved.
In summary, an imaging circuit system of a high-rail area-array staring infrared camera comprises an area-array infrared detector, a bias driving module, a signal processing module, a data storage module, a locking current-limiting monitoring module and a high-speed clock management module. According to the characteristics of severe environment, long service life and long-term power-up of a system in an on-orbit space, a high-performance and high-radiation-resistance device is adopted in a bias driving module and a signal processing module to generate bias driving voltage and time sequence required by the work of an area array infrared detector, the analog signal output by the detector is conditioned and subjected to 14bits analog-to-digital conversion, and meanwhile, multi-channel data subjected to analog-to-digital conversion are subjected to oversampling point selection, mean value filtering, data combination, pixel response non-uniformity correction, blind pixel replacement and data arrangement, and the data are transmitted to image acquisition equipment through a high-speed serial data transmission circuit; the data storage module adopts a magnetic memory array with flexible read-write control and single event upset immunity to store large-scale non-uniformity correction coefficients of the area array infrared detector, so that the single event upset effect is effectively prevented; for devices sensitive to single-particle locking in the system, a locking current-limiting control technology is adopted, and when the single-particle locking occurs in the devices, the power supply of the devices is cut off, so that the locking devices are protected from being burnt by large current, and the single-particle locking resistance of the devices is improved; the high-speed clock management module adopts a clock synchronization debounce chip, a voltage-controlled crystal oscillator and a loop filter to form a phase-locked loop circuit, and provides a high-quality clock for the FPGA, the analog-to-digital converter and the high-speed serial data transmission chip after clock debounce, frequency division and phase modulation are carried out on an input reference clock and the voltage-controlled clock. Compared with the traditional area array staring infrared camera imaging circuit system, the invention has the characteristics of high speed, high reliability and high radiation resistance.
The embodiments in the present description are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
Claims (8)
1. A high rail area array staring infrared camera imaging circuit system is characterized by comprising: the system comprises a bias driving module, an area array infrared detector, a signal processing module, a data storage module, a locking current-limiting monitoring module and a high-speed clock management module;
the bias driving module is used for generating various bias voltages required by the work of the area array infrared detector; driving the detector time sequence signal output by the signal processing module to obtain a driving time sequence signal matched with the requirements of the area array infrared detector;
the area array infrared detector is used for converting the optical signal into 4 paths of analog electric signals under the drive of the bias drive module and outputting the analog electric signals;
the signal processing module is used for processing 4 paths of analog electric signals output by the area array infrared detector to obtain 1 path of high-speed serial image data and transmitting the 1 path of high-speed serial image data to image acquisition equipment;
the data storage module is used for storing large-scale pixel response non-uniformity correction coefficients of the area array infrared detector;
the locking current-limiting monitoring module is used for cutting off the power supply of the single-event locking sensitive device when the single-event locking sensitive device is subjected to single-event locking, so that the locking device is protected from being burnt by large current;
the high-speed clock management module is used for providing a high-quality clock;
wherein the content of the first and second substances,
the locking current-limiting monitoring module is connected in series between a power supply of the single-event locking sensitive device and the device, and is specifically used for setting a threshold current I according to the normal working current of the devicethBy means of a shunt RshuntMonitoring working current I of single event lock sensitive device in real timewWhen the single event locking effect of the device occurs on the track, if the working current I of the devicewGreater than a set threshold current IthCutting off the power supply of the device, and removing the single event locking effect of the device; when the preset time interval T is metdWhen the single-event locking sensitive device is powered up again, the device is protected from being burnt by large current when the single-event locking effect occurs;
the parameters of the locking current-limiting monitoring module are set as follows:
1) locking threshold current I of current limiting monitoring modulethThe standby operation threshold current I can be setth_rAnd a threshold current Ith_sTwo types of the single-event locking sensitive devices can be protected under different working states;
2) by controlling MODE _ IthSignal, selecting threshold current，MODE_IthWhen the current is high level '1', the locking current-limiting monitoring module selects the threshold current Ith_r；MODE_IthWhen the current is high level '0', the locking current-limiting monitoring module selects the threshold current Ith_s；
3)Ith_rAnd Ith_sBy setting a resistor R between the LIM _ s of the locked current-limiting monitoring module and the groundsAnd a resistor R between LIM _ s and LIM _ R of the locking current-limiting monitoring modulerThe specific formula is as follows:
wherein VDD represents a supply voltage value of the power supply; LIM _ s and LIM _ r are two access points in the locking current-limiting monitoring module, and LIM _ s is threshold current Ith_sCorresponding access point, LIM _ r is threshold current Ith_rA corresponding access point;
4) power-off restart interval TdDelay capacitor C between ADJ _ RESTART of the locked current-limiting monitoring module and grounddDetermination of TdAnd CdThe relationship of (1) is:
Cd＝26*Td
wherein, TdUnits of ms, CdIn nF, ADJ _ RESTART is an access point in the lock-in current-limiting monitoring module, specifically a delay capacitor CdA corresponding access point.
2. The system of claim 1, wherein the bias drive module comprises: the bias voltage generation submodule and the time sequence driving submodule;
the bias voltage generation submodule is used for generating various bias voltages required by the operation of the area array infrared detector;
and the time sequence driving submodule is used for driving the detector time sequence signal output by the signal processing module to obtain a driving time sequence signal matched with the requirement of the area array detector.
3. The system of claim 2, wherein the bias voltage generation submodule is configured to generate a plurality of bias voltages required for the operation of the area array infrared detector according to the driving current, the noise and the tolerance requirement.
4. The system of claim 3, wherein the bias voltage generation submodule is configured to: when the noise and tolerance requirements meet a first preset requirement and the photodiode bias voltage needs to be accurately adjusted, generating a high-precision reference voltage signal according to a voltage reference with low noise, low temperature drift and high radiation resistance; dividing the quasi-voltage signal through a voltage dividing resistor network to obtain a divided voltage signal; driving and amplifying the voltage division signal through an operational amplifier with high common mode rejection ratio and low noise to obtain bias voltage;
the voltage division resistor network consists of an adjustable potentiometer and a precision resistor;
the adjustable potentiometer is used for adjusting the voltage dividing resistance value in real time and dividing the reference voltage signal to obtain the optimal photodiode bias voltage;
and the precision resistor is used for determining a precision voltage dividing resistance value according to the resistance value adjusted by the adjustable potentiometer to obtain the bias voltage.
5. The system of claim 3, wherein the bias voltage generation submodule is configured to:
when the noise and tolerance requirements meet a second preset requirement and the driving current is larger than or equal to 100mA, a high-current and low-noise voltage signal is generated through the low-dropout linear regulator with low noise and high radiation resistance, and the required power supply voltage is generated through the low-pass filter circuit.
6. The system of claim 1, wherein the signal processing module comprises: the device comprises a conditioning module, a 14bits analog-to-digital converter, an FPGA and a high-speed serial data transmission circuit;
the conditioning module is used for conditioning 4 paths of analog electric signals output by the area array infrared detector to obtain analog signals matched with an input interface of the 14bits analog-to-digital converter;
the 14bits analog-to-digital converter is used for performing analog-to-digital conversion on the conditioned 4 paths of analog signals to obtain 4 paths of 14bits digital data;
the FPGA is used for performing oversampling point selection, mean value filtering, data combining, pixel response non-uniformity correction, blind pixel replacement and data arrangement on 4 paths of 14bits digital data to obtain 1 path of high-speed serial image data;
and the high-speed serial data transmission circuit is used for transmitting the 1-path high-speed serial image data to image acquisition equipment.
7. The system of claim 1, wherein the high-speed clock management module comprises: the circuit comprises a reference clock, a voltage-controlled crystal oscillator, a clock synchronization debouncing chip and a loop filter; the reference clock, the voltage-controlled crystal oscillator, the clock synchronization debouncing chip and the loop filter form a phase-locked loop circuit;
the reference clock is used for generating a reference clock signal;
the clock synchronization debouncing chip is used for carrying out frequency division and phase discrimination on a clock output by the voltage-controlled crystal oscillator and generating control current according to a phase discrimination result;
the loop filter is used for converting the control current into a low-noise control voltage signal; the low-noise control voltage signal is used for controlling the output frequency of the voltage-controlled crystal oscillator;
and the voltage-controlled crystal oscillator is used for locking the phase of an output clock with the phase of a reference clock and removing jitter under the control of the low-noise control voltage signal.
8. The system of claim 7, wherein the clock synchronization debounce chip comprises: the device comprises a phase discriminator, a frequency divider and a charge pump;
the frequency divider is used for dividing the frequency of the clock signal output by the voltage-controlled crystal oscillator;
the phase discriminator is used for carrying out phase comparison on the clock signal subjected to frequency division by the frequency divider and the reference clock signal to obtain a comparison result;
the charge pump is used for outputting control current according to a phase comparison result output by the phase discriminator;
the frequency divider is also used for dividing the frequency of the voltage-controlled crystal oscillator after being locked and removed, outputting 4 pairs of 50MHz LVPECL differential clocks to provide conversion clocks for the 4 paths of analog-to-digital converters, and outputting two paths of 100MHz LVCMOS single-ended clocks to provide main clocks for the FPGA and the high-speed serial transmission circuit.
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| CN109977062A (en) * | 2019-03-14 | 2019-07-05 | 建荣半导体（深圳）有限公司 | A kind of method, apparatus and electronic equipment of software realization Serial data receiving |
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