CN108874020B - Current mode array SPAD gain uniformity self-adaptive control circuit - Google Patents

Abstract

The invention discloses a current mode array SPAD gain uniformity self-adaptive control circuit, which comprises: a common current bias module, a plurality of single pixel circuits corresponding to the number of SPAD pixel units in the array SPAD, wherein each single pixel circuit comprises a current monitoring module and an active quenching module(ii) a The current monitoring module consists of an operational amplifier and a current mirror, and the active quenching module consists of a comparator and a quenching tube and is used for triggering work according to an output voltage signal of the current monitoring module and controlling the quenching tube to generate an avalanche quenching signal; the current monitoring module is composed of an operational amplifier OP_iA PMOS transistor M_{4_i}And PMOS transistor M_{5_i}The cascode current mirror is composed of an NMOS transistor M_{i_L}And NMOS transistor M_{i_R}The formed current mirror is formed. The invention adopts the current mode control method to adaptively control the reverse bias voltage of the SPAD, inhibits the gain nonuniformity problem of the array SPAD, overcomes the defect of complex circuit in the traditional voltage mode, and reduces the area and the power consumption.

Description

Current mode array SPAD gain uniformity self-adaptive control circuit

Technical Field

The invention relates to a current mode array SPAD gain uniformity self-adaptive control circuit, and belongs to the technical field of single photon detection.

Background

Avalanche Photodiodes (APDs) have the advantages of small weight, low power consumption, high quantum efficiency, insensitivity to magnetic fields and radiation, convenience in integration, and the like, and high-performance APDs operating in the geiger mode have single photon detection capability and are called single photon avalanche photodiodes (SPADs). Therefore, the single photon detection system based on the APD becomes an important research direction and can be used in the related fields of laser radar three-dimensional imaging, environment detection, national defense safety, medical detection and the like.

At present, single photon detectors are developing towards integration, miniaturization and arraying, and especially with the continuous expansion of the scale of array detection application, higher requirements are provided for the uniformity of the detectors. For array SPAD, due to the influence of process dispersion, the uniformity of performance parameters of the detector is difficult to ensure, so that under the same reverse bias condition, due to the difference of the reverse breakdown voltages of the SPAD, the distribution of overdrive voltages of the SPAD is not uniform, the dispersion change of the SPAD avalanche current is caused, namely the gain of the array SPAD is different under the same reverse bias voltage condition. For the SPAD pixel unit with lower gain, the voltage pulse induced by the avalanche current is difficult to effectively distinguish from the noise voltage and cannot be detected, so that larger error is brought to array SPAD detection. There is therefore a need to address the issue of array SPAD gain non-uniformity in array applications.

The traditional solution is to directly control the reverse bias voltage of the SPAD by using a voltage mode, so that the over-bias voltage of the detector is consistent, and the gain is consistent. However, in array applications, these methods need to provide an adjustable reverse bias voltage for the detector of each pixel unit, and also need to know the breakdown voltage of each detector in advance. Such a control method increases the workload of preliminary preparation, increases the number of control terminals, and increases the complexity of the circuit structure, and such a gain control method is difficult to implement as the array scale is expanded and the pixel unit area is reduced.

Disclosure of Invention

The invention aims to solve the technical problems that in order to overcome the nonlinear problem of SPAD detection sensitivity caused by process discreteness, weaken the influence caused by the nonuniformity of performance parameters of a detector and simultaneously avoid the problem of complex circuits caused by the traditional voltage mode reverse bias voltage control, a current mode array SPAD gain uniformity self-adaptive control circuit is provided, the current mode reverse bias voltage control idea is introduced, and the self-adaptive control of array SPAD gain is realized.

The invention specifically adopts the following technical scheme to solve the technical problems:

a current mode array SPAD gain uniformity adaptive control circuit comprising:

the common current bias module is composed of a constant current source and a current mirror circuit and is used for providing the same constant current source current for each SPAD pixel unit of the array SPAD through the current mirror circuit;

the array SPAD comprises a plurality of single pixel circuits corresponding to the number of SPAD pixel units in the array SPAD, wherein each single pixel circuit comprises a current monitoring module and an active quenching module; the current monitoring module is composed of an operational amplifier and a current mirror and is used for detecting the working state of an SPAD pixel unit in the array SPAD, generating different voltage signals to carry out gain self-adaptive control on the SPAD pixel unit in the array SPAD, and meanwhile, taking an output voltage signal as an input signal of the active quenching module; the active quenching module consists of a comparator and a quenching tube and is used for triggering work according to the output voltage signal of the current monitoring module and controlling the quenching tube to generate an avalanche quenching signal;

wherein, the current monitoring module comprises operational amplifier and current mirror, specifically is: by an operational amplifier OP_iA PMOS transistor M_{4_i}And PMOS transistor M_{5_i}The cascode current mirror is composed of an NMOS transistor M_{i_L}And NMOS transistor M_{i_R}The PMOS tube M_{4_i}Grid and PMOS transistor M_{5_i}The grid electrodes of the PMOS transistors are respectively short-circuited to the common current bias module and the PMOS transistor M_{4_i}Is connected with a power supply V_DDAnd PMOS tube M_{4_i}Drain electrode of the PMOS tube M_{5_i}A source electrode of (a); the NMOS tube M_{i_L}And NMOS transistor M_{i_R}Is short-circuited with the grid, and an NMOS transistor M_{i_L}Drain electrode of the PMOS tube M_{5_i}Drain electrode of (1), NMOS tube M_{i_R}The drain electrode of the NMOS transistor is connected with the anode of the SPAD and the NMOS transistor M_{i_L}And NMOS transistor M_{i_R}The source of (2) is grounded; the operational amplifier OP_iThe non-inverting input end and the inverting input end of the NMOS are respectively connected with an NMOS tube M_{i_L}And the anode of the SPAD, and an operational amplifier OP_iThe output end of the NMOS transistor M is connected to the NMOS transistor M simultaneously_{i_L}And M_{i_R}A gate electrode of (1); and taking the anode of the SPAD as the output end of the current monitoring module.

Further, as a preferred technical solution of the present invention: the common current bias module is composed of a constant current source and a current mirror circuit, and specifically comprises the following components: by a constant current source I_DCNMOS transistor M₁NMOS transistor M₂NMOS transistor M₆PMOS transistor M₃PMOS transistor M₄And PMOS transistor M₅Is formed of a constant current source I_DCConnecting NMOS tube M₁Drain electrode of (1), NMOS tube M₁The grid and drain electrode are short-circuited and simultaneously connected with an NMOS (N-channel metal oxide semiconductor) tube M₂A gate electrode of (1); the NMOS tube M₂Drain electrode of the PMOS tube M₃And PMOS transistor M₃Grid-drain short circuit and PMOS (P-channel metal oxide semiconductor) tube M₅A gate electrode of (1); the PMOS tube M₅Source electrode of the PMOS tube M₄And a PMOS transistor M₄Grid electrode of the PMOS tube M₅A drain electrode of (1); the NMOS tube M₆Drain electrode of the PMOS tube M₅A drain electrode of (1); the NMOS tube M₁、M₂、M₆All the source electrodes of (1) are grounded, and a PMOS tube M₃PMOS transistor M₄The source electrodes are all connected with a power supply V_DD。

Further, as a preferred technical solution of the present invention: the active quenching module consists of a comparator and a PMOS quenching tube M_{q_i}The structure specifically comprises the following steps: comparator cmp_iIs connected to the current monitoring module, and a comparator cmp_iThe output end of the PMOS quenching tube M is connected with the PMOS quenching tube_{q_i}And a PMOS quench tube M_{q_i}Source electrode of the transistor is connected with a power supply V_DDAnd its drain connected to the anode of the SPAD.

Further, as a preferred technical solution of the present invention: the differential input structure shared by the operational amplifier and the comparator specifically comprises: by PMOS tube M_{7_i}PMOS transistor M_{8_i}PMOS transistor M_{9_i}PMOS transistor M_{16_i}PMOS transistor M_{17_i}NMOS transistor M_{10_i}NMOS transistor M_{11_i}NMOS transistor M_{12_i}NMOS transistor M_{13_i}NMOS transistor M_{14_i}NMOS transistor M_{15_i}Form an operational amplifier OP_iAnd a PMOS transistor M_{7_i}PMOS transistor M_{8_i}PMOS transistor M_{9_i}PMOS transistor M_{16_i}PMOS tube Mp_{_i}NMOS transistor M_{10_i}NMOS transistor M_{11_i}NMOS transistor M_{12_i}NMOS transistor M_{13_i}NMOS transistor M_{14_i}NMOS tube Mn_{_i}And an inverter INV_iForm comparator cmp_i。

Further, as a preferred technical solution of the present invention: the power supply further comprises an enabling PMOS transistor M for controlling the working state of the whole circuit_{en_i}Wherein PMOS transistor M_{en_i}Source electrode of the transistor is connected with a power supplyV_DDAnd the grid electrode of the transistor is connected with an enable control signal EN, and the drain electrode of the transistor is connected with the anode of the SPAD.

By adopting the technical scheme, the invention can produce the following technical effects:

the invention uses current mode bias, can self-adaptively control SPAD reverse bias voltage through the OP control type current monitoring module, greatly simplifies the work of array control compared with the traditional voltage control mode, and can effectively realize the gain consistency detection of the array type SPAD. Compared with the traditional circuit, the invention has the following advantages:

(1) the invention adopts a current mode array SPAD gain uniformity self-adaptive control circuit, uniformly supplies current to the SPAD in the array by using a current mirror through a common current bias module, judges the working state of the SPAD by detecting the current magnitude of the SPAD, and performs self-adaptive feedback control on the reverse bias voltage of the SPAD, thereby realizing the gain uniformity detection and control of the array SPAD, simplifying the design of the circuit while inhibiting nonlinear errors, and reducing the expenses of power consumption and area.

(2) The invention adopts an OP control type current monitoring module to generate different voltage signals according to different SPAD working states, thereby completing the self-adaptive control of the SPAD gain. The operational amplifier in the detection module can solve the influence of the channel length modulation effect on the matching of the current mirror, and can greatly expand the adjustable lower limit range of the SPAD anode potential.

(3) The invention does not need extra reference voltage when detecting avalanche, the non-inverting input end and the inverting input end of the comparator are respectively connected with the non-inverting input end and the inverting input end of the operational amplifier in the OP control type current monitoring module, and simultaneously the comparator and the operational amplifier share a differential input structure, thereby reducing the circuit area consumption. The operational amplifier in the OP control type current monitoring module and the comparator in the active quenching module share a differential input structure, and the operational amplifier can increase nonlinearity to improve gain, bandwidth and slew rate and is beneficial to improving the speed of the comparator.

Drawings

Fig. 1 is a graph of the V-I characteristic of a prior art avalanche photodiode.

Fig. 2 is a voltage mode bias schematic diagram of SPAD in the prior art.

Fig. 3 is a SPAD current mode bias schematic of the present invention.

Fig. 4 is a structural diagram of the adaptive control circuit for gain uniformity of SPAD in current mode array according to the present invention.

Fig. 5 is a schematic diagram of an OP control type current monitoring module according to the present invention.

FIG. 6 is a circuit diagram of a shared structure of an operational amplifier and a comparator in the present invention.

Detailed Description

The following describes embodiments of the present invention with reference to the drawings.

The V-I characteristic curve of the avalanche photodiode is shown in figure 1, the voltage and the current of the avalanche photodiode are in a nonlinear relation, the working area of the diode can be divided into a cut-off area, a linear area, a low-gain Geiger area and a high-gain avalanche area, the gain characteristic of the diode is reflected by the current of the diode, and the gain calibration circuit based on the current mode realizes the self-adaptive control of the gain by detecting the current change of an SPAD detector.

The V-I characteristic curve of an avalanche photodiode is steep in the geiger mode, as shown in fig. 2, where the reverse bias voltage changes slightly and the reverse bias current changes dramatically. Due to the discrete influence of the process, if the SPAD array is simply made to work under the same reverse bias, the actual over-bias voltage of each SPAD is not consistent, and further the current and the gain of each SPAD are different, so that the gain non-uniformity problem of the array SPAD is caused.

The traditional method for solving the problems is to arrange a reverse bias voltage control circuit in a voltage mode bias circuit, and ensure the uniformity of the over-bias voltage of each pixel unit by controlling the SPAD reverse bias voltage, thereby ensuring the gain uniformity of the array SPAD. In array applications, this control method becomes increasingly infeasible as the array scale expands and the pixel cell area shrinks.

In order to avoid the defect that a reverse bias voltage control circuit in a voltage mode is too complex, the invention provides a current mode array SPAD gain uniformity self-adaptive control circuit. Different from the idea of pixel-by-pixel reverse bias voltage control in the traditional method, the invention adopts a control idea based on a current mode, and leads the SPAD of each pixel in the array to generate the same static current through circuit control, thereby leading the over-bias voltage of the SPAD to be consistent and achieving the purpose of gain consistency. In the application process of the SPAD, the current is greatly changed along with the change of a dynamic bias condition, the current is closely related to the gain, the steady-state current is directly controlled in a current bias mode, and the reverse bias voltage can be self-adaptively matched with the requirement of the steady-state current, namely if the steady state exists, the reverse bias voltage is fixed, but each pixel is different. As shown in FIG. 3, when the SPAD is biased in the Geiger mode, the V-I characteristic curve is very steep, and if the reverse bias current of each SPAD pixel unit in the array is the same at this time, the over-bias voltage and the gain of each SPAD pixel unit are ensured to be approximately consistent. Therefore, the greatest advantage of using current biasing is: the final adjusted target bias current for each pixel is uniform, and the current bias can be conveniently delivered through a current mirror.

As shown in fig. 4, the present invention provides a current mode array SPAD gain uniformity adaptive control circuit, which mainly includes a common current bias module, and a plurality of single pixel circuits corresponding to the number of SPAD pixel units in the array SPAD, that is, the number i of the single pixel circuits is 1,2,3 …, and the specific value is determined by the number of the corresponding SPAD pixel units, wherein each single pixel circuit includes a current monitoring module and an active quenching module, and an enable tube M_{en_i}. The common current bias module consists of a constant current source and a current mirror circuit and is used for providing the same constant current source current for each SPAD pixel unit of the array SPAD through the current mirror circuit; each single pixel circuit in the single pixel circuits comprises a current monitoring module and an active quenching module, wherein the current monitoring module consists of an operational amplifier and a current mirror and is used for detecting the working state of an SPAD pixel unit in the array SPAD and generating different voltage signals to the SPAD in the array SPADThe SPAD pixel unit performs gain self-adaptive control, and simultaneously takes an output voltage signal as an input signal of the active quenching module; the active quenching module consists of a comparator and a quenching tube and is used for triggering work according to the output voltage signal of the current monitoring module and controlling the quenching tube to generate an avalanche quenching signal.

Specifically, as shown in fig. 4, the common current bias module is composed of a constant current source and a current mirror circuit, and supplies the same current to each pixel unit of the array SPAD, mainly composed of a constant current source I_DCNMOS transistor M₁NMOS transistor M₂NMOS transistor M₆PMOS transistor M₃PMOS transistor M₄And PMOS transistor M₅Is formed of a constant current source I_DCConnecting NMOS tube M₁Drain electrode of (1), NMOS tube M₁The grid and drain electrode are short-circuited and simultaneously connected with an NMOS (N-channel metal oxide semiconductor) tube M₂A gate electrode of (1); the NMOS tube M₂Drain electrode of the PMOS tube M₃And PMOS transistor M₃Grid-drain short circuit and PMOS (P-channel metal oxide semiconductor) tube M₅A gate electrode of (1); the PMOS tube M₅Source electrode of the PMOS tube M₄And a PMOS transistor M₄Grid electrode of the PMOS tube M₅A drain electrode of (1); the NMOS tube M₆Drain electrode of the PMOS tube M₅A drain electrode of (1); the NMOS tube M₁、M₂、M₆All the source electrodes of (1) are grounded, and a PMOS tube M₃PMOS transistor M₄The source electrodes are all connected with a power supply V_DD. Wherein, the NMOS transistor M₁、M₂、M₆Form a multi-path current mirror, a PMOS tube M₃、M₄、M₅Form a wide-swing cascode current mirror transmission circuit, and use a constant current source I_DCIs transmitted to each pixel unit using PMOS transistor M₄And M₅The wide-swing cascode current mirror is formed, so that the influence of the channel length modulation effect on the matching characteristic of the current mirror can be reduced, and meanwhile, the wide swing can increase the adjusting range of the SPAD anode. The common current bias module can ensure that the finally adjusted target bias current of each pixel unit is consistent, and greatly simplifies a large array.

Each current monitoring module consists of an operational amplifier and a current mirror,mainly composed of an operational amplifier OP_iA PMOS transistor M_{4_i}And PMOS transistor M_{5_i}The cascode current mirror is composed of an NMOS transistor M_{i_L}And NMOS transistor M_{i_R}The current mirror is formed, wherein i is 1,2 and 3 …, and the specific value is determined by the number of the corresponding pixel unit. The PMOS tube M_{4_i}Grid and PMOS tube M in common current bias module₄Is shorted, and PMOS transistor M_{5_i}The grid electrode of the transistor is short-circuited to a PMOS transistor M in the common current bias module₅And a PMOS transistor M_{4_i}Is connected with a power supply V_DDAnd PMOS tube M_{4_i}Drain electrode of the PMOS tube M_{5_i}A source electrode of (a); the NMOS tube M_{i_L}And NMOS transistor M_{i_R}Is short-circuited with the grid, and an NMOS transistor M_{i_L}Drain electrode of the PMOS tube M_{5_i}Drain electrode of (1), NMOS tube M_{i_R}The drain electrode of the NMOS transistor is connected with the anode of the SPAD and the NMOS transistor M_{i_L}And NMOS transistor M_{i_R}The source of (2) is grounded; the operational amplifier OP_iThe non-inverting input end and the inverting input end of the NMOS are respectively connected with an NMOS tube M_{i_L}And the anode of the SPAD, and an operational amplifier OP_iThe output end of the NMOS transistor M is connected to the NMOS transistor M simultaneously_{i_L}And M_{i_R}A gate electrode of (1); and taking the anode of the SPAD as the output end of the current monitoring module.

The active quenching module consists of a comparator and a PMOS quenching tube M_{q_i}The structure specifically comprises the following steps: comparator cmp_iThe input end of the comparator cmp is connected with the current monitoring module and the comparator cmp_iAnd the non-inverting input and the inverting input of the operational amplifier OP_iThe connection method of the non-inverting input end and the inverting input end is completely consistent, so that the non-inverting input end and the inverting input end can share a differential input structure; and comparator cmp_iThe output end of the PMOS quenching tube M is connected with the PMOS quenching tube_{q_i}And a PMOS quench tube M_{q_i}Source electrode of the transistor is connected with a power supply V_DDAnd its drain connected to the anode of the SPAD.

The enabling PMOS transistor M_{en_i}For controlling the working state of the whole circuit, wherein the PMOS transistor M_{en_i}Is connected with a power supply V_DDAnd its gate connected to the enable control signal EN and drain connected to the anode of the SPAD. The control circuit enables the PMOS transistor M_{en_i}DeterminingThe working state of the whole circuit. In each pixel, the SPAD can normally work only when the EN enable signal is in high level, and when the EN enable signal is in low level, the enable tube is conducted, and the anode of the SPAD is pulled to V_DDThe pixel cell is in a quenched state.

A schematic diagram of the OP control type current monitoring module is shown in fig. 5. Approximate pseudo-short characteristics can be achieved by using the open-loop gain of the operational amplifier, i.e. there is always an input voltage V of the shared differential input structure_Ai＝V_BiGood matching of current transmission, A_i、B_iThe dot potential can vary over a wide range depending on the variation of the reverse bias breakdown voltage of the SPAD. The maximum value and the minimum value of the reverse bias breakdown voltage of the SPAD are respectively set as V_BR,maxAnd V_BR,minMedian (mean) value of V_BR0The variation range of breakdown voltage relative to the median value is + -DeltaV_BR. Thus, for a fixed current bias, when the reverse bias voltage of the SPAD is large, B_iThe point potential is lowered to increase the reverse bias voltage adaptively, A_iThe point potential falls synchronously with the following, A_iAnd B_iThe lowest point of the point potential can approach 0 theoretically, and the NMOS tube M_{i_L}And NMOS transistor M_{i_R}The current mirror is constructed to enter the linear region but still maintain the linear current mirror relationship. After entering the linear current mirror region, OP_iThe output of (A) is obviously improved, the grid voltage potential of the current mirror is increased, and the current is kept unchanged, so that_i、B_iThe lower the potential at two points is, OP_iThe higher the output of (c). Similarly, when the reverse bias breakdown voltage of the SPAD is smaller, A is adaptively controlled_i、B_iThe higher the potential at the two points, at A_i、B_iUnder the premise that the point potential is higher, the gate voltage of the current mirror MOS tube is lower and reaches saturation (approximately constant). A. the_i、B_iThe input constant current source should maintain enough V under the highest potential of the point_DSVoltage and input current are maintained.

The OP control type current monitoring module can detect the current of the SPAD pixel unit to judge the working state of the SPAD pixel unit, generate different voltage signals to carry out gain self-adaptive control on the SPAD pixel unit and simultaneously serve as an input signal of the active quenching moduleNumber (n). Let the current on the SPAD pixel cell be I_QIf I is_QApproaching 0, it means that the SPAD pixel unit is in linear mode, at this time B_iThe dot potential is around 0V. If I_QIf the output current of the detection circuit is larger than the current on the SPAD pixel unit, V is at the moment_BiWill automatically decrease, causing the current on the SPAD pixel cell to increase, but at the same time V_BiThe small variations of (a) have little effect on the current of the detection circuit. The self-adaptive control of the SPAD reverse bias voltage is realized through the process, and through the self-adaptive control process, the current on the SPAD pixel unit is equal to the output current of the current detection circuit. In the process, the reverse bias voltage of the array SPAD is changed in a self-adaptive mode according to the current preset by the common current bias module, so that the over-bias voltage of each SPAD pixel unit in the array is consistent, and the consistency of the gain is further ensured.

The active quenching module is composed of a comparator cmp_iAnd a quenching tube M_{q_i}And (4) forming. B is_iComparators with point potentials varying over a wide range and unable to be driven with a fixed reference potential, B_iThe point is connected to the anode of SPAD and then to the comparator cmp_iThe inverting input of the comparator is connected with B_iPoint potential, in-phase input terminal A_iPoint potential, in static state (without photon induction) A_iAnd the potentials of the two points Bi are the same, but the comparator outputs a high level through the action of the introduced equivalent input offset voltage. When the SPAD pixel unit is in a high-gain avalanche region, the generated large amount of avalanche current can cause the current of the OP control type current monitoring module to increase rapidly, and at the moment B_iThe point potential rises rapidly and exceeds A_iPoint potential, resulting in comparator cmp_iThe output flips to a low level. In this process, the operational amplifier OP_iThe controlled current mirror is in an unbalanced state in a transient state, and the operational amplifier OP_iThe output potential is reduced, resulting in the NMOS transistor M_{i_L}And M_{i_R}Off, I_inInput current pair A_iCharging of point capacitor, A_iThe point potential rises when A_iPoint capacitance and B_iPoint capacitance is comparable (B)_iPoint capacitance is approximately SPAD junction capacitance) of the transistor, and_inabout two orders of magnitude less than the SPAD avalanche current, so a_iThe rising speed of the point potential is less than B_iThe dot potential rise rate is about two orders of magnitude. Even if A_iPoint capacitance less than B_iOne order of magnitude of point capacitance, A_iThe dot potential rising speed is still slow. Thus, A_i、B_iThe two points form differential voltage, a comparator can be used for voltage comparison, and a pulse signal generated by the comparator meets the detection requirements of the quenching tube and a subsequent circuit.

When comparator cmp_iWhen a negative pulse is output, the quenching tube M_{q_i}On, B_iThe point potential is pulled up to V_DDUnder control of A_iAdaptive ramp-up to supply voltage V_DDIin is 0, operational amplifier OP_iOutput low level, NMOS transistor M_{i_L}And M_{i_R}The tube is off, the bias circuit current is 0, and the circuit is in the off mode. After the reset signal comes, B_iPoint down to 0, operational amplifier OP_iOutput goes high, NMOS transistor M_{i_L}And M_{i_R}The tube is conducted, the current mirror starts to regulate again, and after a certain control time delay, A_i、B_iThe two points are restored to the static points in the original mode to be tested. The recovery process is performed by an operational amplifier OP_iBandwidth and swing control of the operational amplifier OP_iThe bandwidth and SR need to be as large as possible. Simultaneously according to an operational amplifier OP_iThe functional requirement in the circuit, the input needs to adopt P type differential pair to adapt to A_i、B_iLower common mode point, operational amplifier OP_iThe output common mode range of (1) should be as wide as possible to satisfy the requirement of a pair, NMOS transistor M_{i_L}And M_{i_R}Various requirements for switching the tube on and off.

Operational amplifier OP_iAnd comparator cmp_iAre identical, so both may share a differential input structure. As shown in fig. 6, is an operational amplifier OP_iAnd comparator cmp_iThe specific circuit structure of (1). By adopting an OTA circuit, the differential input + the load form an OP structure, and simultaneously the same differential input + the other load + INV form a comparator junctionConstruct, differential pair sharing.

Specifically, the differential input structure shared by the operational amplifier and the comparator, as shown in fig. 6, specifically includes: by PMOS tube M_{7_i}PMOS transistor M_{8_i}PMOS transistor M_{9_i}PMOS transistor M_{16_i}PMOS transistor M_{17_i}PMOS tube Mp_{_i}NMOS transistor M_{10_i}NMOS transistor M_{11_i}NMOS transistor M_{12_i}NMOS transistor M_{13_i}NMOS transistor M_{14_i}NMOS transistor M_{15_i}NMOS tube Mn_{_i}And an inverter INV_iAnd (4) forming. Wherein, the PMOS transistor M_{7_i}PMOS transistor M_{8_i}PMOS transistor M_{9_i}PMOS transistor M_{16_i}PMOS transistor M_{17_i}NMOS transistor M_{10_i}NMOS transistor M_{11_i}NMOS transistor M_{12_i}NMOS transistor M_{13_i}NMOS transistor M_{14_i}NMOS transistor M_{15_i}Form an operational amplifier OP_iAnd PMOS transistor M thereof_{7_i}Is a constant current bias tube, PMOS tube M_{8_i}、M_{9_i}Is a differential input tube, an NMOS tube M_{10_i}、M_{11_i}、M_{14_i}、M_{15_i}A transmission output stage transistor for load current mirror, PMOS transistor M_{16_i}、M_{17_i}Form a current mirror, an NMOS tube M_{12_i}、M_{13_i}Forming a cross-coupled pair. And a PMOS transistor M_{7_i}PMOS transistor M_{8_i}PMOS transistor M_{9_i}PMOS transistor M_{16_i}PMOS tube Mp_{_i}NMOS transistor M_{10_i}NMOS transistor M_{11_i}NMOS transistor M_{12_i}NMOS transistor M_{13_i}NMOS transistor M_{14_i}NMOS tube Mn_{_i}And an inverter INV_iForm comparator cmp_i。

The circuit connection specifically comprises: the PMOS tube M_{7_i}The source electrodes are all connected with a power supply V_DDAnd PMOS transistor M_{7_i}The grid of the PMOS transistor M is connected with the output of the common current bias module_{7_i}The drain electrode of the PMOS tube M is connected with the PMOS tube M simultaneously_{8_i}PMOS transistor M_{9_i}Source electrode of (D), the PMOS tube M_{8_i}PMOS transistor M_{9_i}The grids of the two differential pairs are respectively connected with the input voltage V of the shared differential pair_AiAnd V_Bi(ii) a The NMOS tube M_{10_i}OfDrain electrode short circuit connected with PMOS transistor M_{9_i}Drain electrode of (1) and NMOS tube M_{14_i}A gate electrode of (1); the NMOS tube M_{11_i}The grid and the drain are in short circuit and are simultaneously connected with a PMOS tube M_{8_i}Drain electrode of (1) and NMOS tube M_{15_i}A gate electrode of (1); the NMOS tube M_{12_i}Grid and NMOS tube M_{13_i}Is short-circuited while the NMOS transistor M_{12_i}Grid electrode of the PMOS tube M_{8_i}Drain electrode of (1) and NMOS tube M_{11_i}、M_{15_i}、Mn_{_i}A gate electrode of (1); the NMOS tube M_{13_i}Grid and NMOS tube M_{12_i}Is short-circuited while the NMOS transistor M_{13_i}Grid electrode of the PMOS tube M_{9_i}Drain electrode of (1) and NMOS tube M_{10_i}、M_{14_i}A gate electrode of (1); the PMOS tube M_{16_i}The grid and the drain are in short circuit and are simultaneously connected with an NMOS tube M_{14_i}And PMOS transistor M_{16_i}Grid and PMOS transistor M_{17_i}、Mp_{_i}The grid of (2) is short-circuited; the operational amplifier OP_iThe output of the PMOS transistor M is connected at the same time_{17_i}And NMOS transistor M_{15_i}And an inverter INV_iIs simultaneously connected with a PMOS tube Mp_{_i}And NMOS tube Mn_{_i}And a PMOS transistor M_{16_i}、M_{17_i}、Mp_{_i}The source electrodes are all connected with a power supply V_DD(ii) a The NMOS tube M_{10_i}、M_{11_i}、M_{12_i}、M_{13_i}、M_{14_i}、M_{15_i}、Mn_{_i}The source electrodes of the first and second transistors are all grounded; and, inverter INV_iAs the comparator cmp_iTo output of (c).

The introduction of artificial mismatch and offset in the load of the comparator is equivalent to the introduction of an input offset voltage in the comparator, but since there cannot be offset in the operational amplifier, no offset is introduced in the shared differential pair structure. In FIG. 6, PMOS transistor Mp_{_i}And NMOS tube Mn_{_i}The output of which constitutes the output of the comparator, which may be connected to the inverter INV_iShaping or adjusting the polarity. PMOS tube Mp_{_i}And NMOS tube Mn_{_i}The width-length ratio of the two transistors needs to be reasonably set, and the proportional relation of the two transistors relative to the MOS transistors at the same position in the operational amplifier changes. At an input voltage V_Ai＝V_BiIn the static state of (a) of (b),the comparator has a high output level due to the offset, and when the comparator senses avalanche current, the voltage V is high_Bi>V_AiAnd outputs a low level. In the structure shown in FIG. 6, a PMOS transistor M is required_{7_i}Additionally providing bias to determine the current I of the branch in which it is located_BiAn operational amplifier OP_iIn part, the non-linearity can also be increased to improve gain, bandwidth and slew rate, as well as to facilitate increasing comparator speed.

In conclusion, the invention adopts the current mode control method to adaptively control the reverse bias voltage of the SPAD, inhibits the gain nonuniformity problem of the array SPAD, overcomes the defect of complex circuit of the traditional voltage mode, reduces the area and the power consumption, is more suitable for array application, and realizes the adaptive control of the gain uniformity of the array SPAD.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims (6)

1. A current mode array SPAD gain uniformity adaptive control circuit, comprising:

the common current bias module is composed of a constant current source and a current mirror circuit and is used for providing the same constant current source current for each SPAD pixel unit of the array SPAD through the current mirror circuit;

the array SPAD comprises a plurality of single pixel circuits corresponding to the number of SPAD pixel units in the array SPAD, wherein each single pixel circuit comprises a current monitoring module and an active quenching module; the current monitoring module is composed of an operational amplifier and a current mirror and is used for detecting the working state of an SPAD pixel unit in the array SPAD, generating different voltage signals to carry out gain self-adaptive control on the SPAD pixel unit and taking an output voltage signal as an input signal of the active quenching module; the active quenching module consists of a comparator and a quenching tube and is used for triggering work according to the output voltage signal of the current monitoring module and controlling the quenching tube to generate an avalanche quenching signal;

whereinThe current monitoring module is composed of an operational amplifier and a current mirror, and specifically comprises: by an operational amplifier OP_iA PMOS transistor M_{4_i}And PMOS transistor M_{5_i}The cascode current mirror is composed of an NMOS transistor M_{i_L}And NMOS transistor M_{i_R}The current mirror is formed, wherein i is the serial number of SPAD pixel units in the array SPAD, and the value is a natural number more than 1; the PMOS tube M_{4_i}Grid and PMOS transistor M_{5_i}The grid electrodes of the PMOS transistors are respectively short-circuited to the common current bias module and the PMOS transistor M_{4_i}Is connected with a power supply V_DDAnd PMOS tube M_{4_i}Drain electrode of the PMOS tube M_{5_i}A source electrode of (a); the NMOS tube M_{i_L}And NMOS transistor M_{i_R}Is short-circuited with the grid, and an NMOS transistor M_{i_L}Drain electrode of the PMOS tube M_{5_i}Drain electrode of (1), NMOS tube M_{i_R}The drain electrode of the NMOS transistor is connected with the anode of the SPAD and the NMOS transistor M_{i_L}And NMOS transistor M_{i_R}The source of (2) is grounded; the operational amplifier OP_iThe non-inverting input end and the inverting input end of the NMOS are respectively connected with an NMOS tube M_{i_L}And the anode of the SPAD, and an operational amplifier OP_iThe output end of the NMOS transistor M is connected to the NMOS transistor M simultaneously_{i_L}And M_{i_R}A gate electrode of (1); the anode of the SPAD is used as the output end of the current monitoring module.

2. The current-mode array SPAD gain uniformity adaptive control circuit of claim 1, wherein: the common current bias module is composed of a constant current source and a current mirror circuit, and specifically comprises the following components: by a constant current source I_DCNMOS transistor M₁NMOS transistor M₂NMOS transistor M₆PMOS transistor M₃PMOS transistor M₄And PMOS transistor M₅Is formed of a constant current source I_DCConnecting NMOS tube M₁Drain electrode of (1), NMOS tube M₁The grid and drain electrode are short-circuited and simultaneously connected with an NMOS (N-channel metal oxide semiconductor) tube M₂A gate electrode of (1); the NMOS tube M₂Drain electrode of the PMOS tube M₃And PMOS transistor M₃Grid-drain short circuit and PMOS tube M connected at the same time₅A gate electrode of (1); the PMOS tube M₅Source electrode of the PMOS tube M₄And a PMOS transistor M₄Grid electrode of the PMOS tube M₅A drain electrode of (1); the NMOS tube M₆Drain electrode of the PMOS tube M₅A drain electrode of (1); the NMOS tube M₁、M₂、M₆All the source electrodes of (1) are grounded, and a PMOS tube M₃PMOS transistor M₄The source electrodes are all connected with a power supply V_DD。

3. The current-mode array SPAD gain uniformity adaptive control circuit of claim 1, wherein: the active quenching module consists of a comparator and a PMOS quenching tube M_{q_i}The structure specifically comprises the following steps: comparator cmp_iIs connected to the current monitoring module, and a comparator cmp_iThe output end of the PMOS quenching tube M is connected with the PMOS quenching tube_{q_i}And a PMOS quench tube M_{q_i}Source electrode of the transistor is connected with a power supply V_DDAnd its drain connected to the anode of the SPAD.

4. The current-mode array SPAD gain uniformity adaptive control circuit of claim 1, wherein: the operational amplifier and the comparator share a differential input structure.

5. The current mode array SPAD gain uniformity adaptive control circuit of claim 4, wherein: the differential input structure shared by the operational amplifier and the comparator specifically comprises: by PMOS tube M_{7_i}PMOS transistor M_{8_i}PMOS transistor M_{9_i}PMOS transistor M_{16_i}PMOS transistor M_{17_i}NMOS transistor M_{10_i}NMOS transistor M_{11_i}NMOS transistor M_{12_i}NMOS transistor M_{13_i}NMOS transistor M_{14_i}NMOS transistor M_{15_i}Form an operational amplifier OP_iAnd a PMOS transistor M_{7_i}PMOS transistor M_{8_i}PMOS transistor M_{9_i}PMOS transistor M_{16_i}PMOS tube Mp_{_i}NMOS transistor M_{10_i}NMOS transistor M_{11_i}NMOS transistor M_{12_i}NMOS transistor M_{13_i}NMOS transistor M_{14_i}NMOS tube Mn_{_i}And an inverter INV_iForm comparator cmp_i(ii) a Wherein, the PMOS tube M_{7_i}The source electrodes are all connected with a power supply V_DDAnd PMOS transistorM_{7_i}The grid of the PMOS transistor M is connected with the output of the common current bias module_{7_i}The drain electrode of the PMOS tube M is connected with the PMOS tube M simultaneously_{8_i}PMOS transistor M_{9_i}Source electrode of (D), the PMOS tube M_{8_i}PMOS transistor M_{9_i}The grid electrodes of the two-way differential input structure are respectively connected with an input voltage V of the shared differential input structure_AiAnd V_Bi(ii) a The NMOS tube M_{10_i}The grid and the drain are in short circuit and are simultaneously connected with a PMOS tube M_{9_i}Drain electrode of (1) and NMOS tube M_{14_i}A gate electrode of (1); the NMOS tube M_{11_i}The grid and the drain are in short circuit and are simultaneously connected with a PMOS tube M_{8_i}Drain electrode of (1) and NMOS tube M_{15_i}A gate electrode of (1); the NMOS tube M_{12_i}Grid and NMOS tube M_{13_i}Is short-circuited while the NMOS transistor M_{12_i}Grid electrode of the PMOS tube M_{8_i}Drain electrode of (1) and NMOS tube M_{11_i}、M_{15_i}、Mn_{_i}A gate electrode of (1); the NMOS tube M_{13_i}Grid and NMOS tube M_{12_i}Is short-circuited while the NMOS transistor M_{13_i}Grid electrode of the PMOS tube M_{9_i}Drain electrode of (1) and NMOS tube M_{10_i}、M_{14_i}A gate electrode of (1); the PMOS tube M_{16_i}The grid and the drain are in short circuit and are simultaneously connected with an NMOS tube M_{14_i}And PMOS transistor M_{16_i}Grid and PMOS transistor M_{17_i}、Mp_{_i}The grid of (2) is short-circuited; the operational amplifier OP_iThe output of the PMOS transistor M is connected at the same time_{17_i}And NMOS transistor M_{15_i}And an inverter INV_iIs simultaneously connected with a PMOS tube Mp_{_i}And NMOS tube Mn_{_i}And a PMOS transistor M_{16_i}、M_{17_i}、Mp_{_i}The source electrodes are all connected with a power supply V_DD(ii) a The NMOS tube M_{10_i}、M_{11_i}、M_{12_i}、M_{13_i}、M_{14_i}、M_{15_i}、Mn_{_i}The source electrodes of the first and second transistors are all grounded; and, inverter INV_iAs the comparator cmp_iTo output of (c).

6. The current-mode array SPAD gain uniformity adaptive control circuit of claim 1, wherein: also includes an enable for controlling the working state of the whole circuitPMOS tube M_{en_i}Wherein PMOS transistor M_{en_i}Is connected with a power supply V_DDAnd the grid electrode of the transistor is connected with an enable control signal EN, and the drain electrode of the transistor is connected with the anode of the SPAD.

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