CN111130506B - Stable pulse width conversion circuit triggered by pulse leading edge - Google Patents
Stable pulse width conversion circuit triggered by pulse leading edge Download PDFInfo
- Publication number
- CN111130506B CN111130506B CN201911283692.4A CN201911283692A CN111130506B CN 111130506 B CN111130506 B CN 111130506B CN 201911283692 A CN201911283692 A CN 201911283692A CN 111130506 B CN111130506 B CN 111130506B
- Authority
- CN
- China
- Prior art keywords
- resistor
- capacitor
- pulse width
- comparator
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 25
- 230000001960 triggered effect Effects 0.000 title claims abstract description 21
- 239000003990 capacitor Substances 0.000 claims description 48
- 230000005856 abnormality Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
- H03K2005/00208—Layout of the delay element using FET's using differential stages
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention provides a stable pulse width conversion circuit triggered by a pulse front edge, which converts an input random signal with a fluctuation pulse width to output a modulation signal with a fixed width, and the frequency of the modulation signal is consistent with the frequency of the random signal so as to meet the requirement of a radar system.
Description
Technical Field
The invention relates to the field of electronic power, in particular to a stable pulse width conversion circuit triggered by a pulse front edge.
Background
Along with the continuous development of power electronic technology, the industrialization process is deepened continuously, the application field of electronic devices is increased continuously, and the application environment is more complex and more severe. Such as high temperature, high humidity, low temperature, frost, etc., have higher requirements for the reliability and anti-interference capability of the circuit. Based on the characteristics of strong anti-interference capability, tracking prevention and strong concealment of the prior radar system, the invention requires that the transmitting frequency completely and randomly appears in a certain range, the frequency of the modulating signal completely follows the random transmitting frequency signal, and the modulating width is completely the same. It is very difficult to get a modulated signal that is the same frequency as the random signal and changes the input different pulse width to an output pulse width that is exactly identical. If the frequency synchronization and the pulse width cannot be completely consistent, the disorder of the modulation frequency can be caused, the modulation pulse width determines the energy of the transmitter, and the abnormality of the modulation pulse width can cause damage to the whole radar system.
Disclosure of Invention
In order to solve the above problems, the present invention proposes a stable pulse width conversion circuit triggered by a pulse leading edge to output a modulated signal with a synchronous frequency and a fixed pulse width.
The invention is realized by the following technical scheme:
the invention provides a stable pulse width conversion circuit triggered by a pulse front edge, which converts an input random signal with a fluctuation pulse width to output a modulation signal with a fixed width, wherein the frequency of the modulation signal is consistent with that of the random signal;
the stable pulse width conversion circuit triggered by the pulse front comprises a resistor R2, a resistor R3, a resistor R5, a resistor R6, a resistor R12, a resistor R13, a capacitor C2, a capacitor C3 and a comparator U9; wherein,
the resistor R2 and the resistor R3 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the resistor R2 and the resistor R3 is connected with the same-phase terminal of the comparator U9;
the resistor R5 and the resistor R6 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the resistor R5 and the resistor R6 is connected with an inverting terminal of the comparator U9;
the capacitor C2 and the capacitor C3 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the capacitor C2 and the capacitor C3 is connected with an inverting terminal of the comparator U9;
the input signal G1 is connected to the non-inverting terminal of the comparator U9 through the resistor R12, and to the inverting terminal of the comparator U9 through the resistor R13.
Further, the stable pulse width conversion circuit triggered by the pulse front edge further comprises a resistor R17, and the resistor R17 is connected between the output modulation signal and the non-inverting terminal of the comparator U9.
Further, the stable pulse width conversion circuit triggered by the pulse front edge further comprises a resistor R35, and the output modulation end is connected to the Vcc voltage through the resistor R35.
Further, the stable pulse width conversion circuit triggered by the pulse front edge further comprises a filter capacitor C16, and the filter capacitor C16 is connected between Vcc voltage and a ground terminal.
Further, the stable pulse width conversion circuit triggered by the pulse front edge further comprises a capacitor C5 and a capacitor C6, wherein the capacitor C5 and the capacitor C6 are connected in series between Vcc voltage and a grounding end, and an intermediate node between the capacitor C5 and the capacitor C6 is connected with an inverting end of the comparator U9.
The invention has the beneficial effects that:
the stable pulse width conversion circuit triggered by the pulse front edge disclosed by the invention converts an input random signal with a fluctuation pulse width through the stable pulse width conversion circuit and outputs a modulation signal with a fixed width, and the frequency of the modulation signal is consistent with the frequency of the random signal so as to meet the requirement of a radar system.
Drawings
Fig. 1 is a schematic diagram of a stabilized pulse width conversion circuit triggered by a pulse leading edge according to the present invention.
Detailed Description
In order to more clearly and completely describe the technical scheme of the invention, the invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, the present invention proposes a stable pulse width conversion circuit triggered by a pulse leading edge, through which an input random signal with a fluctuating pulse width is converted and then a modulation signal with a fixed width is output, and the frequency of the modulation signal is consistent with the frequency of the random signal;
the stable pulse width conversion circuit triggered by the pulse front comprises a resistor R2, a resistor R3, a resistor R5, a resistor R6, a resistor R12, a resistor R13, a capacitor C2, a capacitor C3 and a comparator U9; wherein,
the resistor R2 and the resistor R3 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the resistor R2 and the resistor R3 is connected with the same-phase terminal of the comparator U9;
the resistor R5 and the resistor R6 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the resistor R5 and the resistor R6 is connected with an inverting terminal of the comparator U9;
the capacitor C2 and the capacitor C3 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the capacitor C2 and the capacitor C3 is connected with an inverting terminal of the comparator U9;
the input signal G1 is connected to the non-inverting terminal of the comparator U9 through the resistor R12, and to the inverting terminal of the comparator U9 through the resistor R13.
Further, the stable pulse width conversion circuit triggered by the pulse front edge further comprises a resistor R17, and the resistor R17 is connected between the output modulation signal and the non-inverting terminal of the comparator U9 and used as positive feedback.
Further, the stable pulse width conversion circuit triggered by the pulse front edge further comprises a resistor R35, and the output modulation end is connected to the Vcc voltage through the resistor R35.
Further, the stable pulse width conversion circuit triggered by the pulse front edge further includes a filter capacitor C16, the filter capacitor C16 is connected between Vcc voltage and the ground terminal, and the positive electrode of the filter capacitor C16 is further connected to the non-inverting terminal of the comparator U9.
Further, the stable pulse width conversion circuit triggered by the pulse front edge further comprises a capacitor C5 and a capacitor C6, wherein the capacitor C5 and the capacitor C6 are connected in series between Vcc voltage and a grounding end, and an intermediate node between the capacitor C5 and the capacitor C6 is connected with an inverting end of the comparator U9.
In this embodiment, the 1 st pin of the comparator U9 is connected to output a modulation signal, the 3 rd pin and the 5 th pin are in-phase terminals, and the 4 th pin and the 2 nd pin are anti-phase terminals.
In the present embodiment, a random signal is input at G1, the pulse width of which is T1-T2, the frequency of which is f1, and the modulated signal obtained after conversion is the pulse width of T3, the frequency of which is f1; wherein the pulse width T3 is smaller than the width of T1-T2, and T3 is a fixed width.
In the present embodiment, the capacitors C2 and C3 are connected in series, and the intermediate voltage is connected to the inverting terminal of the comparator U9, so that the malfunction of the output modulation signal can be eliminated by equally dividing the voltage between the capacitor C2 and the capacitor C3 during the rising and falling of the Vcc voltage.
In the present embodiment, the resistor R17 is connected between the non-inverting terminal of the comparator U9 and the output modulation signal, and R17 is a positive feedback resistor, and prevents continuous oscillation of the output voltage when the output is inverted.
In this embodiment, the capacitors C5 and C6 and the capacitors C2 and C3 are connected in parallel, so as to correct the modulation pulse width value, and make the output pulse width more accurate.
Through the stable pulse width conversion circuit, an input random signal with a fluctuation pulse width is converted and then a modulation signal with a fixed width is output, and the frequency of the modulation signal is consistent with that of the random signal, namely different width pulses are converted into fixed width pulses, and the frequencies are the same, so that the requirements of a radar system are met.
Of course, the present invention can be implemented in various other embodiments, and based on this embodiment, those skilled in the art can obtain other embodiments without any inventive effort, which fall within the scope of the present invention.
Claims (1)
1. A stable pulse width conversion circuit triggered by a pulse front edge is characterized in that an input random signal with a fluctuation pulse width is converted by the stable pulse width conversion circuit and then a modulation signal with a fixed width is output, and the frequency of the modulation signal is consistent with that of the random signal;
the stable pulse width conversion circuit triggered by the pulse front comprises a resistor R2, a resistor R3, a resistor R5, a resistor R6, a resistor R12, a resistor R13, a resistor R17, a resistor R35, a capacitor C2, a capacitor C3, a capacitor C5, a capacitor C6, a filter capacitor C16 and a comparator U9; wherein,
the resistor R2 and the resistor R3 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the resistor R2 and the resistor R3 is connected with the same-phase terminal of the comparator U9;
the resistor R5 and the resistor R6 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the resistor R5 and the resistor R6 is connected with an inverting terminal of the comparator U9;
the capacitor C2 and the capacitor C3 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the capacitor C2 and the capacitor C3 is connected with an inverting terminal of the comparator U9;
the input signal G1 is connected with the non-inverting terminal of the comparator U9 through a resistor R12, and is connected with the inverting terminal of the comparator U9 through a resistor R13;
the resistor R17 is connected between the output modulation signal and the non-inverting terminal of the comparator U9;
the output modulation end is connected to Vcc voltage through a resistor R35;
the capacitor C5 and the capacitor C6 are connected in series between Vcc voltage and a ground terminal, and an intermediate node between the capacitor C5 and the capacitor C6 is connected with an inverting terminal of the comparator U9;
the filter capacitor C16 is connected between Vcc voltage and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911283692.4A CN111130506B (en) | 2019-12-13 | 2019-12-13 | Stable pulse width conversion circuit triggered by pulse leading edge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911283692.4A CN111130506B (en) | 2019-12-13 | 2019-12-13 | Stable pulse width conversion circuit triggered by pulse leading edge |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111130506A CN111130506A (en) | 2020-05-08 |
| CN111130506B true CN111130506B (en) | 2024-04-12 |
Family
ID=70498719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911283692.4A Active CN111130506B (en) | 2019-12-13 | 2019-12-13 | Stable pulse width conversion circuit triggered by pulse leading edge |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111130506B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1289165A (en) * | 2000-09-19 | 2001-03-28 | 乔建军 | Rectifying regulator |
| JP2004266780A (en) * | 2003-03-04 | 2004-09-24 | Fuji Electric Device Technology Co Ltd | Pulse width modulation circuit |
| CN201985825U (en) * | 2011-01-28 | 2011-09-21 | 北京康拓科技有限公司 | Pulse generation and pulse width protection circuit based on monostabillity |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4810775B2 (en) * | 2001-08-03 | 2011-11-09 | 日本テキサス・インスツルメンツ株式会社 | DC-DC converter |
-
2019
- 2019-12-13 CN CN201911283692.4A patent/CN111130506B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1289165A (en) * | 2000-09-19 | 2001-03-28 | 乔建军 | Rectifying regulator |
| JP2004266780A (en) * | 2003-03-04 | 2004-09-24 | Fuji Electric Device Technology Co Ltd | Pulse width modulation circuit |
| CN201985825U (en) * | 2011-01-28 | 2011-09-21 | 北京康拓科技有限公司 | Pulse generation and pulse width protection circuit based on monostabillity |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111130506A (en) | 2020-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10120064B2 (en) | Radar system and method with saturation detection and reset | |
| CN107678010B (en) | Multi-order Gao Tongrong resistance moment identification circuit of pulse laser radar | |
| CN117579173B (en) | Signal loss detection circuit and chip | |
| CN204964613U (en) | Zero -cross detection circuit | |
| CN111130506B (en) | Stable pulse width conversion circuit triggered by pulse leading edge | |
| CN103227624A (en) | Second-order differential gaussian pulse generator based on SRD | |
| CN106656050B (en) | S-band octave high-performance frequency synthesizer | |
| CN203278774U (en) | SRD-based second-order differential Gaussian pulse generator | |
| CN203630356U (en) | Frequency hopping type electronic countermeasure equipment | |
| Li et al. | An ultra-wideband monocycle pulse generator with good performance | |
| US9140778B2 (en) | Baseband amplifier unit and pulse radar device | |
| CN211296688U (en) | Single-path signal echo processing circuit | |
| CN110492871B (en) | Constant ratio timing circuit with timing back edge | |
| CN113777595A (en) | Ultrasonic receiving circuit | |
| CN205539148U (en) | Nonsinusoidal waveform's peak value and valley voltage detection circuit | |
| CN204145437U (en) | A kind of square-wave signal generation circuit | |
| CN207502715U (en) | The heterodyne detection of laser system of photoelectric detective circuit and single-ended signal link mode | |
| CN216751697U (en) | Pulse width locking circuit | |
| CN204967777U (en) | Square wave generator unit | |
| CN217444822U (en) | Laser Q-switching control circuit | |
| CN210444238U (en) | Picosecond pulse signal generating circuit | |
| US4117483A (en) | Noise-immune signal processing circuit for pulsed radars | |
| CN104122441A (en) | Frequency detection device | |
| CN210578436U (en) | Wide-temperature high-precision high-amplitude limiting module | |
| CN203675090U (en) | Non-communication long-distance analog quantity collector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |