CN111130506A - Stable pulse width conversion circuit triggered by pulse leading edge - Google Patents
Stable pulse width conversion circuit triggered by pulse leading edge Download PDFInfo
- Publication number
- CN111130506A CN111130506A CN201911283692.4A CN201911283692A CN111130506A CN 111130506 A CN111130506 A CN 111130506A CN 201911283692 A CN201911283692 A CN 201911283692A CN 111130506 A CN111130506 A CN 111130506A
- Authority
- CN
- China
- Prior art keywords
- resistor
- capacitor
- pulse width
- conversion circuit
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 29
- 230000001960 triggered effect Effects 0.000 title claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims description 48
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
- H03K2005/00208—Layout of the delay element using FET's using differential stages
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention provides a stable pulse width conversion circuit triggered by a pulse leading edge, which converts an input random signal with a fluctuating pulse width and outputs a modulation signal with a fixed width, wherein the frequency of the modulation signal is consistent with that of the random signal, so that the requirement of a radar system is met.
Description
Technical Field
The invention relates to the field of electronic power, in particular to a stable pulse width conversion circuit triggered by a pulse leading edge.
Background
With the continuous development of power electronic technology, the industrialization process is deepened continuously, the application fields of electronic devices are increased continuously, and the application environment is more complex and more severe. Such as high temperature, high humidity, low temperature, frost, etc., have higher requirements for the reliability and the anti-interference capability of the circuit. The invention is based on the characteristics of strong anti-interference capability, tracking prevention and strong concealment of the current radar system, requires that the transmitting frequency completely randomly appears in a certain range, requires that the frequency of a modulation signal completely follows the random transmitting frequency signal, and requires that the modulation widths are completely the same. It is therefore very difficult to obtain a modulated signal having the same frequency as the random signal and having different input pulse widths identical to the output pulse width. If the frequency synchronization and the pulse width are not completely consistent, the modulation frequency is disordered, the modulation pulse width determines the energy of the transmitter, and the complete radar system can be damaged due to the abnormity of the modulation pulse width.
Disclosure of Invention
In order to solve the above problems, the present invention provides a stable pulse width conversion circuit triggered by the leading edge of a pulse to output a modulation signal with a synchronous frequency and a fixed pulse width.
The invention is realized by the following technical scheme:
the invention provides a stable pulse width conversion circuit triggered by a pulse leading edge, which converts an input random signal with a fluctuating pulse width and outputs a modulation signal with a fixed width, wherein the frequency of the modulation signal is consistent with that of the random signal;
the stable pulse width conversion circuit triggered by the pulse leading edge comprises a resistor R2, a resistor R3, a resistor R5, a resistor R6, a resistor R12, a resistor R13, a capacitor C2, a capacitor C3 and a comparator U9; wherein,
the resistor R2 and the resistor R3 are connected in series between the Vcc voltage and the ground terminal, and the middle node between the resistor R2 and the resistor R3 is connected with the same-name terminal of the comparator U9;
the resistor R5 and the resistor R6 are connected in series between the Vcc voltage and the ground terminal, and the middle node between the resistor R5 and the resistor R6 is connected with the synonym terminal of the comparator U9;
the capacitor C2 and the capacitor C3 are connected in series between the Vcc voltage and the ground terminal, and the middle node between the capacitor C2 and the capacitor C3 is connected with the synonym terminal of the comparator U9;
the input signal G1 is connected to the dotted terminal of the comparator U9 via a resistor R12, and to the dotted terminal of the comparator U9 via a resistor R13.
Further, the stable pulse width conversion circuit triggered by the pulse leading edge further comprises a resistor R17, and a resistor R17 is connected between the output modulation signal and the same-name end of the comparator U9.
Further, the stable pulse width conversion circuit triggered by the pulse leading edge further comprises a resistor R35, and the output modulation terminal is connected to Vcc voltage through a resistor R35.
Furthermore, the stable pulse width conversion circuit triggered by the pulse leading edge further comprises a filter capacitor C16, and the filter capacitor C16 is connected between the Vcc voltage and the ground terminal.
Furthermore, the stable pulse width conversion circuit triggered by the pulse leading edge further comprises a capacitor C5 and a capacitor C6, the capacitor C5 and the capacitor C6 are connected between the Vcc voltage and the ground terminal in series, and an intermediate node between the capacitor C5 and the capacitor C6 is connected with the synonym terminal of the comparator U9.
The invention has the beneficial effects that:
the stable pulse width conversion circuit triggered by the pulse leading edge converts an input random signal with a fluctuating pulse width and outputs a modulation signal with a fixed width through the stable pulse width conversion circuit, and the frequency of the modulation signal is consistent with that of the random signal, so that the requirement of a radar system is met.
Drawings
Fig. 1 is a schematic diagram of a stable pulse width conversion circuit triggered by a pulse leading edge according to the present invention.
Detailed Description
In order to more clearly and completely explain the technical scheme of the invention, the invention is further explained with reference to the attached drawings.
Referring to fig. 1, the present invention provides a stable pulse width conversion circuit triggered by a pulse leading edge, which converts an input random signal with a fluctuating pulse width and outputs a modulation signal with a fixed width, wherein the frequency of the modulation signal is consistent with the frequency of the random signal;
the stable pulse width conversion circuit triggered by the pulse leading edge comprises a resistor R2, a resistor R3, a resistor R5, a resistor R6, a resistor R12, a resistor R13, a capacitor C2, a capacitor C3 and a comparator U9; wherein,
the resistor R2 and the resistor R3 are connected in series between the Vcc voltage and the ground terminal, and the middle node between the resistor R2 and the resistor R3 is connected with the same-name terminal of the comparator U9;
the resistor R5 and the resistor R6 are connected in series between the Vcc voltage and the ground terminal, and the middle node between the resistor R5 and the resistor R6 is connected with the synonym terminal of the comparator U9;
the capacitor C2 and the capacitor C3 are connected in series between the Vcc voltage and the ground terminal, and the middle node between the capacitor C2 and the capacitor C3 is connected with the synonym terminal of the comparator U9;
the input signal G1 is connected to the dotted terminal of the comparator U9 via a resistor R12, and to the dotted terminal of the comparator U9 via a resistor R13.
Further, the stable pulse width conversion circuit triggered by the pulse leading edge further comprises a resistor R17, and the resistor R17 is connected between the output modulation signal and the dotted terminal of the comparator U9 and used for positive feedback.
Further, the stable pulse width conversion circuit triggered by the pulse leading edge further comprises a resistor R35, and the output modulation terminal is connected to Vcc voltage through a resistor R35.
Furthermore, the stable pulse width conversion circuit triggered by the pulse leading edge further comprises a filter capacitor C16, the filter capacitor C16 is connected between the Vcc voltage and the ground terminal, and the anode of the filter capacitor C16 is also connected with the dotted terminal of the comparator U9.
Furthermore, the stable pulse width conversion circuit triggered by the pulse leading edge further comprises a capacitor C5 and a capacitor C6, the capacitor C5 and the capacitor C6 are connected between the Vcc voltage and the ground terminal in series, and an intermediate node between the capacitor C5 and the capacitor C6 is connected with the synonym terminal of the comparator U9.
In this embodiment, the 1 st pin of the comparator U9 is connected to output a modulation signal, the 3 rd pin and the 5 th pin are homonymous terminals, and the 4 th pin and the 2 nd pin are synonym terminals.
In this embodiment, a random signal with a pulse width of T1-T2 and a frequency of f1 is input at G1, and a modulated signal with a pulse width of T3 and a frequency of f1 is obtained after conversion; wherein the pulse width T3 is less than the width of T1-T2, and T3 is a fixed width.
In this embodiment, capacitors C2 and C3 are connected in series, the intermediate voltage point is connected to the different name end of the comparator U9, and the malfunction of the output modulation signal can be eliminated by sharing the voltage between the capacitor C2 and the capacitor C3 during the rising and falling of the Vcc voltage.
In this embodiment, the resistor R17 is connected between the end of the comparator U9 with the same name and the output modulation signal, and R17 is a positive feedback resistor, which prevents the output voltage from oscillating continuously when the output is inverted.
In this embodiment, the capacitors C5 and C6 and the capacitors C2 and C3 are connected in parallel to correct the modulation pulse width value, so that the output pulse width is more accurate.
Through the stable pulse width conversion circuit, an input random signal with a fluctuating pulse width is converted and then a modulation signal with a fixed width is output, the frequency of the modulation signal is consistent with that of the random signal, namely, different width pulses are converted into fixed width pulses, and the frequencies are the same, so that the requirements of a radar system are met.
Of course, the present invention may have other embodiments, and based on the embodiments, those skilled in the art can obtain other embodiments without any creative effort, and all of them are within the protection scope of the present invention.
Claims (5)
1. A stable pulse width conversion circuit triggered by a pulse leading edge is characterized in that an input random signal with a fluctuating pulse width is converted by the stable pulse width conversion circuit and then a modulation signal with a fixed width is output, and the frequency of the modulation signal is consistent with that of the random signal;
the stable pulse width conversion circuit triggered by the pulse leading edge comprises a resistor R2, a resistor R3, a resistor R5, a resistor R6, a resistor R12, a resistor R13, a capacitor C2, a capacitor C3 and a comparator U9; wherein,
the resistor R2 and the resistor R3 are connected in series between the Vcc voltage and the ground terminal, and the middle node between the resistor R2 and the resistor R3 is connected with the same-name terminal of the comparator U9;
the resistor R5 and the resistor R6 are connected in series between the Vcc voltage and the ground terminal, and the middle node between the resistor R5 and the resistor R6 is connected with the synonym terminal of the comparator U9;
the capacitor C2 and the capacitor C3 are connected in series between the Vcc voltage and the ground terminal, and the middle node between the capacitor C2 and the capacitor C3 is connected with the synonym terminal of the comparator U9;
the input signal G1 is connected to the dotted terminal of the comparator U9 via a resistor R12, and to the dotted terminal of the comparator U9 via a resistor R13.
2. The pulse-leading-edge-triggered stable pulse width conversion circuit as claimed in claim 1, further comprising a resistor R17, wherein the resistor R17 is connected between the output modulation signal and the dotted terminal of the comparator U9.
3. The pulse-edge-triggered stable pulse width conversion circuit as claimed in claim 1, further comprising a resistor R35, wherein the output modulation terminal is connected to Vcc voltage through a resistor R35.
4. The pulse-edge-triggered stable pulse width conversion circuit as claimed in claim 1, further comprising a filter capacitor C16, wherein the filter capacitor C16 is connected between Vcc voltage and ground.
5. The pulse-edge-triggered stable pulse width conversion circuit as claimed in claim 1, further comprising a capacitor C5 and a capacitor C6, wherein the capacitor C5 and the capacitor C6 are connected in series between Vcc voltage and ground, and an intermediate node between the capacitor C5 and the capacitor C6 is connected to the synonym terminal of the comparator U9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911283692.4A CN111130506B (en) | 2019-12-13 | 2019-12-13 | Stable pulse width conversion circuit triggered by pulse leading edge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911283692.4A CN111130506B (en) | 2019-12-13 | 2019-12-13 | Stable pulse width conversion circuit triggered by pulse leading edge |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111130506A true CN111130506A (en) | 2020-05-08 |
| CN111130506B CN111130506B (en) | 2024-04-12 |
Family
ID=70498719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911283692.4A Active CN111130506B (en) | 2019-12-13 | 2019-12-13 | Stable pulse width conversion circuit triggered by pulse leading edge |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111130506B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1289165A (en) * | 2000-09-19 | 2001-03-28 | 乔建军 | Rectifying regulator |
| US20030034762A1 (en) * | 2001-08-03 | 2003-02-20 | Tetsuo Tateishi | DC-DC converter |
| JP2004266780A (en) * | 2003-03-04 | 2004-09-24 | Fuji Electric Device Technology Co Ltd | Pulse width modulation circuit |
| CN201985825U (en) * | 2011-01-28 | 2011-09-21 | 北京康拓科技有限公司 | Pulse generation and pulse width protection circuit based on monostabillity |
-
2019
- 2019-12-13 CN CN201911283692.4A patent/CN111130506B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1289165A (en) * | 2000-09-19 | 2001-03-28 | 乔建军 | Rectifying regulator |
| US20030034762A1 (en) * | 2001-08-03 | 2003-02-20 | Tetsuo Tateishi | DC-DC converter |
| JP2004266780A (en) * | 2003-03-04 | 2004-09-24 | Fuji Electric Device Technology Co Ltd | Pulse width modulation circuit |
| CN201985825U (en) * | 2011-01-28 | 2011-09-21 | 北京康拓科技有限公司 | Pulse generation and pulse width protection circuit based on monostabillity |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111130506B (en) | 2024-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10120064B2 (en) | Radar system and method with saturation detection and reset | |
| CN103731123B (en) | A kind of ultra-wideband impulse signal generation device based on memristor | |
| CN206041199U (en) | High peak power semiconductor laser drive circuit of small -size narrow pulse width | |
| CN204964613U (en) | Zero -cross detection circuit | |
| KR100979155B1 (en) | Impulse generator utilizing nonlinear transmission line | |
| CN111130506B (en) | Stable pulse width conversion circuit triggered by pulse leading edge | |
| CN113659534B (en) | Overstress frequency protection circuit and method for traveling wave tube modulator | |
| CN203278774U (en) | SRD-based second-order differential Gaussian pulse generator | |
| CN203630356U (en) | Frequency hopping type electronic countermeasure equipment | |
| Li et al. | An ultra-wideband monocycle pulse generator with good performance | |
| CN207502976U (en) | A kind of laser warning control system | |
| CN204886901U (en) | Narrow pulse generating circuit based on tunnel diode | |
| Gumber et al. | Nonlinear negative resistance-based harmonic backscatter | |
| US9140778B2 (en) | Baseband amplifier unit and pulse radar device | |
| CN103762984A (en) | Non-communication type remote analog acquisition device | |
| CN107037865B (en) | Reset circuit and floating terminal | |
| CN207502715U (en) | The heterodyne detection of laser system of photoelectric detective circuit and single-ended signal link mode | |
| CN205539148U (en) | Nonsinusoidal waveform's peak value and valley voltage detection circuit | |
| CN103151995B (en) | Digital tri-state class-D amplifier | |
| CN115955235B (en) | Anti-interference output circuit of gyroscope | |
| CN110907718A (en) | Electromagnetic compatibility radiation disturbance standard sample for lighting product | |
| CN217932041U (en) | Frequency synthesizer module for radar radiation simulation | |
| CN210112005U (en) | Boosting module of optical power detection circuit | |
| CN217444822U (en) | Laser Q-switching control circuit | |
| CN110752826B (en) | External RC frequency adjustable oscillator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |