CN111128768A - 制造重布线路结构的方法 - Google Patents
制造重布线路结构的方法 Download PDFInfo
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- CN111128768A CN111128768A CN201911043962.4A CN201911043962A CN111128768A CN 111128768 A CN111128768 A CN 111128768A CN 201911043962 A CN201911043962 A CN 201911043962A CN 111128768 A CN111128768 A CN 111128768A
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Abstract
本发明实施例公开制造重布线路结构的方法,且所述方法中的一种包括以下步骤。在管芯及包封所述管芯的包封体之上形成晶种层。在所述晶种层之上形成光刻胶材料。使用等于或小于0.18的数值孔径,通过相移掩模将所述光刻胶材料曝光于I线步进光刻机内的I线波长。将所述光刻胶材料显影以形成光刻胶层,所述光刻胶层包括光刻胶图案及所述光刻胶图案之间的开口。在所述开口中形成导电材料。移除所述光刻胶图案,以形成导电图案。通过使用所述导电图案作为掩模,局部地移除所述晶种层,以在所述导电图案下方形成晶种层图案,其中重布线导电图案分别包括所述晶种层图案及所述导电图案。
Description
技术领域
本发明实施例涉及制造重布线路结构的方法。
背景技术
由于各种电子组件(即,晶体管、二极管、电阻器、电容器等)的集成密度的持续提高,半导体行业已经历快速增长。在很大程度上,集成密度的此种提高来自于最小特征尺寸(minimum feature size)的反复减小,此使得更多较小的组件能够集成到给定区域中。这些较小的电子组件也需要与先前的封装件相比利用较小面积的较小的封装件。半导体组件的一些较小类型的封装件包括方形扁平封装件(quad flat package,QFP)、引脚栅阵列(pin grid array,PGA)封装件、球栅阵列(ball grid array,BGA)封装件等等。
当前,集成扇出型封装件因其紧凑性而正变得日渐流行。集成扇出型封装件通常包括位于模制集成电路装置之上的重布线路结构,以便可通达集成电路装置。为了满足对更小尺寸及更高封装密度的要求,重布线路结构的制造方法已经成为此领域中的重要问题。
发明内容
本发明实施例的一种制造重布线路结构的方法包括以下步骤。在管芯及包封所述管芯的包封体之上形成晶种层。在所述晶种层之上形成第一光刻胶材料。使用等于或小于0.18的数值孔径,通过相移掩模将所述第一光刻胶材料曝光于I线步进光刻机内的I线波长。将所述第一光刻胶材料显影以形成第一光刻胶层,其中所述第一光刻胶层包括多个第一光刻胶图案及所述多个第一光刻胶图案之间的多个第一开口。在所述多个第一开口中形成第一导电材料。移除所述第一光刻胶层,以形成多个第一导电图案。使用所述多个第一导电图案作为掩模,局部地移除所述晶种层,以在所述多个第一导电图案下方形成多个晶种层图案,其中多个重布线导电图案分别包括所述多个晶种层图案及所述多个第一导电图案。
附图说明
结合附图阅读以下详细说明,会最好地理解本发明的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为使论述清晰起见,可任意增大或减小各种特征的关键尺寸。
图1A至图1H是示出根据本发明一些实施例的封装件的制造工艺的示意性剖视图。
图2A至图2F是示出根据本发明一些实施例的重布线路结构的制造工艺的剖视图。
图3A至图3F是示出根据本发明一些实施例的重布线路结构的制造工艺的剖视图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。以下阐述组件及排列的具体实例以简化本发明。当然,这些仅为实例且不旨在进行限制。举例来说,以下说明中将第二特征形成在第一特征之上或第一特征上可包括其中第二特征与第一特征被形成为直接接触的实施例,且也可包括其中第二特征与第一特征之间可形成有附加特征从而使得所述第二特征与所述第一特征可不直接接触的实施例。另外,本发明可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的,而不是自身指示所论述的各种实施例及/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“在…之下(beneath)”、“在…下方(below)”、“下部的(lower)”、“在…上(on)”、“在…之上(over)”、“上覆在…上(overlying)”、“在…上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向),且本文中所使用的空间相对性描述语可同样相应地进行解释。
当前公开内容中所述的先进光刻工艺、方法及材料可用于许多应用,包括鳍型场效晶体管(fin-type field effect transistor,FinFET)。例如,可将鳍图案化以在特征之间产生相对紧密的间隔,这是上述公开内容非常适合的。另外,可根据上述公开内容来处理在形成FinFET的鳍时所使用的间隔物。
图1A至图1H是示出根据本发明一些实施例的封装件的制造工艺的示意性剖视图。参照图1A,提供载体C。在载体C之上以循序次序堆叠剥离层DB及介电层DI。在一些实施例中,剥离层DB形成在载体C的上表面上,且剥离层DB在载体C与介电层DI之间。载体C例如是玻璃衬底。另一方面,在一些实施例中,剥离层DB是形成在玻璃衬底上的光/热转换(light-to-heat conversion,LTHC)释放层。在一些实施例中,介电层DI例如是聚合物,例如聚酰亚胺、苯环丁烷(benzocyclobutene,BCB)、聚苯并恶唑(polybenzoxazole,PBO)等。在一些替代实施例中,介电层DI可包含非有机介电材料,例如氧化硅、氮化硅、碳化硅、氮氧化硅等。然而,剥离层DB、载体C及介电层DI的材料仅用于说明,且本发明并非仅限于此。
在介电层DI上设置多个导电柱102及多个管芯104。管芯104被安装到上面形成有导电柱102的介电层DI上。在一些实施例中,管芯贴合膜(die attach film,DAF)(图中未示出)位于管芯104与介电层DI之间,用于将管芯104贴合到介电层DI上。管芯104排列成阵列,且被导电柱102环绕。管芯104例如是半导体管芯。管芯104中的每一者包括有源表面104a、分布在有源表面104a上的多个接垫104b、覆盖有源表面104a的钝化层104c、多个导电柱104d及保护层104e。接垫104b由钝化层104c局部地暴露出。导电柱104d设置在接垫104b上并电连接到接垫104b,且保护层104e覆盖导电柱104d及钝化层104c。例如,导电柱104d是铜柱或其他适合的金属柱。在一些实施例中,保护层104e可为聚苯并恶唑(PBO)层、聚酰亚胺(polyimide,PI)层或其他适合的聚合物。在一些替代实施例中,保护层104e可由无机材料制成。如图1A中所示,管芯104的顶表面低于导电柱102的顶表面。然而,本发明并非仅限于此。在一些替代实施例中,管芯104的顶表面可与导电柱102的顶表面实质上共面或高于导电柱102的顶表面。
参照图1B,在介电层DI上形成绝缘材料106,以包封导电柱102及管芯104。在一些实施例中,绝缘材料106是通过模制工艺形成的模制化合物。导电柱102及管芯104的保护层104e由绝缘材料106包封。换句话说,导电柱102及管芯104的保护层104e未展露出,且由绝缘材料106充分地保护。在一些实施例中,绝缘材料106可包括环氧树脂或其他适合的材料。
参照图1C,研磨绝缘材料106及管芯104的保护层104e,直到导电柱104d的顶表面暴露出为止。在研磨绝缘材料106之后,在介电层DI之上形成包封体106’。在前述研磨工艺期间,保护层104e的部分也被研磨以形成保护层104e’。在一些实施例中,在绝缘材料106及保护层104e的前述研磨工艺期间,研磨导电柱104d的部分及导电柱102的部分,直到导电柱104d的顶表面及导电柱102的顶表面暴露出为止。换句话说,包封体106’暴露出管芯104的至少一部分及导电柱102的至少一部分。在一些实施例中,可通过机械研磨、化学机械抛光(chemical mechanical polishing,CMP)或另一种适合的机制形成包封体106’。
包封体106’包封管芯104的侧壁,且包封体106’被导电柱102穿透。换句话说,管芯104及导电柱102嵌置在包封体106’中。应注意,尽管管芯104及导电柱102嵌置在包封体106’中,但包封体106’暴露出管芯104的及导电柱102的顶表面。换句话说,导电柱102的顶表面、保护层104e’的顶表面及导电柱104d的顶表面与包封体106’的顶表面实质上共面。
在一些实施例中,在形成包封体106’以包封管芯104之后,例如,由于管芯104与包封体106’之间的热膨胀系数(Coefficient of Thermal Expansion,CTE)及刚度差异,整个封装件可能发生全局(global)翘曲。全局翘曲可跨整个封装件的顶表面而引起可介于10μm至20μm范围内的高度变化(差异)。在一些实施例中,单独的管芯104可发生局部翘曲,且这跨单独的管芯104的顶表面而引起高度变化(差异)。然而,在一些实施例中,在上述研磨工艺之后,由于局部翘曲所致的高度变化可介于3μm至5μm的范围内,这可忽略不计。
参照图1D,在形成包封体106’及保护层104e’之后,在导电柱102的顶表面、包封体106’的顶表面、导电柱104d的顶表面及保护层104e’的顶表面上形成介电层108。在一些实施例中,介电层108例如是聚合物,例如聚酰亚胺、苯环丁烷(BCB)、聚苯并恶唑(PBO)等。在一些替代实施例中,介电层108可包含非有机介电材料,例如氧化硅、氮化硅、碳化硅、氮氧化硅等。然后,在介电层108中形成多个通孔110,其中通孔110中的每一者电连接到管芯104的导电柱104d中的一者或导电柱102中的一者。在一些实施例中,在介电层108中形成多个开口(图中未示出),且然后分别在所述开口中形成通孔110。在一些实施例中,导电柱104d的顶表面及导电柱102的顶表面与通孔110接触。在一些实施例中,例如,通孔110是铜通孔或其他适合的金属通孔。在一些实施例中,例如,通孔110可包括晶种层及所述晶种层上的导电层。
参照图1E,在介电层108的顶表面上形成电连接到通孔110的重布线路结构112。如图1E中所示,重布线路结构112包括交替堆叠的多个重布线导电图案112a及多个层间介电层112b。在一些实施例中,重布线导电图案112a电连接到嵌置在介电层108中的通孔110,其中通孔110的顶表面与重布线路结构112的最底部的重布线导电图案112a接触。此外,最顶部的重布线导电图案112a包括多个接垫。在一些实施例中,前述接垫包括用于球安装的多个球下金属(under-ball metallurgy,UBM)图案112a1及/或用于无源组件安装的至少一个连接接垫112a2。球下金属图案112a1及连接接垫112a2的数目在本发明中不受限制。
以下将详细阐述重布线路结构112的形成。图2A至图2F是示出根据本发明一些实施例图1E中所绘示的重布线路结构112的制造工艺的剖视图。应注意,图2A至图2F中所绘示的图示仅用作示范实例。因此,图2A至图2F中所示的比例、尺寸及形状可能不完全反映图1D中所示的重布线路结构112。然而,相同的元件由相同的参考编号表示,以建立图2A至图2F与图1E之间的相关性。
当前,为了覆盖例如集成扇出型(integrated fan-out,INFO)封装件或INFO超高密度(ultra-high density,UHD)封装件等封装件的高形貌及高翘曲特性,应用I线(I-line)以及0.18或更小的低数值孔径(numerical aperture,NA)来获得较宽的焦深(depthof focus,DOF)。然而,低NA引起低图像对比度,且间距分辨率(也称为“最小间距(minimalpitch)”)相应地受到限制,也就是说,间距大于2μm。换句话说,通过使用I线及低NA,难以获得具有亚微米尺度(例如1μm或更小)的临界尺寸的导电线。详细来说,“间距”是线宽度与间隔宽度之和,且“最小间距(也称为间距分辨率)”是可由具有预定波长λ及数值孔径NA的投影光学曝光设备分辨的间距。已知,间距分辨率由瑞利公式(Rayleigh formula)确定:R=k1(λ/NA),其中R是图案的分辨率,NA是数值孔径,λ是用於曝光的光的波长,且k1是常数。焦深(DOF)被定义为DOF=k2(λ/(NA)2),其中k2是常数,NA是数值孔径,且λ是用於曝光的光的波长。如前所述,高DOF是通过使用I线及低NA而获得,然而,这会不利地影响间距分辨率。在一些实施例中,为了减小间距而不改变I线及低NA的曝光条件,采用相移掩模或者调整瑞利公式中的常数k1以提高间距分辨率。换句话说,在保持宽DOF的同时提高图像对比度及光学分辨率。因此,在I线及低NA的曝光条件下,图案的临界尺寸可减小至亚微米尺度。换句话说,光学分辨率得以提高,且超过当前I线曝光工具的能力。
参照图2A,提供衬底SUB。衬底SUB具有第一区R1及第二区R2。在一些实施例中,衬底SUB可如图1D中所示包括载体C、剥离层DB、介电层DI、导电柱102、管芯104、包封体106’、介电层108及通孔110。然而,本发明并非仅限于此。随后,在衬底SUB之上形成晶种层210。在一些实施例中,晶种层210形成在通孔110的及介电层108的顶表面之上。在一些实施例中,晶种层210与通孔110的及介电层108的顶表面接触。在一些实施例中,晶种层210的材料可例如包括铜、铜合金或其他适合的材料选择。在一些实施例中,通过溅镀方法、沉积方法(例如物理气相沉积)或其他适用的方法来形成晶种层210。在一些实施例中,例如,晶种层210可具有大约0.01μm至大约1μm的厚度。
在一些实施例中,可在晶种层210之上形成光刻胶材料220,且对应于光刻胶材料220并在光刻胶材料220之上设置相移掩模PSM。在一些实施例中,光刻胶材料220是正性光刻胶。在替代实施例中,例如,光刻胶材料220可为负性光刻胶。在一些实施例中,提供I线步进光刻机(图中未示出,也称为I线扫描仪)。I线步进光刻机是一种I线型光刻光学系统,其使用曝光波长为365nm的紫外光(ultraviolet light,UV)。例如,光学光刻系统可包括光源、光、聚光透镜、光掩模、掩模载台、投影透镜及封装件载台。然而,可存在对系统的其他配置及包含或省略。光源包括提供单一波长为365nm的光的辐射源。例如,可利用汞灯,其可操作以提供I线(例如,365nm)波长。在一些实施例中,将图2A所示封装件设置在封装件载台上。在一些实施例中,例如,光掩模是相移掩模PSM。例如,相移掩模PSM可为交替孔径相移掩模(alternating aperture phase shift mask,alt-PSM)、衰减PSM(attenuating PSM,att-PSM)或其他适合的相移掩模。在一些实施例中,相移掩模PSM包括多个图案MP及图案MP之间的多个开口OP。图案MP可被设计成形成重布线导电图案112a,例如通孔、导电线或其他可能的导电图案。在一些实施例中,相移掩模PSM包括被设计成形成重布线导电图案112a(例如通孔、导电线或其他可能的导电图案)的多个图案(图中未示出)。
参照图2B,执行曝光步骤,也就是说,使用曝光条件通过相移掩模PSM将光刻胶材料220曝光于I线步进光刻机内的I线波长。然后,将光刻胶材料220显影以形成光刻胶层220’,从而将相移掩模PSM的图案MP转移到光刻胶层220’上。在一些实施例中,光刻胶层220’包括多个光刻胶图案222a、222b及光刻胶图案222a、222b之间的多个开口224a、224b。在一些实施例中,曝光条件是,在瑞利公式中,λ是I线的波长(例如,365nm),NA等于或小于0.18,且常数k1是等于或小于0.49的正常数(positive constant)。在一些实施例中,通过使用曝光条件,与区R1对应的光刻胶层220’的间距P可等于或小于2μm。间距P(也称为最小间距)是光刻胶图案222a的宽度W1(即,线宽度)与开口224a的宽度W2(即,间隔宽度)之和。在一些实施例中,例如,当常数k1是等于或小于0.39的正常数时,间距P是1.6μm。在一些实施例中,例如,光刻胶图案222a的宽度可为0.5μm,且开口224a的宽度可为1.1μm。在一些替代实施例中,间距可等于或小于1.4μm。例如,当常数k1是等于或小于0.35的正常数时,间距可为1.4μm。在一些实施例中,根据要求,与其他区(例如其中设置有光刻胶图案222b的区R2)对应的光刻胶层220’的间距可大于2μm。在一些实施例中,例如,开口224a、224b是对应于通孔110而设置,且可设置在通孔110正上方。
参照图2C,将导电材料230局部地填充到光刻胶层220’的开口224a、224b中。在一些实施例中,例如,导电材料230的顶表面低于光刻胶层220’的顶表面。然而,在一些替代实施例中,导电材料230的顶表面可与光刻胶层220’的顶表面实质上共面。在一些实施例中,可通过镀覆工艺形成导电材料230。镀覆工艺例如是电镀、无电镀覆、浸渍镀覆等。导电材料230例如是铜、铜合金等。在一些实施例中,晶种层210及导电材料230包含相同的材料。例如,晶种层210及导电材料230由相同的材料制成。
参照图2D,随后移除光刻胶层220’以呈现多个导电图案232a、232b,且暴露出晶种层210的部分。因为导电图案232a、232b源自开口224a、224b,所以导电图案232a、232b也具有相同的配置。也就是说,间距P(也称为最小间距)是导电图案232a的线宽度W2与导电图案232a之间的间隔宽度W1之和。间距P可等于或小于2μm。在一些实施例中,例如,通过剥除工艺移除光刻胶层220’。晶种层210的部分被导电图案232a、232b覆盖,且晶种层210的在导电图案232a、232b之间的部分暴露出。在一些实施例中,例如,导电图案232a、232b可为导电线。
如图2D及图2E中所示,在一些实施例中,可在导电图案232a、232b上方形成附加图案。例如,可在第二区R2中形成附加导电图案252。参照图2D,在形成导电图案232a、232b之后,在晶种层210及导电图案232a、232b之上形成光刻胶层240,以进行附加图案化。在一些实施例中,例如,光刻胶层240具有开口242以暴露出导电图案232b。在一些实施例中,例如,开口242的宽度小于导电图案232b的线宽度。然后,将导电材料250局部地填充到光刻胶层240的开口242中。在一些实施例中,例如,导电材料250的顶表面低于光刻胶层240的顶表面。在一些实施例中,可通过镀覆工艺形成导电材料250。镀覆工艺例如是电镀、无电镀覆、浸渍镀覆等。导电材料250例如是铜、铜合金等。
参照图2E,然后,随后移除光刻胶层240,以在第二区R2中呈现导电图案252。在一些实施例中,例如,导电图案252可为通孔。在一些实施例中,例如,通过剥除工艺移除光刻胶层240。在一些实施例中,例如,导电图案252的宽度可与导电图案232a的宽度实质上相同。在一些替代实施例中,可省略导电图案252的形成。
参照图2F,此后,通过使用导电图案232a、232b作为掩模层,局部地移除晶种层210,以分别在导电图案232a、232b下方形成多个晶种层图案210a、210b。详细来说,例如,通过湿式蚀刻或干式蚀刻选择性地移除晶种层210的由导电图案232a、232b暴露出的部分。应注意,不可避免地,导电图案232a、232b、252的材料可在晶种层210的蚀刻工艺期间被局部地移除。具体来说,导电图案232a、232b、252的宽度及/或高度可减小,从而得到多个剩余的导电图案232a’、232b’、252’。在一些实施例中,剩余的导电图案232a’具有小于线宽度W2的蚀刻后线宽度W2’,导电图案232a’之间的间隔宽度W1’大于间隔宽度W1,且间距P是(W1’+W2’),其等于(W1+W2)。换句话说,间距P在晶种层210的蚀刻工艺前后保持实质上相同,如图2E至图2F中所示。在一些实施例中,通过控制与区R1对应的光刻胶层220’的线宽度及间隔宽度以及晶种层210的蚀刻工艺条件,可获得导电图案232a’的所期望线宽度。例如,线宽度W2’及间隔宽度W1’可分别等于间距P的一半。在间距P为1.6μm的实施例中,线宽度W2’及间隔宽度W1’可分别为0.8μm。换句话说,临界尺寸为亚微米尺度。
如图2F中所示,导电图案232a’、232b’的侧壁与晶种层图案210a的侧壁实质上齐平。通过前述蚀刻工艺,导电图案232a’、232b’的侧壁与晶种层图案210a的侧壁实质上对齐。导电图案232a’、232b’及其之下的晶种层图案210a构成可用作导电线或通孔的导电结构234A、234B。导电图案252’可用作通孔。在一些实施例中,可形成介电层236以覆盖导电结构234A、234B及导电图案252’,且例如,介电层236可用作层间介电层112b中的一者。在一些实施例中,通过利用相移掩模PSM调整常数k1或利用其他手段调整常数k1,导电结构234A的临界尺寸可减小至亚微米尺度。
在一些实施例中,重布线路结构112是多层式结构(例如,图1E中所示的重布线路结构112)。在此种情况下,图2A至图2F中所示的步骤可重复几次,以呈现重布线路结构112。在一些实施例中,重布线路结构112包括具有导电结构234A的至少一个重布线图案112a,且其他重布线图案112a可具有导电结构234A、234B及导电图案252’或其他适合的结构中的任何一者。
应注意,图2A至图2F中所示的步骤并非仅限于制作图1E中所绘示的重布线路结构112。前述步骤可用于位于封装件中其他位置处的重布线路结构。在一些实施例中,靠近管芯104的下重布线导电图案112a的宽度可小于靠近导电端子114(图1F中示出)的上部重布线导电图案112a的宽度,因为导电柱104d的尺寸比导电端子114的尺寸小得多。因此,在一些实施例中,可应用前述光刻来形成下部重布线导电图案112a。在一些实施例中,例如,具有导电结构234A的重布线导电图案112a可与通孔110接触。在一些替代实施例中,例如,可通过应用前述光刻来形成通孔110。
返回参照图1F,在形成重布线路结构112之后,在球下金属图案112a1上放置多个导电端子114,且在连接接垫112a2上安装多个无源组件116。在一些实施例中,可通过植球工艺或其他适合的工艺在球下金属图案112a1上放置导电端子1 14,且可通过焊接工艺、回焊工艺或其他适合的工艺在连接接垫112a2上安装无源组件116。
参照图1G,在导电端子114及无源组件116被安装在重布线路结构112上之后,将在包封体106’的底表面上形成的介电层DI从剥离层DB剥离,使得介电层DI与载体C分离。也就是说,载体C被移除。在一些实施例中,可通过UV激光辐照剥离层DB(例如,LTHC释放层),使得粘附在包封体106’的底表面上的介电层DI从载体C剥落。如图1F中所示,然后将介电层DI图案化,以便形成多个接触开口O以局部地暴露出导电柱102。接触开口O的数目对应于导电柱102的数目。在一些实施例中,通过激光钻孔工艺、机械钻孔工艺或其他适合的工艺形成介电层DI的接触开口O。
参照图1H,在介电层DI中形成接触开口O之后,在接触开口O中放置多个导电端子118,且导电端子118电连接到导电柱102。本文中,集成扇出型(INFO)封装阵列的形成实质上完成。如图1H中所示,在形成导电端子114及导电端子118之后,切分INFO封装阵列以形成具有双侧端子设计的多个INFO封装件10。在一些实施例中,切分工艺或单体化工艺通常涉及利用旋转刀片或激光束进行切分。换句话说,切分或单体化工艺例如是激光切割工艺、机械切割工艺或其他适合的工艺。在一些替代实施例中,INFO封装件10可与其他电子装置(例如另一INFO封装件、存储器装置、球栅阵列(BGA)或晶片)堆叠在一起。例如,可通过导电端子118将另一封装件(例如IC封装件)堆叠在INFO封装件10之上并电连接到INFO封装件10,以便制作层叠式封装(package-on-package,POP)结构。
图3A至图3F是示出根据本发明一些实施例图1E中所绘示的重布线路结构112的制造工艺的剖视图。应注意,图3A至图3F中所绘示的图示仅用作示范实例。因此,图3A至图3F中所示的比例、尺寸及形状可能不完全反映图1E中所示的重布线路结构。然而,相同的元件由相同的参考编号表示,以建立图3A至图3F与图1E之间的相关性。
参照图3A,提供衬底SUB,且在衬底SUB之上形成晶种层210。然后,可在晶种层210之上形成光刻胶材料220。衬底SUB、晶种层210及光刻胶材料220的结构及材料类似于图2A及2B中所绘示的那些,且因此本文中省略了细节。
在一些实施例中,为了形成亚微米尺度的间距,采用双重曝光方法。双重曝光方法由使用两个不同的光掩模在同一光刻胶层上进行两次依序分开的曝光组成。双重曝光可两次以两倍放大的线间隔比(line-to-space)界定最小尺寸特征,且因此提高光刻分辨率。
此后,在光刻胶材料220之上设置第一掩模M1。然后,执行第一曝光步骤,也就是说,通过第一掩模M1将第一区220a中的光刻胶材料220曝光于I线步进光刻机内的I线波长。在一些实施例中,NA等于或小于0.18。在一些实施例中,第一掩模M1具有多个图案MP1及图案MP1之间的多个开口OP1,且开口OP1是对应于第一区220a而设置。在一些实施例中,例如,图案MP1的宽度与开口OP1的宽度之比实质上为3:1。
参照图3B,在光刻胶材料220之上设置第二掩模M2。然后,执行第二曝光步骤,也就是说,通过第二掩模M2将第二区220b中的光刻胶材料220曝光于I线步进光刻机内的I线波长。在一些实施例中,NA等于或小于0.18。在一些实施例中,第二掩模M2具有多个图案MP2及图案MP2之间的多个开口OP2,且开口OP2是对应于第二区220b而设置。在一些实施例中,例如,图案MP2的宽度与开口OP2的宽度之比实质上为3:1。在一些实施例中,第二掩模M2的间距等于第一掩模M1的间距。在一些实施例中,第一区220a及第二区220b交替设置。
参照图3C,将光刻胶材料220显影以形成光刻胶层220’,从而将第一掩模M1的图案MP1及第二掩模M2的图案MP2转移到光刻胶层220’上。在一些实施例中,光刻胶层220’包括多个光刻胶图案222及光刻胶图案222之间在区220a、220b中的多个开口224。例如,开口224对应于开口OP1、OP2。在一些实施例中,通过使用双重曝光,光刻胶层220’的间距P可等于或小于2μm。间距P是光刻胶图案222的宽度W1(即,线宽度)与开口224的宽度W2(即,间隔宽度)之和。在一些实施例中,例如,光刻胶图案222的宽度W1可实质上等于开口224的宽度W2。
参照图3D,将导电材料230局部地填充到光刻胶层220’的开口224中。在一些实施例中,例如,导电材料230的顶表面低于光刻胶层220’的顶表面。然而,在一些替代实施例中,导电材料230的顶表面可与光刻胶层220’的顶表面实质上共面。在一些实施例中,可通过镀覆工艺形成导电材料230。镀覆工艺例如是电镀、无电镀覆、浸渍镀覆等。导电材料230例如是铜、铜合金等。在一些实施例中,晶种层210及导电材料230包含相同的材料。例如,晶种层210及导电材料230由相同的材料制成。
参照图3E,随后移除光刻胶层220’以呈现多个导电图案232,且暴露出晶种层210的部分。因为导电图案232源自开口224,所以导电图案232也具有相同的配置。在一些实施例中,例如,通过剥除工艺移除光刻胶层220’。在一些实施例中,间距P是导电图案232的线宽度W2与导电图案232之间的间隔宽度W1之和。
参照图3F,此后,通过使用导电图案232作为掩模,局部地移除晶种层210,以分别在导电图案232下方形成多个晶种层图案210a。详细来说,例如,通过湿式蚀刻或干式蚀刻选择性地移除晶种层210的由导电图案232暴露出的部分。应注意,不可避免地,导电图案232的材料可在晶种层210的蚀刻工艺期间被局部地移除。具体来说,导电图案232的宽度W2及/或高度可减小,从而得到多个导电图案232’。导电图案232’及其之下的晶种层图案210a构成可用作导电线或通孔的导电结构234。在一些实施例中,导电图案232’具有小于线宽度W2的蚀刻后线宽度W2’,导电图案232’之间的间隔宽度W1’大于间隔宽度W1,且间距P是(W1’+W2’),其等于(W1+W2)。换句话说,间距P在晶种层210的蚀刻工艺前后是恒定的。在一些实施例中,例如,间距P等于或小于2μm。在一些实施例中,例如,间距P等于或小于1.4μm。在一些实施例中,线宽度及间隔宽度可等于间距P的一半,且例如,可为0.7μm。在一些实施例中,通过双重曝光及间距分裂(pitch splitting),重布线导电图案的临界尺寸可扩展成亚微米尺度,这超过了当前I线曝光工具的能力。因此,实现了精细间距。
在一些实施例中,重布线路结构112是多层式结构(例如,图1E中所示的重布线路结构112)。在此种情况下,图3A至图3F中所示的步骤可重复几次,以呈现重布线路结构112。在一些实施例中,重布线路结构112包括具有导电结构234的至少一个重布线图案112a,且其他重布线图案112a可具有其他适合的结构。
传统上,由于例如INFO封装件或INFO UHD封装件等的封装件具有高形貌(topography)及高翘曲特性,所以需要具有I线及0.18或更小的低NA的曝光工具来获得较宽的DOF,这引起低图像对比度且限制间距分辨率。在一些实施例中,通过使用相移掩模、调整瑞利公式中的常数k1或使用双重曝光,在利用I线及低NA保持宽DOF的同时,图像对比度及光学分辨率得以提高。因此,光刻性能及工艺窗口显著提高,且获得大的DOF及高的分辨率。换句话说,光学分辨率得以提高,且超过当前I线曝光工具的能力。因此,重布线导电图案的临界尺寸可扩展成亚微米尺度。另外,前述光刻可应用于需要通过I线曝光工具利用I线及低NA形成的其他元件。
根据本发明的一些实施例,一种制造重布线路结构的方法包括以下步骤。在管芯及包封所述管芯的包封体之上形成晶种层。在所述晶种层之上形成第一光刻胶材料。使用等于或小于0.18的数值孔径,通过相移掩模将所述第一光刻胶材料曝光于I线步进光刻机内的I线波长。将所述第一光刻胶材料显影以形成第一光刻胶层,其中所述第一光刻胶层包括多个第一光刻胶图案及所述多个第一光刻胶图案之间的多个第一开口。在所述多个第一开口中形成第一导电材料。移除所述第一光刻胶层,以形成多个第一导电图案。使用所述多个第一导电图案作为掩模,局部地移除所述晶种层,以在所述多个第一导电图案下方形成多个晶种层图案,其中多个重布线导电图案分别包括所述多个晶种层图案及所述多个第一导电图案。
在一些实施例中,其中所述多个第一导电图案的线宽度等于或小于1μm。
在一些实施例中,其中所述多个第一导电图案的线宽度等于或小于0.7μm。
在一些实施例中,其中通过蚀刻工艺局部地移除所述晶种层,且通过所述蚀刻工艺局部地移除所述多个第一导电图案。
在一些实施例中,所述方法进一步包括:在所述第一导电材料及所述第一光刻胶层之上形成第二光刻胶层,其中所述第二光刻胶层包括至少一个第二开口;在所述至少一个第二开口中形成第二导电材料;移除所述第二光刻胶层,以形成至少一个第二导电图案;以及形成介电层,其中所述至少一个第二导电图案设置在所述介电层中。
在一些实施例中,其中通过蚀刻工艺局部地移除所述晶种层,且通过所述蚀刻工艺局部地移除所述多个第一导电图案及所述至少一个第二导电图案。
在一些实施例中,其中所述第一光刻胶层及所述第二光刻胶层被同时移除。
在一些实施例中,其中所述管芯包括在其上的导电柱,且所述多个晶种层图案中的一者与所述导电柱接触。
根据本发明的替代实施例,一种制造重布线路结构的方法包括以下步骤。在管芯及包封所述管芯的包封体之上形成晶种层。在所述晶种层之上形成第一光刻胶材料。使用瑞利公式R=k1(λ/NA)中的条件,通过掩模将所述第一光刻胶材料曝光于I线步进光刻机内的I线波长,其中R是图案的分辨率,NA是数值孔径,λ是用于曝光的光的波长,且k1是等于或小于0.49的正常数。将所述第一光刻胶材料显影以形成第一光刻胶层,其中所述第一光刻胶层包括多个第一光刻胶图案及所述多个第一光刻胶图案之间的多个第一开口。在所述多个第一开口中形成第一导电材料。移除所述第一光刻胶层,以形成多个第一导电图案。使用所述多个第一导电图案作为掩模层,局部地移除所述晶种层,以在所述多个第一导电图案下方形成多个晶种层图案,其中多个重布线导电图案分别包括所述多个晶种层图案及所述多个第一导电图案。
在一些实施例中,其中k1是等于或小于0.35的正常数。
在一些实施例中,其中所述多个第一导电图案的线宽度等于或小于1μm。
在一些实施例中,其中所述多个第一导电图案的线宽度等于或小于0.7μm。
在一些实施例中,其中通过蚀刻工艺局部地移除所述晶种层,且通过所述蚀刻工艺局部地移除所述多个第一导电图案。
在一些实施例中,其中在执行所述蚀刻工艺之后,所述多个第一导电图案的宽度减小,且所述多个第一导电图案之间的间隔增大。
在一些实施例中,其中所述管芯包括在其上的导电柱,且所述多个晶种层图案中的一者与所述导电柱接触。
根据本发明的又一些替代实施例,一种制造重布线路结构的方法包括以下步骤。在管芯及包封所述管芯的包封体之上形成晶种层。在所述晶种层之上形成光刻胶材料。通过使用等于或小于0.18的数值孔径进行第一次曝光,通过第一掩模将所述光刻胶材料的第一部分曝光于I线步进光刻机内的I线波长。通过使用等于或小于0.18的数值孔径进行第二次曝光,通过第二掩模将所述光刻胶材料的第二部分曝光于所述I线步进光刻机内的所述I线波长,其中所述第一部分及所述第二部分交替设置。将所述光刻胶材料显影以形成光刻胶层,其中所述光刻胶层包括多个光刻胶图案及所述多个光刻胶图案之间的多个开口。在所述多个开口中形成导电材料。移除所述光刻胶层,以形成多个导电图案。通过使用所述多个导电图案作为掩模,局部地移除所述晶种层,以在所述多个导电图案下方形成多个晶种层图案,其中多个重布线导电图案分别包括所述多个晶种层图案及所述多个导电图案。
在一些实施例中,其中所述多个导电图案的线宽度等于或小于1μm。
在一些实施例中,其中所述多个导电图案的线宽度等于或小于0.7μm。
在一些实施例中,其中通过蚀刻工艺局部地移除所述晶种层,且通过所述蚀刻工艺局部地移除所述多个导电图案。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应了解,他们可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本发明的精神及范围,而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。
Claims (1)
1.一种制造重布线路结构的方法,所述方法包括:
在管芯及包封所述管芯的包封体之上形成晶种层;
在所述晶种层之上形成第一光刻胶材料;
使用等于或小于0.18的数值孔径,通过相移掩模将所述第一光刻胶材料曝光于I线步进光刻机内的I线波长;
将所述第一光刻胶材料显影以形成第一光刻胶层,其中所述第一光刻胶层包括多个第一光刻胶图案及所述多个第一光刻胶图案之间的多个第一开口;
在所述多个第一开口中形成第一导电材料;
移除所述第一光刻胶层,以形成多个第一导电图案;以及
使用所述多个第一导电图案作为掩模,局部地移除所述晶种层,以在所述多个第一导电图案下方形成多个晶种层图案,其中多个重布线导电图案分别包括所述多个晶种层图案及所述多个第一导电图案。
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