CN111128723B - Method for forming semiconductor nanowire - Google Patents
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- CN111128723B CN111128723B CN201911360925.6A CN201911360925A CN111128723B CN 111128723 B CN111128723 B CN 111128723B CN 201911360925 A CN201911360925 A CN 201911360925A CN 111128723 B CN111128723 B CN 111128723B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 239000002070 nanowire Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000001338 self-assembly Methods 0.000 claims abstract description 60
- 239000003054 catalyst Substances 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 33
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 41
- 238000002408 directed self-assembly Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 25
- 229920001400 block copolymer Polymers 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 239000011261 inert gas Substances 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 2
- 230000002209 hydrophobic effect Effects 0.000 description 20
- 229910052710 silicon Inorganic materials 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 239000004793 Polystyrene Substances 0.000 description 9
- 230000000737 periodic effect Effects 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 7
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 7
- 239000004926 polymethyl methacrylate Substances 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005289 physical deposition Methods 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000006555 catalytic reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 229920002223 polystyrene Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 210000005252 bulbus oculi Anatomy 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004054 semiconductor nanocrystal Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
Abstract
The invention provides a method for forming semiconductor nanowires, which comprises the steps of preparing periodically arranged island structures with uniform sizes through a guiding self-assembly process and corresponding photoetching and etching processes, and annealing the island structures, so that a catalyst layer in the island structures can catalyze semiconductor layers in the island structures to form semiconductor nanowires with uniform thickness and ordered arrangement.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a method for forming semiconductor nanowires.
Background
In recent years, with continuous research and study of the field of nanotechnology, materials with one-dimensional nanostructures, such as semiconductor nanowires, attract more and more eyeballs. The semiconductor nanowire has the characteristics of obvious quantum effect, ultra-large specific surface area and the like, and has good application prospects in the fields of MOS devices, sensors and the like.
Conventional semiconductor nanowires, such as silicon nanowires, are formed by catalyst growth of silicon nanowires by growing a layer of Ni on a silicon substrate, which at high temperatures liquefies and catalyzes the substrate silicon to form silicon nanowires. However, due to the influence of uniformity of the Ni film, the size of Ni at the time of liquefaction (i.e., the size of Ni-rich silicide formed by mutual dissolution of Ni and silicon on the silicon substrate) is not completely uniform and regularly arranged, so that the grown nanowires are uneven in thickness and disordered in arrangement.
Disclosure of Invention
The invention aims to provide a method for forming semiconductor nanowires, which is used for preparing island structures which are periodically arranged and uniform in size, and forming semiconductor nanowires which are uniform in thickness and orderly arranged under the actions of annealing and catalysis.
In order to solve the technical problems, the invention provides a method for forming a semiconductor nanowire, which comprises the following steps:
step S1: providing a substrate, and sequentially forming a catalyst layer, a semiconductor layer, a first hard mask layer and a patterned first guide self-assembly thereon;
step S2: etching the first hard mask layer by taking the patterned first guide self-assembly as a mask, wherein the patterned first hard mask layer is provided with a first groove, and a second hard mask layer with a material different from that of the first hard mask layer is filled in the first groove;
step S3: forming a third hard mask layer and a patterned second guide self-assembly layer above the first hard mask layer and the second hard mask layer in sequence, wherein the second guide self-assembly pattern and the first guide self-assembly pattern are overlapped with each other, and the third hard mask layer is made of a material different from the first hard mask layer and the second hard mask layer;
step S4: etching the third hard mask layer by taking the patterned second guide self-assembly as a mask to form a patterned third hard mask layer, and etching the second hard mask layer and the first hard mask layer by taking the patterned third hard mask layer as a mask to re-pattern the second hard mask layer and the first hard mask layer;
step S5: removing the third hard mask layer and removing the second hard mask layer or the first hard mask layer to form a mask pattern layer;
step S6: etching the semiconductor layer and the catalyst layer by taking the mask pattern layer as a mask to form an island-shaped structure;
step S7: the island structure is annealed so that the catalyst layer in the island structure catalyzes the semiconductor layer in the island structure to form nanowires.
Optionally, in the method for forming a semiconductor nanowire, the step of forming the patterned first directed self-assembly on the first hard mask layer includes:
step S11: forming a first photoresist layer on the first hard mask layer;
step S12: photoetching the first photoresist layer to form a patterned first photoresist layer, wherein the patterned first photoresist layer is provided with a second groove;
step S13: filling a first block copolymer in the second groove, and enabling the first block copolymer to perform self-assembly so as to form first guiding self-assembly with at least two structures;
step S14: and removing part of the structure in the first guiding self-assembly to form the patterned first guiding self-assembly.
Optionally, in the method for forming a semiconductor nanowire, the step of forming the patterned second directed self-assembly on the third hard mask layer includes:
step S31: forming a second photoresist layer on the third hard mask layer;
step S32: photoetching the second photoresist layer to form a patterned second photoresist layer, wherein the patterned second photoresist layer is provided with a third groove;
step S33: filling a second block copolymer in the third groove, and enabling the second block copolymer to perform self-assembly so as to form second guiding self-assembly with at least two structures;
step S34: and removing part of the structure in the second guiding self-assembly to form the patterned second guiding self-assembly.
Optionally, in the method for forming a semiconductor nanowire, a certain angle exists between the patterned first directed self-assembly and the patterned second directed self-assembly, and the range of the angle is: 0-90 deg. and not 0 deg..
Optionally, in the method for forming a semiconductor nanowire, a machine for forming the patterned first photoresist layer and the patterned second photoresist layer includes a KrF, arF or I-line lithography machine.
Optionally, in the method for forming a semiconductor nanowire, nitrogen and/or inert gas is introduced during the process of growing the semiconductor layer on the catalyst layer to prevent oxidation.
Optionally, in the method for forming a semiconductor nanowire, a stop layer is further formed between the semiconductor layer and the first hard mask layer.
Optionally, in the method for forming a semiconductor nanowire, the island-shaped structure is a structure with periodic arrangement and uniform size.
Optionally, in the method for forming a semiconductor nanowire, in step S7, the annealing temperature is 1000 ℃ to 1200 ℃, and the annealing process is performed under a nitrogen and/or inert gas environment.
Optionally, in the method for forming a semiconductor nanowire, the material of the catalyst layer is at least one of Au, ni, co, ti, in and Fe.
In summary, the present invention provides a method for forming a semiconductor nanowire, which prepares an island structure with a periodic arrangement and a uniform size by guiding a self-assembly process and a corresponding photolithography and etching process, and anneals the island structure, so that a catalyst layer in the island structure can catalyze a semiconductor layer in the island structure to form a semiconductor nanowire with uniform thickness and ordered arrangement. Since the island structures are uniform in size such that the amount of catalyst present in each of the island structures is substantially the same, the catalyst-rich semiconductor compound formed during annealing is uniform in size; and the island structures are periodically arranged, so that the formed semiconductor compounds rich in the catalyst are also periodically arranged, and finally the semiconductor nanowires with uniform thickness and ordered arrangement can be formed.
Drawings
FIG. 1 is a microscopic image of a silicon nanowire;
FIG. 2 is a flow chart of a method for forming semiconductor nanowires according to an embodiment of the invention;
FIGS. 3 a-3 d are schematic diagrams illustrating a first patterned directed self-assembly forming process according to an embodiment of the present invention;
FIGS. 4 a-4 b are cross-sectional and perspective views of a first hard mask layer structure patterned in accordance with one embodiment of the present invention;
FIGS. 5 a-5 b are cross-sectional and perspective views of a second hard mask layer formed in accordance with one embodiment of the present invention;
FIGS. 6 a-6 d are schematic diagrams illustrating a process for forming a patterned second-oriented self-assembly according to one embodiment of the present invention;
FIGS. 7 a-7 b are cross-sectional and perspective views of a patterned third hard mask layer structure in accordance with one embodiment of the present invention;
FIGS. 8-10 are schematic views illustrating a process for forming island structures according to an embodiment of the invention;
FIGS. 11 a-11 c are schematic views of a process for forming semiconductor nanowires by catalyzing a semiconductor island located directly above a catalyst by a catalyst island at a high temperature in accordance with an embodiment of the present invention;
wherein in fig. 3 a-11 c:
10-substrate, 20-catalyst layer, 201-catalyst island, 30-semiconductor layer, 301-semiconductor island, 3011-nanowire mandrel, 3012-nanowire shell, 3013-catalyst, 40-stop layer, 50-first hard mask layer, 501-patterned first hard mask layer, 502-second patterned first hard mask layer, 60-patterned first photoresist layer, 61-patterned second photoresist layer, 70-first block copolymer, 71-second block copolymer, 701-first directed self-assembled hydrophobic portion, 702-first directed self-assembled hydrophilic portion, 711-second directed self-assembled hydrophobic portion, 712-second directed self-assembled hydrophilic portion, 80-second hard mask layer, 801-patterned second hard mask layer, 90-third hard mask layer, 901-patterned third hard mask layer.
Detailed Description
Conventional catalysts grow semiconductor nanowires, such as silicon nanowires, by growing a layer of Ni on a silicon substrate, which at high temperatures liquefies and catalyzes the substrate silicon to form silicon nanowires. However, due to the influence of uniformity of the Ni film, the size of Ni at the time of liquefaction (i.e., the size of Ni-rich silicide formed by mutual dissolution of Ni and silicon on the silicon substrate) is not completely uniform and regularly arranged, so that the grown nanowires are uneven in thickness and disordered in arrangement, see fig. 1.
In order to prepare the island-shaped structure which is periodically arranged and uniform in size, and form the semiconductor nanowires with uniform thickness and ordered arrangement under the actions of annealing and catalysis, the invention provides a method for forming the semiconductor nanowires.
Referring to fig. 2, the method for forming the semiconductor nanowire includes:
step S1: providing a substrate, and sequentially forming a catalyst layer, a semiconductor layer, a first hard mask layer and a patterned first guide self-assembly thereon;
step S2: etching the first hard mask layer by taking the patterned first guide self-assembly as a mask, wherein the patterned first hard mask layer is provided with a first groove, and a second hard mask layer with a material different from that of the first hard mask layer is filled in the first groove;
step S3: forming a third hard mask layer and a patterned second guide self-assembly layer above the first hard mask layer and the second hard mask layer in sequence, wherein the second guide self-assembly pattern and the first guide self-assembly pattern are overlapped with each other, and the third hard mask layer is made of a material different from the first hard mask layer and the second hard mask layer;
step S4: etching the third hard mask layer by taking the patterned second guide self-assembly as a mask to form a patterned third hard mask layer, and etching the second hard mask layer and the first hard mask layer by taking the patterned third hard mask layer as a mask to re-pattern the second hard mask layer and the first hard mask layer;
step S5: removing the third hard mask layer and removing the second hard mask layer or the first hard mask layer to form a mask pattern layer;
step S6: etching the semiconductor layer and the catalyst layer by taking the mask pattern layer as a mask to form an island-shaped structure;
step S7: the island structure is annealed so that the catalyst layer in the island structure catalyzes the semiconductor layer in the island structure to form nanowires.
Referring to fig. 3a, in step S1, a substrate 10 is provided first, where the substrate 10 may be a Si substrate or other material substrate, but is not limited thereto, and may be any substrate. The catalyst layer 20 is formed on the upper surface of the substrate 10, preferably by physical deposition, and more preferably by laser-induced plasma physical deposition. The material of the catalyst layer 20 is preferably at least one of Au, ni, co, ti, in and Fe, and the thickness is preferably 10nm to 50nm.
With continued reference to fig. 3a, in step S1, a semiconductor layer 30 is formed on the upper surface of the catalyst layer 20, preferably by chemical vapor deposition. In the forming process, nitrogen and/or inert gas is/are introduced to prevent oxidation, wherein the inert gas comprises helium, argon or the like. The material of the semiconductor layer 30 is preferably at least one of Si, ge, sn, se, te and B, etc., and the thickness is preferably 100nm to 500nm.
With continued reference to fig. 3a, in step S1, a first hard mask layer 50 is formed over the semiconductor layer 30, where the forming method includes physical deposition or chemical deposition, and the material of the first hard mask layer 50 is preferably SiN (silicon nitride) and the thickness is preferably 25nm to 60nm. A stop layer 40 may be further formed between the semiconductor layer 30 and the first hard mask layer 50, and the material of the stop layer 40 is preferably ALN, and the thickness is preferably 5nm to 30nm.
Then, in step S1, a patterned first directed self-assembly is formed over the first hard mask layer 50. The forming process of the patterned first guiding self-assembly comprises the following steps:
step S11: forming a first photoresist layer on the first hard mask layer 50;
step S12: photoetching the first photoresist layer to form a patterned first photoresist layer 60, wherein the patterned first photoresist layer 60 is provided with a second groove;
step S13: filling a first block copolymer 70 in the second trench, and self-assembling the first block copolymer 70 to form a first guided self-assembly having at least two structures;
step S14: and removing part of the structure in the first guiding self-assembly to form the patterned first guiding self-assembly.
With continued reference to fig. 3a, in step S11, a first photoresist layer is formed on the upper surface of the first hard mask layer 50 by spin coating; in step S12, the first photoresist layer is subjected to photolithography exposure to form a patterned first photoresist layer 60, i.e. the first photoresist layer is provided with a second trench, and the second trench may be a trench with a larger size, and the size may range from several tens of nanometers to several micrometers. The photoetching can be performed by adopting an I-line, krF or ArF photoetching machine according to the size requirement of the second groove.
Referring to fig. 3b and 3c, in step S13, the second trench is filled with a first block copolymer 70, and the first block copolymer 70 may include a hydrophobic portion and a hydrophilic portion, such as PS-b-PMMA (where PS is Polystyrene, polystyrene; PMMA is Polymethylmethacrylate), where PS is a hydrophobic portion, PMMA is a hydrophilic portion, and the patterned first photoresist layer 60 is hydrophobic. The first block copolymer 70 is self-assembled to form a first directed self-assembly having at least two structures, wherein the method of self-assembling the first block copolymer 70 is preferably heating. For example, during heating, the hydrophobic portions (e.g., PS) and the hydrophilic portions (e.g., PMMA) begin to self-assemble to form a first guided self-assembly, the hydrophobic portions (e.g., PS) will preferentially be adjacent to the hydrophobic patterned first photoresist layer 60, the hydrophilic portions (e.g., PMMA) will be between the hydrophobic portions (e.g., PS), and finally the first guided self-assembled hydrophobic portions 701 and 702 will be formed.
Referring to fig. 3d, in step S14, a portion of the structure in the first directed self-assembly is removed to form the patterned first directed self-assembly. The removing method may be ultraviolet exposure or etching, preferably selective etching, further, the selective etching is preferably dry etching, and the etching gas is preferably O2, that is, the partial structure in the first guiding self-assembly is removed by using the selective etching of O2. And the partial structure in the first directed self-assembly refers to the first directed self-assembled hydrophilic portion 702. That is, the first guided self-assembled hydrophilic portion 702 is removed by selective etching, leaving the first guided self-assembled hydrophobic portion 701 to form a patterned first guided self-assembly. The patterned first-guide self-assembly may be formed to a resolution of tens of nanometers, the line width (the first-guide self-assembly hydrophobic portion 701, for example, PS) may be formed to a resolution of tens of nanometers, the line width may be adjusted according to the requirements of the nanowire size, the minimum line width used in this embodiment is 30nm, and the size and the line width of the trench in the patterned first-guide self-assembly may be 1:1 or not.
Referring to fig. 4a and 4b, in step S2, first, using the patterned first directed self-assembly as a mask, etching the first hard mask layer 50 to form a patterned first hard mask layer 501, where the patterned first hard mask layer 501 has a first trench; then, mask materials different from the first hard mask layer can be deposited on the surfaces of the patterned first hard mask layer 501 and the first trenches through chemical vapor deposition, sputtering deposition and other processes until the deposited materials fill each first trench; next, the filled material is planarized to the upper surface of the patterned first mask layer 501 by a chemical mechanical polishing or the like process to form a second hard mask layer 80 filled in each of the first trenches (see fig. 5a and 5 b). I.e. the patterned first directed self-assembled pattern is transferred onto the first hard mask 50 by etching, and then the first trench is filled with a second hard mask layer 80 of a material different from the first hard mask layer 50, the material of the second hard mask layer 80 preferably being SiO 2 Provision is made for self-assembly of the patterned second guide. At this time, the first hard mask layer 50 and the second hard mask layer 80 are elongated.
Referring to fig. 6a to 6d, in step S3, a third hard mask layer 90 and a patterned second directed self-assembly are formed over the first hard mask layer 50 and the second hard mask layer 80, and the second directed self-assembly pattern and the first directed self-assembly pattern overlap each other, and the third hard mask layer 90 is made of a material different from the first hard mask layer 50 and the second hard mask layer 80. The third hard mask layer 90 is preferably APF (advanced patterning film ), and is preferably formed by chemical vapor deposition as a material having an etching ratio selective to the material of the first hard mask layer 50 and the second hard mask layer 80. A patterned second directed self-assembly is then formed on the upper surface of the third hard mask layer 90. The forming method of the patterned second guiding self-assembly comprises the following steps:
step S31: forming a second photoresist layer on the third hard mask layer 90;
step S32: photoetching the second photoresist layer to form a patterned second photoresist layer 61, wherein the patterned second photoresist layer 61 is provided with a third groove;
step S33: filling a second block copolymer 71 in the third trench, and subjecting the second block copolymer 71 to self-assembly to form a second guided self-assembly having at least two structures;
step S34: and removing part of the structure in the second guiding self-assembly to form the patterned second guiding self-assembly.
Referring to fig. 6a, first, in step S31, a photoresist layer is coated on the third hard mask layer 90 to form a second photoresist layer; next, in step S32, the second photoresist layer is subjected to photolithography to form a patterned second photoresist layer 61 with a third trench, where the photolithography may use a photolithography machine such as I-line, krF, arF, or the like according to the size requirement of the third trench. The third grooves may have a size ranging from several tens of nanometers to several micrometers, and may be the same as or different from the second grooves.
Referring to fig. 6b and 6c, in step S33, the second block copolymer 71 is filled in the third trench, and the second block copolymer 71 may include a hydrophobic portion and a hydrophilic portion, for example, PS-b-PMMA, which may be the same as or different from the first block copolymer 70. The method for self-assembling the second block copolymer 71 is preferably heating, for example, during which the hydrophilic portion and the hydrophobic portion start to self-assemble to form a second directed self-assembly, the hydrophobic portion is preferentially adjacent to the hydrophobic patterned second photoresist layer 61, the hydrophilic portion is located between the hydrophobic portions, and finally the second directed self-assembly is formed with at least two structures, for example, the two structures including the second directed self-assembled hydrophobic portion 711 and the second directed self-assembled hydrophilic portion 712.
Referring to fig. 6d, in step S34, a portion of the structure in the second directed self-assembly is removed to form the patterned second directed self-assembly. The removal may be by ultraviolet exposure or etching, preferably by selective etching. And the partial structure in the second directed self-assembly refers to the second directed self-assembled hydrophilic portion 712, i.e., the second directed self-assembled hydrophilic portion 712 is removed by selective etching, and the second directed self-assembled hydrophobic portion 711 is retained, forming a patterned second directed self-assembly. The patterned second-guide self-assembly may be formed to a resolution of tens of nanometers, the line width (second-guide self-assembly hydrophobic portion 711, e.g., PS) may be formed to a resolution of tens of nanometers, the line width may be adjusted according to the requirements of the nanowire size, the minimum line width used in this embodiment is 30nm, and the size and line width of the trench in the patterned second-guide self-assembly may be 1:1 or not. The second self-assembled pattern and the first self-assembled pattern overlap each other, i.e. a certain angle exists between the second self-assembled pattern and the first self-assembled pattern, and the angle ranges from 0 ° to 90 ° and is not 0 °, preferably 90 °, i.e. the second self-assembled pattern is preferably perpendicular to the first self-assembled pattern. The period and line size (line width) of the patterned second guide self-assembled pattern and the patterned first guide self-assembled pattern may be identical, or may be identical, that is, the period and line size of the two patterns may be identical, or may be identical.
See fig. 7a and 7b, in step S4, the third hard mask layer 90 is etched with the patterned second directed self-assembly as a mask, so as to form a patterned third hard mask layer 901, i.e. the patterned second directed self-assembly pattern is transferred onto the third hard mask layer 90 by etching. Referring to fig. 8, the second hard mask layer 80 and the patterned first hard mask layer 501 are etched by using the patterned third hard mask layer 901 as a mask, so as to pattern the second hard mask layer and the first hard mask layer again, i.e. form a second patterned first hard mask layer 502 and a patterned second hard mask layer 801, where the second patterned first hard mask layer 502 and the patterned second hard mask layer 801 are all cut off from the stripe structure at multiple positions to form an island structure. The material of the second patterned first hard mask layer 502 is preferably SiN and the material of the second hard mask layer 80 is preferably SiO 2 (silicon oxide) the third hard mask layer 90 is preferably APF because of SiN and SiO 2 The selectivity to APF can be tuned to be uniform so that the pattern on the third hard mask layer 90 can be transferred to the patterned first hard mask layer 501 and second hard mask layer 80 by etching, and the etching process does not affect the semiconductor layer 30 because of the presence of the stop layer 40.
Referring to fig. 9, in step S5, the third hard mask layer 90 is removed, and the second hard mask layer 80 or the first hard mask layer 50 is removed to form a mask pattern layer. The removal method is preferably a wet etch, after which only the second patterned hard mask layer 502 or the patterned second hard mask layer 801 remains.
Referring to fig. 10, in step S6, the semiconductor layer 30 and the catalyst layer 20 are etched using the mask pattern layer as a mask to form an island structure. The etching is preferably dry etching, and an etching gas, such as Cl, is selected by using a selectivity ratio among the mask pattern layer, the semiconductor layer 30, and the catalyst layer 20 2 . I.e., the pattern of the mask pattern layer is transferred onto the semiconductor layer 30 and the catalyst layer 20 by etching, and finally an island-like structure, i.e., the semiconductor islands 301+ the catalyst islands 201, is formed. The island-like structures are periodically arranged in all dimensionsThe uniform islands form a periodic island-like structure array. The periodic island-like structure array can be a square periodic array, a hexagonal periodic array or any array between the square periodic array and the hexagonal periodic array.
Referring to fig. 11a to 11c, in step S7, the island structure is annealed so that the catalyst layer in the island structure can catalyze the semiconductor layer in the island structure to form nanowires. I.e. the island structure is annealed at high temperature to form a semiconductor nanowire. The annealing temperature ranges from 1000 ℃ to 1200 ℃, and the annealing process is performed in a nitrogen and/or inert gas environment, wherein the inert gas comprises helium, argon or the like. In the annealing process, the catalyst layer in the island structure is first mutually dissolved with the semiconductor layer positioned right above the catalyst layer to form a semiconductor compound rich in catalyst, and the semiconductor nano wires (30 nm-100 nm) which are periodically arranged and have uniform sizes can be generated after continuous annealing, wherein the top ends of the nano wires are catalysts 3013, the nano wire shell 3012 is non-luminous oxide, and the nano wire core shaft 3011 is a semiconductor nano crystal (< 5 nm) capable of luminous. If the material of the semiconductor layer is amorphous Si, the catalytic process is more efficient because the grown amorphous Si is less dense than the substrate and is located directly above the catalyst. And because the size formed by the first guide self-assembly and the second guide self-assembly can reach the resolution of tens of nanometers, that is, compared with the traditional process, the guide self-assembly can form smaller size at one time, thereby forming smaller catalyst islands 201 and finally catalyzing and generating finer nanowires.
The islands of catalyst 201 formed in the present invention are uniform in size, i.e., the islands of catalyst 201 in the islands are uniform in size such that the amount of catalyst present in each of the islands is substantially the same, and thus the catalyst-rich semiconductor compound formed is uniform in size during annealing. Since the size of the catalyst-rich semiconductor compound formed is critical to the thickness of the semiconductor nanowire, the larger the size of the catalyst-rich semiconductor compound, the thicker the semiconductor nanowire formed, and in the present invention, the size of the catalyst-rich semiconductor compound formed is uniform, and thus, the thickness of the finally formed semiconductor nanowire is also uniform. And the island structures are arranged periodically, so that the finally formed semiconductor nanowires are also arranged periodically, namely the semiconductor nanowires with uniform thickness and ordered arrangement are finally formed.
Therefore, the semiconductor nanowire forming method provided by the invention prepares the island-shaped structure which is periodically arranged and has uniform size through the guiding self-assembly process and the corresponding photoetching and etching process, catalyzes the semiconductor layer above the catalyst layer at high temperature, and forms the semiconductor nanowire with uniform thickness and ordered arrangement.
Finally, it should be noted that the above-mentioned embodiments are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Equivalent changes and modifications are intended to be within the scope of the present invention as defined in the appended claims.
Claims (10)
1. A method of forming a semiconductor nanowire, comprising the steps of:
step S1: providing a substrate, and sequentially forming a catalyst layer, a semiconductor layer, a first hard mask layer and a patterned first guiding self-assembly on the substrate, wherein the semiconductor layer is made of amorphous Si;
step S2: etching the first hard mask layer by taking the patterned first guide self-assembly as a mask, wherein the patterned first hard mask layer is provided with a first groove, and a second hard mask layer with a material different from that of the first hard mask layer is filled in the first groove;
step S3: forming a third hard mask layer and a patterned second guide self-assembly layer above the first hard mask layer and the second hard mask layer in sequence, wherein the second guide self-assembly pattern and the first guide self-assembly pattern are overlapped with each other, and the third hard mask layer is made of a material different from the first hard mask layer and the second hard mask layer;
step S4: etching the third hard mask layer by taking the patterned second guide self-assembly as a mask to form a patterned third hard mask layer, and etching the second hard mask layer and the first hard mask layer by taking the patterned third hard mask layer as a mask to re-pattern the second hard mask layer and the first hard mask layer;
step S5: removing the third hard mask layer and removing the second hard mask layer or the first hard mask layer to form a mask pattern layer;
step S6: etching the semiconductor layer and the catalyst layer by taking the mask pattern layer as a mask to form an island-shaped structure;
step S7: the island structure is annealed so that the catalyst layer in the island structure catalyzes the semiconductor layer in the island structure to form nanowires.
2. The method of forming a semiconductor nanowire of claim 1, wherein forming the patterned first directed self-assembly on the first hard mask layer comprises:
step S11: forming a first photoresist layer on the first hard mask layer;
step S12: photoetching the first photoresist layer to form a patterned first photoresist layer, wherein the patterned first photoresist layer is provided with a second groove;
step S13: filling a first block copolymer in the second groove, and enabling the first block copolymer to perform self-assembly so as to form first guiding self-assembly with at least two structures;
step S14: and removing part of the structure in the first guiding self-assembly to form the patterned first guiding self-assembly.
3. The method of forming a semiconductor nanowire of claim 1, wherein forming the patterned second directed self-assembly on the third hard mask layer comprises:
step S31: forming a second photoresist layer on the third hard mask layer;
step S32: photoetching the second photoresist layer to form a patterned second photoresist layer, wherein the patterned second photoresist layer is provided with a third groove;
step S33: filling a second block copolymer in the third groove, and enabling the second block copolymer to perform self-assembly so as to form second guiding self-assembly with at least two structures;
step S34: and removing part of the structure in the second guiding self-assembly to form the patterned second guiding self-assembly.
4. The method of forming a semiconductor nanowire of claim 1, wherein an angle exists between the patterned first directed self-assembly and the patterned second directed self-assembly, the angle ranging from: 0-90 deg. and not 0 deg..
5. The method of forming a semiconductor nanowire as recited in claim 2 or 3, wherein the means for forming the patterned first photoresist layer and the patterned second photoresist layer comprises a KrF, arF, or I-line lithography machine.
6. The method of forming a semiconductor nanowire as claimed in claim 1, wherein nitrogen and/or inert gas is introduced during the growth of the semiconductor layer on the catalyst layer to prevent oxidation.
7. The method of forming a semiconductor nanowire as recited in claim 1, wherein a stop layer is further formed between the semiconductor layer and the first hard mask layer.
8. The method of forming a semiconductor nanowire as recited in claim 1, wherein said island-like structure is a periodically arranged, uniform-sized structure.
9. The method of forming a semiconductor nanowire as claimed in claim 1, wherein in the step S7, the annealing is performed at a temperature of 1000 ℃ to 1200 ℃ under nitrogen and/or inert gas atmosphere.
10. The method of forming a semiconductor nanowire as claimed in claim 1, wherein the material of the catalyst layer is at least one of Au, ni, co, ti, in and Fe.
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