CN111128723A - Method for forming semiconductor nano-wire - Google Patents
Method for forming semiconductor nano-wire Download PDFInfo
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- CN111128723A CN111128723A CN201911360925.6A CN201911360925A CN111128723A CN 111128723 A CN111128723 A CN 111128723A CN 201911360925 A CN201911360925 A CN 201911360925A CN 111128723 A CN111128723 A CN 111128723A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
Abstract
The invention provides a method for forming semiconductor nanowires, which is characterized in that island-shaped structures which are periodically arranged and have uniform sizes are prepared through a guided self-assembly process and corresponding photoetching and etching processes, and the island-shaped structures are annealed, so that a catalyst layer in the island-shaped structures can catalyze a semiconductor layer in the island-shaped structures to form semiconductor nanowires which are uniform in thickness and ordered in arrangement.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a method for forming a semiconductor nanowire.
Background
In recent years, with the continuous research and study of nanotechnology fields, materials having one-dimensional nanostructures, such as semiconductor nanowires, attract more and more people. The semiconductor nanowire has the characteristics of obvious quantum effect, ultra-large specific surface area and the like, and has good application prospect in the fields of MOS devices, sensors and the like.
The traditional method for forming semiconductor nanowires, such as silicon nanowires, is to grow a layer of Ni on a silicon substrate by using a catalyst, wherein the Ni layer liquefies and catalyzes the substrate silicon to form the silicon nanowires at high temperature. However, due to the effect of the uniformity of the Ni thin film, the size of the liquefied Ni (i.e., the size of the Ni-rich silicide formed by dissolving Ni in silicon on the silicon substrate) is not completely uniform and regularly arranged, and thus the grown nanowires have non-uniform thickness and random arrangement.
Disclosure of Invention
The invention aims to provide a method for forming semiconductor nanowires, which is used for preparing island-shaped structures which are periodically arranged and have uniform sizes and forming semiconductor nanowires with uniform thickness and ordered arrangement under the action of annealing and catalysis.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor nanowire, comprising the steps of:
step S1: providing a substrate, and sequentially forming a catalyst layer, a semiconductor layer, a first hard mask layer and a patterned first guide self-assembly on the substrate;
step S2: etching the first hard mask layer by taking the patterned first guide self-assembly as a mask to form a patterned first hard mask layer, wherein the patterned first hard mask layer is provided with a first groove, and a second hard mask layer with the material different from that of the first hard mask layer is filled in the first groove;
step S3: sequentially forming a third hard mask layer and a patterned second oriented self-assembly above the first hard mask layer and the second hard mask layer, wherein the second oriented self-assembly pattern and the first oriented self-assembly pattern are overlapped, and the material of the third hard mask layer is different from that of the first hard mask layer and the second hard mask layer;
step S4: etching the third hard mask layer by taking the graphical second oriented self-assembly as a mask to form a graphical third hard mask layer, and etching the second hard mask layer and the first hard mask layer by taking the graphical third hard mask layer as a mask to graph the second hard mask layer and the first hard mask layer again;
step S5: removing the third hard mask layer, and removing the second hard mask layer or the first hard mask layer to form a mask patterning layer;
step S6: etching the semiconductor layer and the catalyst layer by taking the mask pattern layer as a mask to form an island-shaped structure;
step S7: and annealing the island structures so that the catalyst layers in the island structures can catalyze the semiconductor layers in the island structures to form the nanowires.
Optionally, in the method for forming a semiconductor nanowire, the step of forming the patterned first guided self-assembly on the first hard mask layer includes:
step S11: forming a first photoresist layer on the first hard mask layer;
step S12: photoetching the first photoresist layer to form a patterned first photoresist layer, wherein the patterned first photoresist layer is provided with a second groove;
step S13: filling a first block copolymer in the second groove, and enabling the first block copolymer to carry out self-assembly so as to form a first oriented self-assembly with at least two structures;
step S14: removing part of the structure in the first guided self-assembly to form the patterned first guided self-assembly.
Optionally, in the method for forming a semiconductor nanowire, the step of forming the patterned second guided self-assembly on the third hard mask layer includes:
step S31: forming a second photoresist layer on the third hard mask layer;
step S32: photoetching the second photoresist layer to form a patterned second photoresist layer, wherein the patterned second photoresist layer is provided with a third groove;
step S33: filling a second block copolymer in the third groove, and enabling the second block copolymer to carry out self-assembly so as to form second oriented self-assembly with at least two structures;
step S34: removing part of the structure in the second guided self-assembly to form the patterned second guided self-assembly.
Optionally, in the method for forming a semiconductor nanowire, an angle exists between the patterned first guided self-assembly and the patterned second guided self-assembly, and the angle ranges from: 0 to 90 degrees and not 0 degrees.
Optionally, in the method for forming a semiconductor nanowire, a machine for forming the patterned first photoresist layer and the patterned second photoresist layer includes a KrF, ArF, or I-line lithography machine.
Optionally, in the method for forming a semiconductor nanowire, nitrogen and/or an inert gas is introduced during the process of growing the semiconductor layer on the catalyst layer to prevent oxidation.
Optionally, in the method for forming a semiconductor nanowire, a stop layer is further formed between the semiconductor layer and the first hard mask layer.
Optionally, in the method for forming a semiconductor nanowire, the island-shaped structures are periodically arranged and have uniform sizes.
Optionally, in the method for forming a semiconductor nanowire, in step S7, the annealing temperature is 1000 ℃ to 1200 ℃, and the annealing process is performed in a nitrogen and/or inert gas environment.
Optionally, In the method for forming a semiconductor nanowire, the material of the catalyst layer is at least one of Au, Ni, Co, Ti, In, and Fe.
In summary, the invention provides a method for forming semiconductor nanowires, which includes preparing periodically arranged island-shaped structures with uniform size by using a guided self-assembly process and corresponding photolithography and etching processes, and annealing the island-shaped structures, so that a catalyst layer in the island-shaped structures can catalyze a semiconductor layer in the island-shaped structures to form semiconductor nanowires with uniform thickness and ordered arrangement. Because the island structures are uniform in size such that each of the island structures has substantially the same amount of catalyst, the catalyst-rich semiconductor compound formed during the annealing process is uniform in size; and because the island-shaped structures are arranged periodically, the formed semiconductor compounds rich in the catalyst are also arranged periodically, and finally, the semiconductor nanowires with uniform thickness and ordered arrangement can be formed.
Drawings
FIG. 1 is a microscope photograph of a silicon nanowire;
FIG. 2 is a flow chart of a method of forming a semiconductor nanowire in accordance with one embodiment of the present invention;
FIGS. 3 a-3 d are schematic diagrams illustrating a first patterned guided self-assembly process according to an embodiment of the invention;
FIGS. 4 a-4 b are cross-sectional and perspective views illustrating the formation of a patterned first hard mask layer structure in accordance with one embodiment of the present invention;
FIGS. 5 a-5 b are a cross-sectional view and a perspective view of a second hard mask layer formed in an embodiment of the present invention;
FIGS. 6 a-6 d are schematic diagrams illustrating a second patterned guided self-assembly process according to an embodiment of the present invention;
FIGS. 7 a-7 b are cross-sectional and perspective views of a third patterned hard mask layer structure in accordance with an embodiment of the present invention;
FIGS. 8-10 are schematic views illustrating a process for forming an island structure according to an embodiment of the invention;
FIGS. 11 a-11 c are schematic diagrams illustrating a process for generating a semiconductor nanowire by catalyzing, by a catalyst island, a semiconductor island located directly above a catalyst at an elevated temperature according to an embodiment of the present invention;
wherein in FIGS. 3 a-11 c:
10-substrate, 20-catalyst layer, 201-catalyst island, 30-semiconductor layer, 301-semiconductor island, 3011-nanowire mandrel, 3012-nanowire shell, 3013-catalyst, 40-stop layer, 50-first hardmask layer, 501-patterned first hardmask layer, 502-second patterned first hardmask layer, 60-patterned first photoresist layer, 61-patterned second photoresist layer, 70-first block copolymer, 71-second block copolymer, 701-first guided self-assembly hydrophobic portion, 702-first guided self-assembly hydrophilic portion, 711-second guided self-assembly hydrophobic portion, 712-second guided self-assembly hydrophilic portion, 80-second hardmask layer, 801-patterned second hardmask layer, 90-third hard mask layer, 901-patterned third hard mask layer.
Detailed Description
The traditional catalyst for growing semiconductor nanowires, such as silicon nanowires, grows a layer of Ni on a silicon substrate, and the Ni layer can liquefy and catalyze the substrate silicon to generate the silicon nanowires at high temperature. However, due to the effect of the uniformity of the Ni thin film, the size of the liquefied Ni (i.e., the size of the Ni-rich silicide formed by dissolving Ni and si on the si substrate) is not completely uniform and regularly arranged, so the grown nanowires have non-uniform thickness and are randomly arranged, as shown in fig. 1.
The invention provides a method for forming semiconductor nanowires, which aims to prepare island-shaped structures which are periodically arranged and have uniform sizes and form semiconductor nanowires with uniform thickness and ordered arrangement under the annealing and catalysis effects.
Referring to fig. 2, the method for forming the semiconductor nanowire includes:
step S1: providing a substrate, and sequentially forming a catalyst layer, a semiconductor layer, a first hard mask layer and a patterned first guide self-assembly on the substrate;
step S2: etching the first hard mask layer by taking the patterned first guide self-assembly as a mask to form a patterned first hard mask layer, wherein the patterned first hard mask layer is provided with a first groove, and a second hard mask layer with the material different from that of the first hard mask layer is filled in the first groove;
step S3: sequentially forming a third hard mask layer and a patterned second oriented self-assembly above the first hard mask layer and the second hard mask layer, wherein the second oriented self-assembly pattern and the first oriented self-assembly pattern are overlapped, and the material of the third hard mask layer is different from that of the first hard mask layer and the second hard mask layer;
step S4: etching the third hard mask layer by taking the graphical second oriented self-assembly as a mask to form a graphical third hard mask layer, and etching the second hard mask layer and the first hard mask layer by taking the graphical third hard mask layer as a mask to graph the second hard mask layer and the first hard mask layer again;
step S5: removing the third hard mask layer, and removing the second hard mask layer or the first hard mask layer to form a mask patterning layer;
step S6: etching the semiconductor layer and the catalyst layer by taking the mask pattern layer as a mask to form an island-shaped structure;
step S7: and annealing the island structures so that the catalyst layers in the island structures can catalyze the semiconductor layers in the island structures to form the nanowires.
Referring to fig. 3a, in step S1, a substrate 10 is first provided, where the substrate 10 may be a Si substrate or a substrate made of other materials, but is not limited thereto, i.e., may be any substrate. The catalyst layer 20 is formed on the upper surface of the substrate 10 by a method preferably including physical deposition, and more preferably by laser-induced plasma physical deposition. The material of the catalyst layer 20 is preferably at least one of Au, Ni, Co, Ti, In, Fe, etc., and the thickness is preferably 10nm to 50 nm.
Continuing with fig. 3a, in step S1, a semiconductor layer 30 is formed on the upper surface of the catalyst layer 20, preferably by chemical vapor deposition. During the formation process, nitrogen and/or inert gas including helium, argon, etc. is introduced to prevent oxidation. The material of the semiconductor layer 30 is preferably at least one of Si, Ge, Sn, Se, Te, B, etc., and the thickness is preferably 100nm to 500 nm.
With reference to fig. 3a, in step S1, a first hard mask layer 50 is formed on the semiconductor layer 30 by a physical deposition method or a chemical deposition method, wherein the first hard mask layer 50 is preferably SiN (silicon nitride) and has a thickness of 25nm to 60 nm. A stop layer 40 may be further formed between the semiconductor layer 30 and the first hard mask layer 50, wherein the material of the stop layer 40 is preferably ALN, and the thickness is preferably 5nm to 30 nm.
Then, in step S1, a patterned first guided self-assembly is formed over the first hard mask layer 50. The forming process of the patterned first guided self-assembly comprises the following steps:
step S11: forming a first photoresist layer on the first hard mask layer 50;
step S12: photoetching the first photoresist layer to form a patterned first photoresist layer 60, wherein the patterned first photoresist layer 60 is provided with a second groove;
step S13: filling the second trench with a first block copolymer 70, and allowing the first block copolymer 70 to self-assemble to form a first directed self-assembly having at least two structures;
step S14: removing part of the structure in the first guided self-assembly to form the patterned first guided self-assembly.
Continuing to refer to fig. 3a, in step S11, a first photoresist layer is formed on the upper surface of the first hard mask layer 50 by spin coating; in step S12, the first photoresist layer is lithographically exposed to form the patterned first photoresist layer 60, i.e., such that the first photoresist layer has second trenches, which may be larger trenches, ranging from tens of nanometers to several micrometers. The photoetching machine can be an I-line photoetching machine, a KrF photoetching machine or an ArF photoetching machine according to the size requirement of the second groove.
Referring to fig. 3b and 3c, in step S13, the second trenches are filled with a first block copolymer 70, and the first block copolymer 70 may include a hydrophobic portion and a hydrophilic portion, such as PS-b-PMMA (where PS is Polystyrene, Polystyrene; PMMA is Polymethylmethacrylate), where PS is the hydrophobic portion, PMMA is the hydrophilic portion, and the patterned first photoresist layer 60 is hydrophobic. The first block copolymer 70 is self-assembled to form a first directed self-assembly having at least two structures, wherein the method of self-assembling the first block copolymer 70 is preferably heating. For example, during heating, the hydrophobic portion (e.g., PS) and the hydrophilic portion (e.g., PMMA) begin to self-assemble to form a first guided self-assembly, the hydrophobic portion (e.g., PS) will preferentially approach the hydrophobic patterned first photoresist layer 60, and the hydrophilic portion (e.g., PMMA) will be between the hydrophobic portion (e.g., PS), resulting in a first guided self-assembly hydrophobic portion 701 and a first guided self-assembly hydrophilic portion 702.
Referring to fig. 3d, in step S14, a portion of the structures in the first guided self-assembly are removed to form the patterned first guided self-assembly. The removing method can be ultraviolet exposure or etching, preferably selective etching, further preferably dry etching, and the etching gas is preferably O2, namely, the selective etching using O2 removes part of the structure in the first guided self-assembly. And the partial structure in the first guided self-assembly is referred to as the first guided self-assembly hydrophilic part 702. Namely, the first oriented self-assembly hydrophilic part 702 is removed by selective etching, and the first oriented self-assembly hydrophobic part 701 is remained, so as to form the patterned first oriented self-assembly. The dimension of the patterned first guided self-assembly can reach a resolution of tens of nanometers, and the dimension of the line width (the first guided self-assembly hydrophobic part 701, such as PS) can also reach a resolution of tens of nanometers, the dimension of the line width can be adjusted according to the requirement of the dimension of the nanowire, the minimum dimension of the line width used in the embodiment is 30nm, and the dimension and the line width of the trench in the patterned first guided self-assembly can be 1:1 or not 1: 1.
Referring to fig. 4a and 4b, in step S2, first, using the patterned first guided self-assembly as a mask, etching the first hard mask layer 50 to form a patterned first hard mask layer 501, where the patterned first hard mask layer 501 has a first trench; then, a material difference may be deposited on the patterned first hard mask layer 501 and the surface of the first trench by a chemical vapor deposition, a sputtering deposition, or the likeMasking material on the first hard mask layer until the deposited material fills each first trench; next, the filled material is planarized by a chemical mechanical polishing process or the like to the upper surface of the patterned first mask layer 501 to form a second hard mask layer 80 filled in each first trench (see fig. 5a and 5 b). Transferring the patterned first oriented self-assembly pattern onto the first hard mask 50 by etching, and filling a second hard mask layer 80 with a material different from that of the first hard mask layer 50 into the first trench, wherein the material of the second hard mask layer 80 is preferably SiO2Preparation is made for growing the patterned second guided self-assembly. At this time, the first hard mask layer 50 and the second hard mask layer 80 are both long.
Referring to fig. 6a to 6d, in step S3, a third hard mask layer 90 and a patterned second guided self-assembly are formed over the first hard mask layer 50 and the second hard mask layer 80, wherein the second guided self-assembly pattern and the first guided self-assembly pattern overlap each other, and the material of the third hard mask layer 90 is different from that of the first hard mask layer 50 and the second hard mask layer 80. The third hard mask layer 90 is preferably an Advanced Patterning Film (APF), and is a material having a selective etching ratio with respect to the materials of the first hard mask layer 50 and the second hard mask layer 80, and the forming method is preferably chemical vapor deposition. A patterned second guided self-assembly is then formed on the upper surface of the third hard mask layer 90. The forming method of the patterned second guided self-assembly comprises the following steps:
step S31: forming a second photoresist layer on the third hard mask layer 90;
step S32: photoetching the second photoresist layer to form a patterned second photoresist layer 61, wherein the patterned second photoresist layer 61 is provided with a third groove;
step S33: filling a second block copolymer 71 in the third trench, and allowing the second block copolymer 71 to self-assemble to form a second directed self-assembly having at least two structures;
step S34: removing part of the structure in the second guided self-assembly to form the patterned second guided self-assembly.
Referring to fig. 6a, first, in step S31, a photoresist layer is coated on the third hard mask layer 90 to form a second photoresist layer; next, in step S32, the second photoresist layer is subjected to photolithography to form a patterned second photoresist layer 61 having a third trench, wherein the photolithography may be performed by using a photolithography machine such as I-line, KrF or ArF according to the size requirement of the third trench. The size of the third trench may range from tens of nanometers to several micrometers, and may be the same as or different from the size of the second trench.
Referring to fig. 6b and 6c, in step S33, the third grooves are filled with a second block copolymer 71, and the second block copolymer 71 may include a hydrophobic portion and a hydrophilic portion, such as PS-b-PMMA, which may be the same as or different from the first block copolymer 70. While the method of enabling the second block copolymer 71 to self-assemble is preferably heating, for example, during heating, the hydrophilic portion and the hydrophobic portion start to self-assemble to form a second directed self-assembly, the hydrophobic portion will be preferentially adjacent to the hydrophobic patterned second photoresist layer 61, and the hydrophilic portion is between the hydrophobic portions, finally forming a second directed self-assembly having at least two structures, for example, a second directed self-assembly hydrophobic portion 711 and a second directed self-assembly hydrophilic portion 712.
Referring to fig. 6d, in step S34, a portion of the structure in the second guided self-assembly is removed to form the patterned second guided self-assembly. The removal method may be ultraviolet exposure or etching, preferably selective etching. And the partial structure in the second guided self-assembly refers to the second guided self-assembly hydrophilic part 712, that is, the second guided self-assembly hydrophilic part 712 is removed by selective etching, and the second guided self-assembly hydrophobic part 711 is remained to form a patterned second guided self-assembly. The dimension of the patterned second guided self-assembly can reach a resolution of tens of nanometers, and the dimension of the line width (the second guided self-assembly hydrophobic part 711, such as PS) can also reach a resolution of tens of nanometers, the dimension of the line width can be adjusted according to the requirement of the dimension of the nanowire, the minimum dimension of the line width used in the embodiment is 30nm, and the dimension and the line width of the trench in the patterned second guided self-assembly can be 1:1 or not 1: 1. The second guided self-assembly pattern and the first guided self-assembly pattern are overlapped, namely, a certain angle exists between the patterned second guided self-assembly and the patterned first guided self-assembly, the angle ranges from 0 degrees to 90 degrees and is not 0 degrees, and is preferably 90 degrees, namely the patterned second guided self-assembly pattern and the patterned first guided self-assembly pattern are preferably perpendicular to each other. The period and line size (line width) of the patterned second guided self-assembly pattern and the patterned first guided self-assembly pattern may be the same or may be the same, that is, the period and line size of the two patterns may be the same or may be the same.
Referring to fig. 7a and 7b, in step S4, the third hard mask layer 90 is etched using the patterned second guided self-assembly as a mask to form a patterned third hard mask layer 901, i.e., the patterned second guided self-assembly pattern is transferred onto the third hard mask layer 90 by etching. Referring to fig. 8, the second hard mask layer 80 and the patterned first hard mask layer 501 are etched using the patterned third hard mask layer 901 as a mask to pattern the second hard mask layer and the patterned first hard mask layer again, that is, to form a second patterned first hard mask layer 502 and a patterned second hard mask layer 801, where the second patterned first hard mask layer 502 and the patterned second hard mask layer 801 are both cut off from the strip structure at multiple positions to form an island-shaped structure. The material of the second patterned first hard mask layer 502 is preferably SiN, and the material of the second hard mask layer 80 is preferably SiO2(silicon oxide), the third hard mask layer 90 is preferably APF, since SiN and SiO2The selection ratio of the relative APF can be tuned to be uniform, so that the pattern on the third hard mask layer 90 can be transferred to the patterned first and second hard mask layers 501 and 80 by etching, again because of the stop layer40, the etching process does not affect the semiconductor layer 30.
Referring to fig. 9, in step S5, the third hard mask layer 90 is removed, and the second hard mask layer 80 or the first hard mask layer 50 is removed to form a mask pattern layer. The removing method is preferably wet etching, and only the second patterned hard mask layer 502 or the patterned second hard mask layer 801 remains after etching.
Referring to fig. 10, in step S6, the semiconductor layer 30 and the catalyst layer 20 are etched using the mask pattern layer as a mask to form an island-shaped structure. The etching is preferably dry etching, and an etching gas, such as Cl, is selected using a selection ratio among the mask pattern layer, the semiconductor layer 30, and the catalyst layer 202. That is, the pattern of the mask pattern layer is transferred onto the semiconductor layer 30 and the catalyst layer 20 by etching, and finally island-shaped structures, i.e., the semiconductor islands 301+ the catalyst islands 201, are formed. The island-shaped structures are periodically arranged small islands with uniform size, namely a periodic island-shaped structure array is formed. The periodic island structure array can be a square periodic array, a hexagonal periodic array or any array in between.
Referring to fig. 11a to 11c, in step S7, the island-shaped structure is annealed so that the catalyst layer in the island-shaped structure can catalyze the semiconductor layer in the island-shaped structure to form a nanowire. Namely, the island-shaped structure is annealed at high temperature to form the semiconductor nanowire. The annealing temperature range is 1000-1200 ℃, the annealing process is carried out in the environment of nitrogen and/or inert gas, and the inert gas comprises helium or argon and the like. In the annealing process, the catalyst layer in the island-shaped structure and the semiconductor layer positioned right above the catalyst layer are mutually dissolved to form a semiconductor compound rich in catalyst, and the semiconductor compound rich in catalyst is continuously annealed to generate semiconductor nanowires (30 nm-100 nm) which are periodically arranged and have uniform size, wherein the catalyst 3013 is arranged at the top end of each nanowire, the nanowire shell 3012 is non-luminous oxide, and the nanowire core 3011 is a luminous semiconductor nanocrystal (<5 nm). If the material of the semiconductor layer is amorphous Si, the catalytic process is more efficient because the grown amorphous Si is less dense than the substrate and is located right above the catalyst. And the size formed by the first guided self-assembly and the second guided self-assembly can reach the resolution of tens of nanometers, namely compared with the traditional process, the guided self-assembly of the invention can form smaller size at one time, thereby forming smaller catalyst islands 201 and finally catalyzing and generating thinner nanowires.
The island structures formed in the present invention are uniform in size, i.e., the catalyst islands 201 in the island structures are uniform in size, so that the amount of catalyst contained in each of the island structures is substantially the same, and thus the size of the catalyst-rich semiconductor compound formed during the annealing process is uniform. Since the size of the catalyst-rich semiconductor compound formed is critical to affect the thickness of the semiconductor nanowire, the larger the size of the catalyst-rich semiconductor compound, the thicker the semiconductor nanowire formed, whereas in the present invention, the size of the catalyst-rich semiconductor compound formed is uniform, and thus, the thickness of the semiconductor nanowire finally formed is also uniform. And because the island-shaped structures are arranged periodically, the finally formed semiconductor nanowires are also arranged periodically, namely the semiconductor nanowires with uniform thickness and ordered arrangement are finally formed.
Therefore, the method for forming the semiconductor nanowires provided by the invention is used for preparing the island-shaped structures which are periodically arranged and have uniform sizes by a guided self-assembly process and corresponding photoetching and etching processes, and catalyzing the semiconductor layer positioned above the catalyst layer at high temperature to form the semiconductor nanowires with uniform thickness and orderly arrangement.
Finally, it should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. That is, all equivalent changes and modifications made according to the content of the claims of the present invention should be within the technical scope of the present invention.
Claims (10)
1. A method of forming a semiconductor nanowire, comprising the steps of:
step S1: providing a substrate, and sequentially forming a catalyst layer, a semiconductor layer, a first hard mask layer and a patterned first guide self-assembly on the substrate;
step S2: etching the first hard mask layer by taking the patterned first guide self-assembly as a mask to form a patterned first hard mask layer, wherein the patterned first hard mask layer is provided with a first groove, and a second hard mask layer with the material different from that of the first hard mask layer is filled in the first groove;
step S3: sequentially forming a third hard mask layer and a patterned second oriented self-assembly above the first hard mask layer and the second hard mask layer, wherein the second oriented self-assembly pattern and the first oriented self-assembly pattern are overlapped, and the material of the third hard mask layer is different from that of the first hard mask layer and the second hard mask layer;
step S4: etching the third hard mask layer by taking the graphical second oriented self-assembly as a mask to form a graphical third hard mask layer, and etching the second hard mask layer and the first hard mask layer by taking the graphical third hard mask layer as a mask to graph the second hard mask layer and the first hard mask layer again;
step S5: removing the third hard mask layer, and removing the second hard mask layer or the first hard mask layer to form a mask patterning layer;
step S6: etching the semiconductor layer and the catalyst layer by taking the mask pattern layer as a mask to form an island-shaped structure;
step S7: and annealing the island structures so that the catalyst layers in the island structures can catalyze the semiconductor layers in the island structures to form the nanowires.
2. The method of forming a semiconductor nanowire of claim 1, wherein forming the patterned first guided self-assembly on the first hardmask layer comprises:
step S11: forming a first photoresist layer on the first hard mask layer;
step S12: photoetching the first photoresist layer to form a patterned first photoresist layer, wherein the patterned first photoresist layer is provided with a second groove;
step S13: filling a first block copolymer in the second groove, and enabling the first block copolymer to carry out self-assembly so as to form a first oriented self-assembly with at least two structures;
step S14: removing part of the structure in the first guided self-assembly to form the patterned first guided self-assembly.
3. The method of forming a semiconductor nanowire of claim 1, wherein forming the patterned second guided self-assembly on the third hardmask layer comprises:
step S31: forming a second photoresist layer on the third hard mask layer;
step S32: photoetching the second photoresist layer to form a patterned second photoresist layer, wherein the patterned second photoresist layer is provided with a third groove;
step S33: filling a second block copolymer in the third groove, and enabling the second block copolymer to carry out self-assembly so as to form second oriented self-assembly with at least two structures;
step S34: removing part of the structure in the second guided self-assembly to form the patterned second guided self-assembly.
4. The method of forming a semiconductor nanowire of claim 1, wherein an angle exists between the patterned first guided self-assembly and the patterned second guided self-assembly pattern, the angle ranging from: 0 to 90 degrees and not 0 degrees.
5. The method of claim 2 or 3, wherein the tool for forming the patterned first photoresist layer and the patterned second photoresist layer comprises a KrF, ArF, or I-line lithography machine.
6. The method for forming a semiconductor nanowire according to claim 1, wherein nitrogen gas and/or inert gas is introduced during growth of the semiconductor layer on the catalyst layer to prevent oxidation.
7. The method for forming a semiconductor nanowire according to claim 1, wherein a stopper layer is further formed between the semiconductor layer and the first hard mask layer.
8. The method of forming a semiconductor nanowire of claim 1, wherein the island-like structures are periodically arranged and have a uniform size.
9. The method for forming a semiconductor nanowire according to claim 1, wherein in step S7, the annealing temperature is 1000 ℃ to 1200 ℃, and the annealing process is performed in a nitrogen and/or inert gas atmosphere.
10. The method of forming a semiconductor nanowire of claim 1, wherein a material of the catalyst layer is at least one of Au, Ni, Co, Ti, In, and Fe.
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| US20070020950A1 (en) * | 2005-02-25 | 2007-01-25 | Byoung-Lyong Choi | Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires |
| US20120129357A1 (en) * | 2008-01-22 | 2012-05-24 | International Business Machines Corporation | Two-dimensional patterning employing self-assembled material |
| CN105239156A (en) * | 2015-09-15 | 2016-01-13 | 南京大学 | Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration |
| US20160027681A1 (en) * | 2014-07-23 | 2016-01-28 | Seagate Technology Llc | Hard-mask defined bit pattern substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20070020950A1 (en) * | 2005-02-25 | 2007-01-25 | Byoung-Lyong Choi | Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires |
| US20120129357A1 (en) * | 2008-01-22 | 2012-05-24 | International Business Machines Corporation | Two-dimensional patterning employing self-assembled material |
| US20160027681A1 (en) * | 2014-07-23 | 2016-01-28 | Seagate Technology Llc | Hard-mask defined bit pattern substrate |
| CN105239156A (en) * | 2015-09-15 | 2016-01-13 | 南京大学 | Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration |
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