CN110993565A - Method for preparing semiconductor nano device structure by directional self-assembly - Google Patents

Method for preparing semiconductor nano device structure by directional self-assembly Download PDF

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CN110993565A
CN110993565A CN201911267633.8A CN201911267633A CN110993565A CN 110993565 A CN110993565 A CN 110993565A CN 201911267633 A CN201911267633 A CN 201911267633A CN 110993565 A CN110993565 A CN 110993565A
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layer
pattern
assembly
mandrel
semiconductor
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孟令款
李可为
周波
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Chengdu Technological University CDTU
Chengdu Univeristy of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask

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Abstract

The invention discloses a method for preparing a semiconductor nano device structure by directed self-assembly, which comprises the steps of forming a hard mask layer, a mandrel layer, a photoetching stack layer and a buffer layer on a semiconductor substrate, forming a guide pattern on the surface of the buffer layer, and then annealing a spin-coated Block Copolymer (BCP) to form a directed self-assembly (DSA) pattern. And then transferring the DSA pattern to the buffer layer, the photoetching stack layer and the mandrel layer in sequence, and further carrying out micro-reduction and patterning on the self-assembly pattern by combining a self-aligned side wall transfer technology, thereby forming a semiconductor nano device structure pattern on the semiconductor substrate. The invention combines the directional self-assembly pattern transfer technology with the self-alignment side wall transfer technology, the technical scheme is compatible with the current integrated circuit manufacturing process, the geometric pattern with the size of below 10nm and high density can be realized through size reduction, and the invention also provides more space for the geometric size regulation of the semiconductor structure, namely the final characteristic size can be further reduced.

Description

Method for preparing semiconductor nano device structure by directional self-assembly
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for preparing a semiconductor nano device structure by utilizing block copolymer directed self-assembly (DSA) and self-aligned sidewall transfer technology (SADP).
Background
Over fifty years, various technologies have been continuously developed to drive the semiconductor industry forward, and despite many challenges, moore's law has been maintained for the history of continuous innovation. As it becomes increasingly difficult to improve the performance of CMOS devices by continuous scaling, other methods for improving device performance, in addition to scaling, become critical.
Currently, the use of non-planar semiconductor devices, such as semiconductor fin field effect transistors (finfets), has pushed CMOS devices forward from the 22nm technology node. With the further development of the technology, in the coming years, the stacked wrap gate nanowire device may be widely used to replace the FinFET device at the 3nm or 2nm technology node. The fabrication process is mostly compatible with FinFET devices, especially Fin formation.
Advanced technology nodes require high density of semiconductor fins and precise customization capabilities. The advent of new integrated circuits in each generation, through which lithography is one of the core fabrication technologies supporting the above-mentioned generations of integrated circuit devices, is always marked by the main technical hallmarks of achieving smaller feature sizes with lithography processes. The 193nm immersion lithography technology used in the industry has been extended to the 14nm, 10nm, and even to 7nm node in combination with double (multiple) pattern exposure (SADP) technology. Currently, more advanced but very expensive EUV lithography techniques are also beginning to be applied at the 7nm node. However, the extremely high process development cost, process complexity and physical limitations of photolithography restrict the further development of the existing photolithography technology, and particularly, there is a great limitation in the process of manufacturing patterns with smaller sizes, and there is a great need in the industry for a solution that can achieve both precision and cost.
Directed Self-assembly (DSA) is a Bottom-up (Bottom-up) nanopattern processing technology with great potential. Regular nanostructures can be formed on highly ordered two-dimensional thin films by DSA techniques using Block Copolymer (BCP) materials, which are difficult to pattern at this scale with conventional optical exposure techniques. Therefore, the DSA technology is used for replacing the traditional optical exposure technology to process the micro-nano electronic device, has the advantages of low cost, high graphic resolution, low edge roughness and the like, has unique advantages in the aspects of large-area regular pattern manufacturing and through hole manufacturing, and has attracted extensive attention in recent years.
However, it is expected that the selection of high resolution block copolymers alone using directed self-assembly (DSA) techniques to achieve patterns with dimensions below 20nm will face many technical challenges in etching, since it is difficult to achieve high etch selectivity between different blocks, which makes it difficult to obtain higher quality lithographic patterns and pattern quality, which in turn affects the geometry and topography control of the patterns, and the line roughness faces serious challenges.
In view of the foregoing, there is a need for a method of fabricating a high density semiconductor structure that provides high reliability and uniformity, and overcomes the process control problems caused by the prior art directed self-assembly pattern transfer and size reduction processes. The method of the present invention may then be used to obtain satisfactory semiconductor nanostructures, such as arrays of Fin in FinFET devices and arrays of Nanofire in Gate Nanowire (GAA Nanofire) devices, in semiconductor substrates, or other more advanced electronic devices or structures, as desired.
Disclosure of Invention
The invention provides a method for preparing a semiconductor nano device structure by directional self-assembly, which specifically comprises the following steps:
a method for preparing a semiconductor nano device structure by adopting directional self-assembly is characterized by comprising the following steps:
providing a semiconductor substrate, and sequentially forming a mandrel layer and a photoetching stacking layer on the semiconductor substrate, wherein a plurality of guide structure patterns are formed in the photoetching stacking layer;
depositing a Block Copolymer (BCP) layer between the guide structure patterns, annealing to form a directional self-assembly pattern consisting of a plurality of phase-separated polymer blocks, and filling the whole area between the guide structures with the phase-separated different polymer blocks and periodically repeating;
selectively removing the polymer block region, using the rest polymer block region as an etching mask, sequentially transferring the etching mask pattern to the photoetching stack layer and the mandrel layer, and removing the photoetching stack layer pattern to obtain an etched mandrel layer pattern;
depositing a side wall dielectric layer on the mandrel layer pattern, and then removing the dielectric layer on the horizontal part of the mandrel layer, and reserving the dielectric layer on the side wall of the mandrel layer pattern;
and further removing the mandrel layer material, and then defining the semiconductor substrate by using the reserved side wall dielectric layer as a mask to form a semiconductor nano-structure pattern.
Preferably, the guide structure pattern is formed by hardened photoresist or by hard mask through photolithography and etching.
Preferably, the self-assembled pattern is formed of a diblock copolymer, a triblock copolymer, or other multiblock copolymer, wherein the widths of the polymer block regions formed may be the same or different.
Preferably, a hard mask layer is deposited between the semiconductor substrate and the mandrel layer, the sidewall dielectric layer pattern is transferred to the hard mask layer, and then the semiconductor substrate is defined by a double-layer mask.
Preferably, a buffer layer is disposed between the lithographic stack layer and a Block Copolymer (BCP) layer, and the pattern forming the block copolymer layer is transferred to the buffer layer and then to the lithographic stack layer and the mandrel layer.
Preferably, a neutral material layer is provided on the surface of the buffer layer, and the neutral material layer is in direct contact with or not in contact with the side wall of the guide structure pattern.
Preferably, a block copolymer may be directly deposited on the surface of the buffer layer without using a neutral material layer, wherein the material of the block copolymer layer is selected from Polystyrene-Polycarbonate (PS-b-PC).
Preferably, the buffer layer material is selected from polysilicon or amorphous silicon, and is obtained by etching with halogen-based, fluorine-based and fluorocarbon-based gases by using a certain copolymer block as a mask, wherein the etching gas is preferably Cl2HBr or SF6、CH2F2。
Preferably, the photolithography stack layer comprises an Optical Planarization (OPL) layer and an anti-reflective coating (ARC) layer or a stack of an Optical Planarization (OPL) layer and an insulating dielectric layer or a single insulating dielectric layer, wherein the Optical Planarization Layer (OPL) is preferably inorganic amorphous carbon or spin-on carbon or diamond-like carbon, the anti-reflective coating (ARC) layer is preferably a silicon-containing anti-reflective coating material, and the insulating dielectric layer is preferably silicon oxide, silicon nitride or silicon oxynitride.
Preferably, the mandrel layer and the hard mask layer are silicon-based dielectric materials or metal compound materials, the materials of the two materials can be the same or different, preferably, the silicon-based dielectric materials are selected from silicon oxide, silicon nitride, polycrystalline silicon and amorphous silicon, and the metal compound materials are selected from aluminum oxide, titanium oxide and titanium nitride.
Preferably, the mandrel pattern may be shrunk and then the sidewall dielectric layer may be deposited to control the feature size of the geometric pattern.
The invention combines the directional self-assembly pattern transfer technology and the self-aligned side wall transfer technology, can realize the geometric pattern with the size of less than 10nm and high density, does not need to introduce complicated and lengthy process, can be compatible with the current integrated circuit manufacturing process, and is very easy to realize large-scale production.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing the method for fabricating a semiconductor nano-device structure by directed self-assembly thereof with reference to the accompanying drawings, in which:
FIG. 1 is a self-assembling template pattern.
Fig. 2 selectively removes a certain block pattern.
The photolithographic pattern of fig. 3 is transferred onto the buffer layer.
Fig. 4 etches the anti-reflective ARC layer.
Fig. 5 anti-reflective ARC layer scaling.
Figure 6 etch photo planarizes the OPL layer.
Fig. 7 forms a mandrel (mandrel) pattern.
Fig. 8 removes the masking layer.
Figure 9 grows the sidewall dielectric layer.
Fig. 10 etches the sidewalls.
Fig. 11 removes the mandrel (mandrel).
FIG. 12 etches the hard mask layer and the semiconductor structure.
FIG. 13 removes the mask to form the semiconductor structure.
Detailed Description
The following definitions and abbreviations are used for the interpretation of the claims and the specification. As used herein, the terms "comprising," "including," "containing," "having," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements, articles, or apparatus not expressly listed or inherent to such composition, mixture, process, method, or apparatus.
As used herein, the articles "a" and "an" preceding an element or component are intended to be non-limiting with respect to the number of instances (i.e., occurrences) of the element or component. Thus, "a" or "an" should be understood to include one or at least one, and the singular form of an element or component also includes the plural unless the number clearly is the singular. The present application will now be described in more detail by reference to the following discussion and the accompanying drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application. The present invention will be described in further detail with reference to the accompanying drawings and examples.
The invention provides a method for preparing a high-density semiconductor nano device structure with high reliability, which can greatly overcome the process control problem caused by the thickness of a block copolymer and the weaker etching selectivity among different block molecules in the existing self-assembly pattern transfer process.
Specifically, the method comprises the following steps:
fig. 1 illustrates a cross-sectional view of a semiconductor stack formed by a directed self-assembly (DSA) technique. First, a semiconductor substrate 1 is provided, on which a hard mask layer 2, a mandrel (mandrel) layer 3, a photolithography stack layer 4, and a buffer layer 5 are sequentially formed. Wherein the buffer layer 5 is primarily to form a transition between the photolithographically stacked layer 4 and the block copolymer layer to facilitate patterning of the block copolymer, it should be noted that this buffer layer 5 is only preferred and in another embodiment the buffer layer 5 may not be employed and the block copolymer layer is formed directly on the photolithographically stacked layer 5. Also, while the hard mask layer between the semiconductor substrate 1 and the mandrel layer can be re-etched to form a pattern to protect the semiconductor substrate 1 to obtain a finer pattern, the hard mask layer 2 is also preferred, and in another embodiment, the mandrel layer may be formed directly on the semiconductor substrate layer 2 without using the hard mask layer 2. In the following discussion of the embodiments, the hard mask layer 2 and the buffer layer 5 are included, unless otherwise specifically mentioned, in order to fully illustrate the concept of the present invention.
The semiconductor substrate 1 may be composed of any semiconductor material including, but not limited to, Si, Ge, SiGe, SiC, SiGeC, carbon nanotubes, and III/V compound semiconductors such as InAs, GaN, GaAs, and InP. Multilayer materials composed of these semiconductor materials may also be used as the semiconductor substrate. The semiconductor substrate 1 may be composed of a single crystal semiconductor material, and single crystal silicon is selected as the semiconductor substrate 1 in the present embodiment. In other embodiments, the semiconductor substrate may be a polycrystalline or amorphous semiconductor material. The method of the present application can then be used to obtain satisfactory semiconductor nanostructures, such as arrays of Fin in FinFET devices and arrays of Nanofire in Gate Nanowire (GAA) devices, in semiconductor substrates, as desired.
In another embodiment, the semiconductor substrate 1 may comprise a semiconductor-on-insulator (SOI) substrate (not specifically shown). Although not specifically shown, those skilled in the art understand that the SOI substrate includes a support substrate, an insulator layer on the surface of the support substrate, and a semiconductor layer on the topmost of the upper surface of the insulator layer. The support substrate provides mechanical support for the insulator layer and the topmost semiconductor layer. In such an embodiment, a semiconductor structure such as a Fin array in a FinFET can then be fabricated into the topmost semiconductor layer of the SOI substrate using the method of the present invention. In this embodiment, the Fin array is formed on the topmost surface of the insulator layer.
The support substrate and the uppermost semiconductor layer of the SOI substrate may comprise the same or different semiconductor materials. In one embodiment, the support substrate and the topmost semiconductor layer are both comprised of silicon. In some embodiments, the support substrate is a non-semiconductor material, including, for example, a dielectric material and/or a conductive material.
In some embodiments, the topmost semiconductor layers of the support substrate and the SOI substrate may have the same or different crystal orientations. For example, the crystal orientation of the supporting substrate and/or the semiconductor layer may be 100, 110, or 111. Other crystallographic orientations than those specifically mentioned may also be used in the present invention. The substrate and/or the top semiconductor layer of the SOI substrate may be a single crystalline semiconductor material, a polycrystalline material, or an amorphous material. Typically, at least the topmost semiconductor layer is a single crystal semiconductor material. In some embodiments, the topmost semiconductor layer, which is located on top of the insulator layer, may be processed to include semiconductor regions having different crystal orientations.
The insulator layer of the SOI substrate may be a crystalline or amorphous oxide or nitride. In some embodiments, the insulator layer is an oxide, such as silicon dioxide. The insulator layer may be continuous or discontinuous. When discontinuous insulator regions are present, the insulator regions may exist as isolated islands surrounded by semiconductor material.
In one example, the thickness of the topmost semiconductor layer of the SOI substrate may be 5nm to 50 nm. In some embodiments, and when an ETSOI (ultra-thin semiconductor on insulator) substrate is used, the semiconductor layer of the topmost layer of the SOI has a thickness of less than 10 nm. If the thickness of the uppermost semiconductor layer is not within one of the above ranges, a thinning technique such as CMP planarization or etching may be used to reduce the thickness of the uppermost semiconductor layer to within the range. The insulator layer of the above-mentioned SOI substrate generally has a thickness of 10nm to 200nm, and more typically has a thickness of 100nm to 150 nm. The thickness of the support substrate of the SOI substrate is not relevant to the present invention.
The hard mask layer 2 comprises a conventional silicon-based dielectric material such as silicon oxide, silicon nitride, or a metal oxide such as HfO2、ZrO2、La2O3、Al2O3、TiO2Etc., HfO is used in the present embodiment2As a hard mask layer. In some embodiments, the hard mask layer may also be comprised of nitrogen-doped silicon carbide, a nitrogen-doped hydrogenated silicon carbide layer, or a carbon-doped silicon oxide. Nitrogen-doped silicon carbide is a compound of silicon, carbon and nitrogen, for example denoted SiCN, nitrogen-doped hydrogenated silicon carbide is a compound of silicon, carbon, nitrogen and hydrogen, for example denoted SiCNH, and carbon-doped silicon oxide is a compound of silicon, carbon, oxygen, for example denoted SiCO.
The mandrel (mandrel) layer 3 on the surface of the hard mask layer 2 may be composed of silicon oxide, silicon nitride, amorphous silicon, polycrystalline silicon, amorphous or polycrystalline germanium, amorphous or polycrystalline-germanium alloy material, amorphous carbon, diamond-like carbon, organosilicate glass, or the like. In some embodiments, the mandrel (mandrel) layer 3 may be composed of a metal, such as Al, W or Cu, as well asMay consist of metal compounds such as Al2O3And TiN, etc.
The hardmask layer 2 and mandrel (mangrel) layer 3 are typically different dielectric materials and may be formed by methods suitable in the art, including Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), or any combination thereof.
After the sidewall is deposited on the mandrel (mandrel) layer 3, an anisotropic etching method is needed to remove the sidewall material deposited on the horizontal surface, and the sidewall is required to have higher etching selectivity to the mandrel layer and the hard mask layer.
The lithographic stack 4 comprises a stack of an Optical Planarization (OPL) layer 4' and an anti-reflective coating (ARC) layer 4 ", which may also be composed of an OPL layer and a silicon-based insulating dielectric layer to enable high fidelity pattern transfer to the underlying mandrel layer, ensuring good topography control. The Optical Planarization (OPL) layer may be inorganic amorphous carbon, or may be an organic material such as spin-on carbon or diamond-like carbon, which provides a smooth and flat surface for the underlying structure. In one embodiment, the Optical Planarization (OPL) layer may be formed by spin coating, (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), evaporation, or chemical solution deposition. The thickness of the OPL is generally selected according to the particular etch dimensions, with the current trend being to use smaller and smaller thicknesses, e.g. 10nm to 100 nm.
The silicon-based insulating dielectric layer may be silicon oxide, silicon nitride or silicon oxynitride, and may be formed by spin coating, (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), high density plasma chemical vapor deposition (HPCVD), chemical solution deposition, Atomic Layer Deposition (ALD), or the like.
The anti-reflective coating (ARC) comprises a silicon-containing anti-reflective coating material, in this embodiment a silicon anti-reflective coating (SiARC) is used, which minimizes light reflection during photolithography. The anti-reflective coating (ARC)4 "may be formed by spin coating, Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), Plasma Enhanced (PEALD), evaporation, or chemical solution deposition. The silicon antireflection layer can also be replaced by a silicon-based insulating dielectric layer such as silicon oxide, silicon nitride or silicon oxynitride.
A buffer layer 5 is deposited on the lithographic stack 4, the buffer layer 5 being amorphous silicon or polysilicon. Then, on the surface thereof, a pattern of confining or inducing guide structures may be formed according to a predetermined design using Graphoepitaxy (Graphoepitaxy directed self-assembly) or Chemoepitaxy (Chemoepitaxy) or other suitable methods. The guide structure pattern may have a surface topography, or be substantially free of a surface topography, may be formed from hardened photoresist or may employ lithographic and etching techniques to form the chemical guide pattern. The DSA technique for forming a block copolymer is not particularly limited in the present invention. By changing the chain length, composition, annealing condition and the like of the block copolymer, the block copolymer can be directionally self-assembled in a film, a hole or a groove, and different block copolymer layer patterns such as spheres, columns, layers and the like can be formed. The pattern of the block copolymer layer is not particularly limited in the present invention.
In one embodiment, before forming the self-assembled template pattern using the Block Copolymer (BCP), it is generally necessary to form a layer of neutral material (not shown) on the surface of the buffer layer 5, which may or may not directly contact the sidewalls of the guide pattern. The neutral material layer may be formed after the formation of the guide structure or before the formation of the guide structure, and the present invention is not particularly limited thereto. In some other embodiments, however, some BCP materials, such as Polystyrene-Polycarbonate (PS-b-PC), may form an oriented self-assembled pattern perpendicular to the bottom surface in the guide structure without using a neutral layer material, depending on the material and process characteristics of the particular block polymer.
The layer of neutral material is a polymer layer that can adhere to the underlying surface and acquire a certain surface energy, typically a random copolymer containing a polar polymer component and a non-polar polymer component, including materials that are chemically neutral to the different polymer blocks in the block copolymer material used for DSA, i.e., the neutral materials have substantially the same wetting affinity for the different polymer blocks in the block copolymer material, thus facilitating the formation of polymer blocks oriented perpendicular to the upper surface of the layer of neutral material. "random" refers to a polymeric material that lacks any defined repeating blocks. In one example, the neutral material may comprise a random copolymer of Polymethylmethacrylate (PMMA) as a component of the polar polymer and Polystyrene (PS) as a component of the non-polar polymer. By controlling the ratio of the non-polar polymer component (i.e., PS) to the polar polymer component (i.e., PMMA) during the synthesis phase, the desired surface properties can be achieved. In some embodiments, to anchor the random copolymer on the surface of buffer layer 5, one or several functional groups may be added to the ends of the polymer chains or in random positions of the polymer chains to react with the buffer layer and establish covalent bonds. The neutral material layer may be formed by spin coating, evaporation or chemical solution deposition, and may be 2nm to 20nm thick, or even smaller thicknesses may be used.
In one embodiment, the neutral material layer may be made of a polymer brush material having ends substituted with reactive functional groups capable of attaching to the surface of buffer layer 5, which is a random copolymer having ends of a block copolymer material substituted with reactive functional groups. Exemplary polymeric brush materials for use in the present invention are random copolymers comprised of block copolymer materials having reactive groups such as hydroxyl, amino, halogen groups, and the like. These reactive groups can react with the hydroxylated groups present on the surface of the buffer layer. In one embodiment, when the block copolymer for DSA is a diblock copolymer of Polystyrene (PS) and Polymethylmethacrylate (PMMA), the neutral material layer may be PS-r-PMMA-OH consisting of styrene and random methyl acrylate having hydroxyl groups. The hydroxyl groups at the ends of the polymer chains will be covalently bonded to the hydroxyl groups on the surface of buffer layer 5 by a condensation reaction. Because there is only one reactive functional group per polymer chain, the reaction will be self-limiting, and only one monolayer of polymer brush material will be anchored on the surface of buffer layer 5, the unreacted polymer brush material remaining soluble in the solvent.
To form the layer of neutral material, a polymer brush material may be spin coated into the guide structure and onto the surface of the buffer layer 5. The polymer brush material is baked at a suitable temperature to activate the reaction between the polymer and the functional groups on the surface of buffer layer 5, and then excess polymer brush material not bound to the surface of buffer layer 5 is removed using a neutral solvent that does not significantly affect the neutral material layer. Of course, depending on the polymeric material used, the solvent used to remove excess polymeric brush material may vary, and suitable solvents include, but are not limited to, Propylene Glycol Monomethyl Ether Acetate (PGMEA), n-butyl acetate (nBA), toluene, and anisole.
To form the nanoscale periodic pattern, the block copolymer material is first dissolved in a suitable solvent to form a block copolymer solution, which is then applied over the layer of neutral material and between the guide patterns to provide a layer of block copolymer. The solvent system used to dissolve the block copolymer material and form the block copolymer solution may comprise any suitable solvent, including, but not limited to, toluene, Propylene Glycol Monomethyl Ether Acetate (PGMEA), Propylene Glycol Monomethyl Ether (PGME), and acetone. The block copolymer solution may be applied by any suitable technique, including but not limited to spin coating, spray coating, and dip coating.
The block copolymer layer includes a first polymer block and a second polymer block that are immiscible with each other. In some embodiments of the invention, the material providing the copolymer layer is self-planarizing. Microphase separation of the different polymer blocks comprised in the block copolymer layer can be achieved by annealing at a temperature to form an alternating periodic pattern with perpendicular orientation on the nanometer scale. By "nanoscale" is meant herein the level of feature sizes less than 50 nm. Exemplary block copolymers that can be used to form nanoscale periodic patterns include, but are not limited to, poly (styrene-b-methyl methacrylate) (PS-b-PMMA), poly (ethylene oxide-b-isoprene) (PEO-b-PI), poly (ethylene oxide-b-methyl methacrylate) (PEO-b-PMMA), poly (ethylene oxide-b-ethyl ethylene) (PEO-b-PEE), poly (styrene-b-vinyl pyridine) (PS-b-PVP), poly (styrene-b-butadiene) (PS-b-PBD), poly (styrene-b-ferrocenyldimethylsilane) (PS-b-PFS), poly (styrene-b-lactic acid) (PS-b-PLA), and poly (styrene-b-dimethylsiloxane) Alkane) (PS-b-PDMS). In one embodiment, PS-b-PMMA is preferably used.
In addition, the block copolymer may be formed of a diblock copolymer, and the block copolymer layer may be formed of a triblock copolymer or other multiblock copolymers according to another embodiment of the present invention, but the present invention is not limited thereto. The diblock copolymer PS-b-PMMA was used in this example to form a block copolymer layer. However, in other embodiments of the present invention, any suitable block copolymer may be used to form the block copolymer layer. In the present embodiment, the block copolymer layer includes a first polymer block 6 composed of a first component PMMA and a second polymer block 7 composed of a second component PS. In one embodiment, the block copolymer layer may be annealed at elevated temperatures by solvent vapor annealing or by thermal annealing to form the first polymer block 6 and the second polymer block 7. The annealing may be performed at a temperature of about 150 ℃ to about 300 ℃ for a duration of 30 seconds to about 5 hours. In other embodiments of the present invention, other annealing conditions (i.e., temperature and time) may also be used to convert the copolymer layer into a self-assembled block copolymer structure. As shown in fig. 1, each first phase separated polymer block 6 and each second phase separated polymer block 7 of each self-assembled block copolymer structure repeat in a regular pattern. Thus, in accordance with the present invention, a certain phase separated polymer block within a self-assembled structure formed of a particular block copolymer can be used to define and fabricate nanowires in a semiconductor Fin or a gate Nanowire device (GAA Nanowire) in a FinFET device, while another phase separated polymer block can be used to define the spacing between each semiconductor Fin or Nanowire in the same self-assembled structure. The specific size is generally determined by the respective chemical nature of the polymer blocks. Each first phase separated polymer block has a first width L1 and each second phase separated polymer block has a second width L2. In some embodiments, the second width L2 is the same as the first width L1. In other embodiments, the second width L2 is different from the first width L1. This allows for the selection of an appropriate block copolymer in defining the final semiconductor nanostructure, depending on the design requirements of the device, so that more control over the results can be achieved. Each of the first and second widths is nano-scale and may be generally less than 50 nm.
As in FIG. 2, O may be used2Ar or fluorocarbon-based gas, O2The first phase separated polymer block 6 is selectively removed by plasma dry etching while the second phase separated polymer block 7 is used as an etching mask to form a directional self-assembled lithographic pattern. The first phase separated polymer block 6 can also be selectively removed using a wet development process (e.g., UV radiation followed by solvent washing) to form a nano-scale lithographic pattern. In the process, the corresponding part of the neutral layer below the first phase-separated polymer block 6 is also removed. In other embodiments, other etching methods may be used to remove the first phase-separated polymer block 6, which is not specifically limited in the present invention. After selective removal of the first polymer blocks 6, the remaining second polymer blocks 7 define the structure of the semiconductor, while the distance between adjacent second polymer blocks defines the pitch of the semiconductor structure. In one embodiment, the first polymer block is PMMA, the second polymer block is PS, and the PMMA is selectively removed using the PS as a mask.
Subsequently, the resist pattern is transferred to the buffer layer 5, and the resist pattern may be obtained using halogen-based, fluorine-based, and fluorocarbon-based gases, preferably Cl2HBr or SF6、CH2F2As shown in fig. 3. The buffer layer may be etched using any suitable etching process, such as a dry etching process, e.g., plasma etching, reactive ion etching, pulsed plasma etching, etc. The present invention is not particularly limited in this regard. By adopting the polycrystalline silicon or amorphous silicon material, the excessive consumption of the block molecules caused by the etching of the conventional mask material can be reduced, so that the high dependence of the block copolymer on the etching technology is reduced, and the better fidelity and integrity can be realized in the pattern transfer process.
Subsequently, the pattern obtained above can be transferred into the photolithographic stack 4 by methods known in the art, as shown in FIG. 4. In this process, each ofAnd carrying out isotropic etching to transversely shrink the obtained pattern to obtain a pattern with a smaller size, so as to avoid transverse expansion of the CD caused by etching morphology. In another embodiment, a fluorocarbon based gas such as CF may be used4、CHF3And O2The hybrid plasma of (a) is used to micro-scale the antireflective coating (ARC). The etched anti-reflective layer is then transferred to an Optical Planarization (OPL) layer, in which process O may be used2Ar or halogen-based gases such as Cl2HBr or fluorocarbon based gases such as CF4And O2The hybrid plasma of (a) micro-shrinks the Optical Planarization (OPL) layer (not shown in the figure) resulting in an etched lithographic stack, as shown in fig. 6. The photolithographically stacked layer 4 is then transferred onto a mandrel layer (mandrel)3, depending on the material used for the mandrel layer, as shown in fig. 7. As one example, a halogen-based, fluorine-based, or fluorocarbon-based gas, preferably Cl, may be generally selected when a polysilicon or amorphous silicon material is employed2HBr or SF6、CH2F2And etching in an ICP etching machine. Any remaining portions of the ARC layer and OPL layer are then removed, resulting in a mandrel layer (mandrel) pattern with steep etch profile and clean-out, as shown in fig. 8. This process may be performed by dry etching, wet etching, or any other suitable etching process. As an example, an oxygen plasma may be used to strip the entire patterned photoresist layer OPL while also completely removing the remaining material above.
As shown in fig. 8, each mandrel layer (mandrel) pattern formed is rectangular in cross-section and typically has a width less than the minimum feature size that can be formed using a particular photolithographic technique, depending on the chemistry of the block copolymer employed. In one embodiment, the width of each mandrel layer (mandrel) is 20nm to 50nm, although smaller widths may be used. The spacing between adjacent mandrel layer (mandrel) patterns may be 30nm to 50nm, or smaller spacings may be used.
As shown in fig. 9, a sidewall dielectric layer 8 is formed by depositing a dielectric material on the surface of the mandrel layer (mandrel) pattern 3, and a pattern with a smaller size is obtained by etching to realize subsequent sidewall transfer. The sidewall spacers are comprised of a dielectric material having a high etch selectivity with respect to both the hard mask layer 2 and the mandrel layer 3. In one embodiment of the present application, the spacer material may be silicon nitride. The material layer may be formed by a conformal deposition process such as CVD, PECVD or ALD, i.e., a deposited film with good step coverage is required, and the thickness thereof may be 5nm to 20nm depending on the size of the finally prepared semiconductor structure, although other thicknesses may be used.
After conformal deposition, the sidewall material deposited on the horizontal surfaces of the hard mask layer 2 and the mandrel layer 3 is completely removed using an anisotropic dry etching technique such as RIE, while the sidewall material deposited on the vertical sidewalls of the mandrel layer 3 is retained, as shown in fig. 10. In the process, the sidewall is required to have higher etching selectivity to the Mandrel layer 3(Mandrel) and the underlying hard mask layer 2, so that the Mandrel layer and the hard mask layer are ensured not to be damaged too much, and the subsequent etching process is not influenced. The etched spacer dielectric layer 8 is used to further etch the underlying hard mask layer 2 to obtain a scaled bilayer mask pattern for defining the final semiconductor structure dimensions.
Subsequently, the Mandrel layer 3(Mandrel) is removed using dry or wet etching techniques, as shown in fig. 11. The whole process requires high selectivity on the materials of the side wall and the lower layer mask layer, and the horizontal and vertical losses are reduced, so that high-precision etching pattern transfer can be realized. After removing the mandrel layer, the hard mask layer 2 is patterned by using the sidewall dielectric layer 8 as a mask, and then the semiconductor substrate 1 is patterned by using the sidewall layer and the hard mask layer as a double-layer mask, as shown in fig. 12.
And finally, removing the double-layer mask consisting of the side wall dielectric layer and the hard mask layer, thereby forming a final semiconductor structure with expected pattern width (Line width: L) and Pitch (Pitch: P), as shown in FIG. 13. The structure may be a Fin array in a FinFET device, a Nanowire array in a gate-all Nanowire (GAA Nanowire) device, or a dummy gate electrode array. In some embodiments, the etched semiconductor structure may also be a trench, a hole, a line, and other regular or irregular patterns or patterns. On the basis of the formed semiconductor structure, semiconductor structures such as a source-drain region, a grid electrode and the like can be formed according to the existing semiconductor manufacturing process, and finally a required semiconductor device is formed.
The pattern width (L) and the pitch (P) of the formed semiconductor structure are determined by the chemical properties of the initially used block copolymer, namely the size of the periodic structure after the self-assembly micro-phase separation and the size of the subsequently deposited side wall thickness (S). As an embodiment, the above two aspects are adjusted to obtain a semiconductor structure pattern with equal spacing, that is, the sum of the size of the second polymer block 7 and the thickness of the sidewall on both sides etched on the mandrel layer (mandrel) pattern 3 is equal to the size of the first polymer region 6 removed by etching. If the sum of the two is not equal to the size of the etched first polymer regions 6, the resulting semiconductor structure will be a non-equidistant patterned array, which is commonly used in advanced integrated circuit devices, such as a Fin array in a FinFET device, a Nanowire array in a gate Nanowire (gaanewire) device, or a dummy gate electrode array. As a reference example, in a FinFET device with intel 14nm technology node, the top dimension of Fin is approximately 8nm, while the pitch of the Fin array is 42 nm. For the present invention, if such a semiconductor structure is to be manufactured, the following conditions are required: firstly, selecting an asymmetric block copolymer, wherein theoretically, the width of a first phase-separated polymer region is 34nm, the width of a second phase-separated polymer region is 50nm, and the former is used as a mask to remove the latter; second, 8nm of sidewall dielectric material was deposited on the mandrels. And obtaining the Fin array structure of the FinFET device through a series of pattern transfer processes.
By means of the whole process, the buffer layer material is introduced, the problem of etching process caused by weak etching resistance of the segmented copolymer molecules is reduced, mask budget of subsequent etching is increased by adopting a multi-layer pattern transfer method, and the obtained mask pattern is further miniaturized by adopting a side wall transfer technology, so that the size of the desired geometric pattern can be obtained on the semiconductor substrate. The method is compatible with the state-of-the-art FinFET device fabrication process, and the disclosed method also provides more space for the CD and pitch control of the semiconductor structure, i.e., the final feature size can be further scaled down.
Although the invention has been described in detail hereinabove with respect to specific embodiments thereof, it will be apparent to those skilled in the art that modifications and improvements can be made thereto without departing from the scope of the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims (10)

1. A method for preparing a semiconductor nano device structure by adopting directional self-assembly is characterized by comprising the following steps:
providing a semiconductor substrate (1), sequentially forming a mandrel layer (3) and a photoetching stacking layer (4) on the semiconductor substrate, and forming a plurality of guide structure patterns on the photoetching stacking layer (4);
depositing a Block Copolymer (BCP) layer between the guide structure patterns, annealing to form a directional self-assembly pattern consisting of a plurality of phase-separated polymer blocks, and filling the whole area between the guide structures with the phase-separated different polymer blocks and periodically repeating;
selectively removing the polymer block region, using the remaining polymer block region as an etching mask, sequentially transferring the etching mask pattern to the photoetching stack layer (4) and the mandrel layer (3), and removing the photoetching stack layer (4) pattern to obtain an etched mandrel layer pattern;
depositing a side wall dielectric layer (8) on the pattern of the mandrel layer (3), and then removing the dielectric layer on the horizontal part of the mandrel layer (3) and reserving the dielectric layer on the side wall of the pattern of the mandrel (3);
and further removing the mandrel layer material, and then defining the semiconductor substrate (1) by using the reserved side wall dielectric layer as a mask to form a semiconductor nano-structure pattern.
2. The method for directional self-assembly fabrication of semiconductor nano-device structures according to claim 1, wherein the guide structure pattern is formed from a hardened photoresist or from a hard mask via lithography and etching.
3. The method for fabricating semiconductor nano-device structures by directed self-assembly according to claim 1, wherein the self-assembly pattern is formed by diblock copolymers, triblock copolymers or other multiblock copolymers, wherein the widths of the polymer block regions formed may be the same or different.
4. The method for the directed self-assembly fabrication of semiconductor nano-device structures according to claim 1, wherein a hard mask layer (2) is deposited between the semiconductor substrate (1) and the mandrel layer (3), the sidewall dielectric layer pattern is transferred onto the hard mask layer (2), and then the semiconductor substrate (1) is defined with a double-layer mask.
5. The method for the directed self-assembly fabrication of semiconductor nano-device structures according to claim 1, wherein a buffer layer (5) is disposed between the photolithographically stacked layer (4) and a Block Copolymer (BCP) layer, and the pattern forming the block copolymer layer is transferred to the buffer layer (5) and then to the photolithographically stacked layer (4) and the mandrel layer (3).
6. The method for fabricating semiconductor nano-device structures by directed self-assembly according to claim 1, wherein the buffer layer (5) has a layer of neutral material on its surface, and the layer of neutral material is in direct contact with or not in contact with the sidewalls of the guiding structure pattern.
7. The method for fabricating semiconductor nano-device structure according to directed self-assembly of claim 1, wherein a block copolymer is directly deposited on the surface of the buffer layer (5) without using a neutral material layer, wherein the material of the block copolymer layer is selected from Polystyrene-Polycarbonate (PS-b-PC).
8. The method for the directed self-assembly fabrication of semiconductor nano-device structures according to claim 1, wherein the buffer layer (5) is made of a material selected from polysilicon or amorphous silicon and etched with a copolymer block as a mask using a halogen-based, fluorine-based and fluorocarbon-based gas, preferably Cl2HBr or SF6、CH2F2。
9. The method for the directed self-assembly preparation of a semiconductor nanodevice structure according to claim 1, wherein the lithographic stack (4) comprises an Optical Planarization (OPL) layer (4 ") and an anti-reflective coating (ARC) (4') stack or a stack of an Optical Planarization (OPL) layer and an insulating dielectric layer or a single insulating dielectric layer, wherein the Optical Planarization Layer (OPL) is preferably inorganic amorphous carbon or spin-on carbon or diamond-like carbon, the anti-reflective coating (ARC) is preferably a silicon-containing anti-reflective coating material, and the insulating dielectric layer is preferably silicon oxide, silicon nitride or silicon oxynitride.
10. The method for the directed self-assembly fabrication of semiconductor nano-device structures according to claim 1, wherein the mandrel layer (3) and the hard mask layer (2) are silicon-based dielectric material, preferably silicon oxide, silicon nitride, polysilicon, amorphous silicon, or metal compound material, preferably aluminum oxide, titanium nitride, which may be the same or different.
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