KR20090009788A - Topography directed patterning - Google Patents

Abstract

A pattern having exceptionally small features is formed on a partially fabricated integrated circuit (102) during integrated circuit fabrication. The pattern comprises features (162), (164) formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers (152) which have been formed by a pitch multiplication process in which the spacers (152) are formed at the sides of sacrificial mandrels (142), which are later removed to leave the spaced-apart, free-standing spacers (152). Diblock copolymers, composed of two immiscible block species, are deposited over and in the space between the spacers (152). The copolymers are made to self-organize, with each block species aggregating with other block species of the same type.

Description

Topography Oriented Patterning {TOPOGRAPHY DIRECTED PATTERNING}

The present invention generally relates to integrated circuit fabrication and, more particularly, to printing techniques.

As a result of a number of factors, including increased mobility, computational power, memory capacity, and the need for energy efficiency, integrated circuits are constantly becoming dense. Constitutive features forming integrated circuits, such as electronic devices and interconnect lines, are constantly shrinking to facilitate such scaling.

The tendency of feature size to be reduced is evident in memory circuits or devices such as, for example, dynamic random access memory (DRAM), flash memory, static random access memory (SRAM), ferroelectric (FE) memory, and the like. For example, DRAMs include millions of identical circuit elements, commonly known as memory cells. In general, capacitor-based memory cells, such as in conventional DRAM, typically include two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary number) of data. The bit can be written to the cell through the transistor and read by detecting the charge in the capacitor. Some memory techniques use devices that can act as both a storage device and a switch (eg, dendritic memory using silver-doped chalcogenide glass), and some non-volatile memory in each cell. No switch is required (e.g., magnetoresistive RAM) or the switch is integrated into the memory element (e.g., EEPROM). By reducing the size of the electrical devices that make up the memory cell and the conductive lines that access the memory cells, the memory devices can be made smaller. In addition, the storage capacity can be increased by embedding more memory cells on a given area in the memory device. However, the need for reducing feature size is more generally applicable to integrated circuits including general purpose processors and specialized processors.

There is a greater demand on the techniques used to form features due to the continuous reduction in feature size. Photolithography, for example, is commonly used to pattern such features. Typically, photolithography involves passing light through a reticle and concentrating the light on a photochemically active photoresist material. Just as the slide has an image to be projected on the screen, the reticle typically has a pattern to be transferred to the substrate. By allowing light or radiation to pass through the reticle, the pattern in the reticle can be concentrated on the photoresist. Light or radiation causes chemical changes in the illuminated portions of the photoresist, allowing them to be selectively removed or retained, as desired, for the portions that were in the shade. Thus, the exposed and unexposed portions form a pattern in the photoresist. It will be appreciated that such a pattern can be used as a mask to form various features of an integrated circuit including conductive lines or portions of an electrical device.

Since lithography is usually achieved by projecting light or radiation onto a surface, the final resolution of a particular lithography technique depends on factors such as the lens and the light or radiation wavelength. For example, the ability to focus well-defined patterns on the resist depends on the size of the features and the wavelength of the radiation projected through the reticle. Among other things, it will be understood that by diffraction, the resolution decreases with increasing wavelength. Thus, as features decrease in size, short wavelength radiation is usually required to form well-resolved features. Thus, in order to facilitate the reduction of feature size, increasingly lower wavelength systems have been proposed.

For example, as feature size is reduced, systems of 365 nm, 248 nm, 193 nm and 157 nm wavelengths have been developed. Further reduction of feature size, for example features up to 20 nm, requires a shorter wavelength system. For example, X-ray based lithography using X-ray radiation instead of light has been proposed to form very small features, such as 20 nm features. Another technique proposed is extreme ultraviolet (EUV) lithography using, for example, 13.7 nm radiation. However, X-ray and EUV lithography are expected to be enormously expensive to implement. In addition to cost, these techniques also face various technical hurdles. For example, in X-ray lithography, these obstacles include the difficulty of forming a high quality reticle that is sufficiently opaque to X-rays and the difficulty of designing resists that are sufficiently sensitive to X-rays. Moreover, instead of using a lens to focus radiation on the resist, the X-ray system places the reticle close to the resist to directly expose the resist to the X-ray passing through the reticle. This causes complexity in aligning the reticle with the resist, and also greatly requires both the reticle and the resist to be flat. X-ray lithography also uses reflective lenses as opposed to refractive lenses, which may require a complete redesign of optical elements and associated systems. Likewise, other high resolution lithography techniques, including ion beam and electron beam resourcerapies, have their own technical and practical obstacles, including high complexity and cost.

Thus, there is a continuing need for a high resolution method for patterning small features on a semiconductor substrate.

According to one aspect of the present invention, a method for forming a pattern on a semiconductor substrate is provided. The method includes providing a plurality of pitch multiplied features covering a semiconductor substrate. A self-organization material is then provided between the pitch multiplied features. Separation of chemical species forming a self-organizing material begins.

According to another aspect of the present invention, a method for forming a mask pattern is provided. The method includes forming a plurality of spacers by pitch multiplication. A film is formed between the spacers. The film is annealed to form a repeating pattern of features in the film.

According to another aspect of the invention, a method for semiconductor manufacturing is provided. The method includes providing a plurality of lines having a pitch of about 200 nm or less. A pattern comprising block copolymers is formed between the plurality of lines.

According to another aspect of the present invention, a method for forming a mask is provided. The method includes providing a pattern of spacers over a semiconductor substrate. The method also includes providing a homogeneous mask material extending between the spacers. The mask material is exposed to the etchant to form a pattern of voids in the exposed mask material.

According to another aspect of the present invention, a method of semiconductor processing is provided. The method includes forming a first set of block domains on a substrate on a peninsula. The first set of block copolymers comprises a plurality of separate groups of block domains. The second set of block domains is formed subsequent to the spaces between the separated groups of block domains.

According to another aspect of the present invention, a partially manufactured integrated circuit is provided. A partially fabricated integrated circuit includes a plurality of copolymer guides covering a semiconductor substrate, the guides having a pitch of about 200 nm or less. Partially fabricated integrated circuits also include block copolymers disposed between a plurality of copolymer guides.

It will be better understood from the following detailed description of the preferred embodiments of the invention and the accompanying drawings, which are intended to illustrate the invention and not to limit the invention.

1 is a schematic side cross-sectional view of a partially formed integrated circuit, in accordance with preferred embodiments of the present invention.

FIG. 2 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 1 after forming features in the photoresist layer, in accordance with preferred embodiments of the present invention. FIG.

3 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 2 after etching through a hardmask layer, in accordance with preferred embodiments of the present invention.

4 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 3 after removing the photoresist and transferring the pattern from the hardmask layer to the temporary layer in accordance with preferred embodiments of the present invention.

FIG. 5 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 4 after removal of the hard mask layer, in accordance with preferred embodiments of the present invention. FIG.

6 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 5 after depositing a layer of spacer material, in accordance with preferred embodiments of the present invention.

FIG. 7 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 6 after spacer etching, in accordance with preferred embodiments of the present invention. FIG.

FIG. 8 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 7 after removing the remaining portion of the temporary layer to leave a pattern of spacers in accordance with preferred embodiments of the present invention. FIG.

9 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 8 after depositing a layer of a block copolymer solution, in accordance with preferred embodiments of the present invention.

10 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 9 after self-organization of the block copolymer, in accordance with preferred embodiments of the present invention.

11 and 12 are schematic side cross-sectional views of the partially formed integrated circuit of FIG. 10 showing two exemplary copolymer alignments resulting from self-organization of block copolymers, in accordance with preferred embodiments of the present invention.

FIG. 13 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 12 after selectively removing one of the blocks of two block copolymers, in accordance with preferred embodiments of the present invention. FIG.

FIG. 14 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 13 after transferring a pattern defined by a block copolymer to a lower substrate, in accordance with preferred embodiments of the present invention. FIG.

Figure 15 is a schematic side cross-sectional view of a partially formed integrated circuit after transferring a pattern defined by a block copolymer to a hardmask layer and then to a lower substrate, in accordance with preferred embodiments of the present invention.

16 is a schematic side cross-sectional view of a partially formed integrated circuit after forming spacers in the sidewalls of the mandrels, in accordance with preferred embodiments of the present invention.

FIG. 17 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 16 after depositing a layer of a block copolymer solution, in accordance with preferred embodiments of the present invention. FIG.

FIG. 18 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 17 after self-organization of the block copolymer, in accordance with preferred embodiments of the present invention. FIG.

19 selectively removes one of the two copolymer blocks, transfers the pattern formed by the remaining copolymer blocks to the underlying hardmask layer, and retains the remaining copolymer blocks, according to preferred embodiments of the present invention. Schematic side cross-sectional view of the partially formed integrated circuit of FIG. 18 after removal thereof.

FIG. 20 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 19 after planarization to deposit a layer of filler material to fill spaces between spacers and to expose mandrels in accordance with preferred embodiments of the present invention.

FIG. 21 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 20 after removing mandrels, in accordance with preferred embodiments of the present invention. FIG.

FIG. 22 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 21 after depositing a second layer of a block copolymer solution, in accordance with preferred embodiments of the present invention. FIG.

FIG. 23 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 22 after self-organization of the block copolymer, in accordance with preferred embodiments of the present invention. FIG.

FIG. 24 is a schematic side view of the partially formed integrated circuit of FIG. 23 after selectively removing one of two copolymer block species with respect to the other block species and with respect to the filler material, in accordance with preferred embodiments of the present invention. Cross-section.

25 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 24 after transferring the pattern formed by the remaining blocks to the underlying hardmask layer and removing the filler material, in accordance with preferred embodiments of the present invention.

FIG. 26 is a schematic side cross-sectional view of the partially formed integrated circuit of FIG. 25 after transferring a pattern formed by copolymer blocks to a lower substrate, in accordance with preferred embodiments of the present invention. FIG.

The ability of the block copolymers to self-organize can be used to form a mask pattern. Block copolymers are formed of two or more chemically different blocks. For example, each block may be formed of a different monomer. The blocks are preferably not mixed or thermodynamically incompatible, for example one block may be polar and the other block may be nonpolar. Because of the thermodynamic effect, the copolymers will self-organize in solution, minimizing the energy of the system as a whole, which usually makes the copolymers easier to move relative to one another, for example, the same blocks aggregate together, To form alternating regions containing block types or species of. For example, if copolymers are formed of polar and nonpolar blocks, the blocks are separated so that nonpolar blocks aggregate with other nonpolar blocks and polar blocks aggregate with other polar blocks. Block copolymers can be described as self-organizing materials because blocks can form patterns without the application of external forces that direct the movement of individual molecules, but to increase the speed of migration as described below. It will be appreciated that heat may be applied.

In addition to the interactions between the block species, self-organization of the block copolymers can also be affected by topographical features such as steps of the surface on which the block copolymer is deposited. For example, a diblock copolymer formed of two different block species may form alternating regions, each formed of substantially different block species. When self-organization occurs in the area between the walls of the step, the steps interact with the blocks such that each of the alternating areas formed by the blocks can extend parallel to the walls.

Such self-organization can be useful for forming masks for patterning features during semiconductor manufacturing processes. For example, one of the alternating regions can be removed, thereby leaving other regions to function as a mask. The mask can be used to pattern features, such as battery devices, in the underlying semiconductor substrate.

It will be appreciated that the size of the alternating regions is related to the size of the block copolymers and may be in the unit of several nanometers or tens of nanometers. In forming near-distance stepped features, various lithography methods such as X-ray, EUV, ion beam and electron beam lithography are possible candidates. However, applying these methods has various technical and practical obstacles, as discussed above, that can make their use unrealistically and excessively expensive.

In preferred embodiments of the present invention, instead of defining steps in a single lithography step, relatively large features are first defined and then smaller step features are derived from the relatively large features. Block copolymers are then applied around the steps, allowing self-organization in the steps, or in the spaces between the guides, features. Some of the blocks are subsequently selectively removed. Residual block species may be used as a mask for subsequent patterning of underlying material, such as during fabrication of integrated circuits.

Preferably, pitch multiplication is used to form small stepped features. For example, relatively large features can be patterned by conventional photolithography to form a pattern of temporary placeholders or mandrels. Spacers are formed on the sides of the mandrels and then the mandrels are removed, leaving a pattern of free-standing spacers that function as guides to induce self-organization of the block copolymers.

Pitch multiplication advantageously enables the formation of small, close-range stepped features that, if not used, will be formed using new, relatively complex and expensive lithography techniques. Advantageously, conventional, certified and relatively inexpensive lithography techniques can be used, thereby reducing costs and increasing processing reliability. Moreover, the self-organizing behavior of block copolymers allows for the reliable formation of very small features, facilitating the formation of masks of very small feature sizes. For example, features having a critical dimension of about 50 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, can be formed.

Reference will now be made to the drawings, wherein like numerals refer to like parts throughout. It will be appreciated that the drawings are not necessarily drawn to scale.

In a first step of the method according to the preferred embodiments a plurality of spacers are formed on the substrate by pitch multiplication. Suitable pitch multiplication techniques are described in US Pat. No. 11 / 214,544, filed Aug. 29, 2005, by US Pat. No. 5,328,810 to Tran, et al. The entire disclosure of these references is incorporated herein by reference. It will be appreciated that these preferred embodiments can be used to form masks used in the manufacture of various integrated circuits. These integrated circuits may include, for example, memory chips or computer processors.

Referring to FIG. 1, a side cross-sectional view of a partially formed integrated circuit 100 is shown. Various layers 120-140 are preferably provided over the substrate 110 to facilitate pitch multiplication. The material for the layers 120-140 covering the substrate 110 is the interaction of the block copolymer materials with the layers and the chemistry and processing conditions for the various pattern formation and pattern transfer steps discussed herein. Are preferably selected in view of these considerations. Since the patterns of the upper layers are preferably transferred to the lower layers during the pitch multiplication, the lower masking layers 130, 140 between the selectively definable layer 120 and the substrate 110 are exposed to other exposed parts. It is preferably selected so that it can be selectively etched with respect to the materials. When the etch rate for the material is at least about 2-3 times larger than the surrounding material, preferably at least about 10 times larger, more preferably at least about 10 times larger, and most preferably at least about 40 times larger It will be understood that when the material is selectively or preferably etched. Since the purpose for layers 120-140 is to enable the formation of a well formed pattern on substrate 110, layers 120-140 may be used if other suitable materials, chemical reactions and / or processing conditions are used. It will be appreciated that one or more of may be deleted or replaced, or additional layers may be added.

It will be appreciated that the “substrate” to which patterns are transferred may include a layer of a single material, a plurality of layers of different materials, a layer or layers having regions of different materials or structures therein, and the like. These materials may include semiconductors, insulators, conductors or combinations thereof. For example, the substrate may comprise a metal layer, such as doped polysilicon, an electrical device active region, silicide, or a tungsten, aluminum or copper layer or combinations thereof. In some embodiments, the mask features discussed below can correspond directly to the desired placement of conductive features, such as interconnects, in the substrate. In other embodiments, the substrate may be an insulator and the placement of the mask features may correspond to a preferred placement of the insulator between the conductor features, such as in damascene metallization.

With continued reference to FIG. 1, an optionally definable layer 120 covers the hardmask, or etch stop, layer 130, and the hardmask or etch stopper layer 130 provides a temporary layer 140. The temporary layer 140 covers the substrate 110. The selectively definable layer 120 is preferably photodefinable and is formed of a photoresist including, for example, any photoresist known in the art. For example, the photoresist may be any photoresist compatible with a 157 nm, 193 nm, 248 nm or 365 nm wavelength system, a 193 nm wavelength immersion system. Examples of preferred photoresist materials are argon fluoride (ArF) reactive photoresist, ie photoresist suitable for use with ArF light sources, and krypton fluoride (KrF) reactive photoresist, ie photoresist suitable for use with KrF light sources. It includes a resist. ArF photoresists are preferably used with photolithography systems that utilize relatively short wavelength light, such as wavelength light of 193 nm. KrF photoresists are preferably used with longer wavelength photolithography systems, such as in 248 nm systems. In addition, the use of pitch multiplication eliminates the need to define very small features with expensive, relatively new direct forming techniques such as extreme ultraviolet systems (including 13.7 nm wavelength systems) or electron beam lithography systems. It can be used if you want. In addition, maskless lithography, or maskless photolithography, may be used to define the selectively definable layer 120. In other embodiments, layer 120 and any subsequent resist layers may be patterned using nano-imprint lithography, such as by forming a pattern in the resist using a mold or mechanical force.

The material for hardmask layer 130 preferably includes an inorganic material. Exemplary materials include a dielectric anti-reflective coating (DARC) such as silicon oxide (SiO ₂ ), silicon or silicon-rich silicon oxynitride. Preferably, hard mask layer 130 is DARC. Using DARC for hardmask layer 130 is particularly beneficial for forming patterns with pitches that are close to the resolution limitations of photolithographic techniques. DARC can improve resolution by minimizing light reflections, thus increasing the accuracy with which photolithography can define the edges of a pattern.

Temporary layer 140 is preferably formed of amorphous carbon, which provides very high etch selectivity over preferred hardmask materials. More preferably, this amorphous carbon is formed of amorphous carbon which is very transparent to light and transparent to the wavelengths of light used for the light alignment to provide a better improvement in the light alignment. Techniques for forming such transparent carbon can be found in A. Helmbold, D. Meissner, Thin Solid Films, 283 (1996) 196-203. The entire disclosure of this reference is incorporated herein by reference.

With reference to FIG. 2, photodefinable layer 120 is exposed to radiation through a reticle and then developed to leave a pattern comprising features 122 formed of photodefinable material. It will be appreciated that the resulting features 122, such as the pitch of the lines, are equal to the sum of the width of the line 122 and the width of the neighboring space 124. If desired, the dimension of the line 122 may be adjusted, for example by isotropic etching, to reduce both the height and width of the line 122. The pitch of the features 122 can be, for example, about 200 nm or about 120 nm.

Referring to FIG. 3, the pattern of the photodefinable layer 120 is transferred to the hard mask layer 130 to form features 132 in the hard mask layer 130. In particular, FIG. 3 shows features 122 and 132 separately. Pattern transfer is preferably achieved using anisotropic etching, such as etching using fluorocarbon plasma, although wet (isotropic) etching may be appropriate if the hardmask layer 130 is sufficiently thin. Preferred fluorocarbon plasma etch chemistries include CFH ₃ , CF ₂ H ₂ , CF ₃ H and CF ₄ / HBr. The resist forming the photodefinable layer 120 may be selectively removed by, for example, plasma ashing. In the illustrated embodiment, resist removal can be delayed and has the advantage of being efficiently performed in a single step using the etching of the temporary layer 140.

Referring to FIG. 4, the patterns of the photodefinable layer 120 and the hard mask layer 130 are transferred to the temporary layer 140 to allow the deposition of the layer 150 of the spacer material (FIG. 6). The temperature used for spacer material deposition is typically too high to withstand photoresists. Thus, the pattern is formed from the features 122 (FIG. 3) of the photodefinable layer 120 from a material that can withstand the processing conditions for spacer material deposition and etching discussed below. Is preferably transferred. In addition to having a higher thermal resistance than the photoresist, the material forming the temporary layer 140 may be formed on the spacers 152 (FIG. 7) formed and any underlying material, for example, the substrate 110. It is preferably selected so that it can be selectively removed in relation to the material. As mentioned above, layer 140 is preferably formed of amorphous carbon, more preferably of transparent carbon.

The pattern of features 122 in the modified photodefinable layer 120 may comprise an O ₂ -containing plasma, such as a plasma comprising sulfur dioxide (SO ₂ ), oxygen (O ₂ ), and argon (Ar). Is preferably transferred to the temporary layer 140. Other suitable etching chemistries include plasma comprising Cl ₂ / O ₂ / SiCl ₄ or SiCl ₄ / O ₂ / N ₂ or / HBr / O ₂ / N ₂ / SiCl ₄ . The SO ₂ -containing plasma is used because it is possible to etch carbon in the desired temporary layer 140 at a rate 20 times faster, more preferably 40 times faster than the rate at which the hardmask layer 130 is etched. Suitable SO ₂ -containing plasmas are described in US patent application Ser. No. 10 / 931,772, filed August 31, 2004 by Abatchev et al., The entire disclosure of which is incorporated herein by reference. It will be appreciated that the SO ₂ -containing plasma may simultaneously etch the temporary layer 140 and remove features 122 formed from the photodefinable layer 120. The resulting lines 142 in the temporary layer 140 constitute placeholders or mandrels in which a pattern of spacers 152 (FIG. 7) will be formed accordingly.

Referring to FIG. 5, the material 132 (FIG. 4) from the hardmask layer 130 leaves later the formation of the spacer 140 for subsequent etching (FIG. 8), resulting in later spacer formation. Can be removed to facilitate. Preferred hardmask layer 130 may be removed using a buffered oxide etch (BOE), which is a wet etch comprising HF and NH ₄ F.

Next, as shown in FIG. 6, the layer 150 of spacer material includes the hardmask layer 130 (if remaining) and the top and sidewalls of the mandrels 142. Blank film is preferably formed at a conformal angle. The spacer material may function as a mask to transfer the pattern to the underlying substrate 110 and, as discussed below, to allow for etching selectivity with respect to one or more block species of the block copolymer. It may be a material of. The spacer material may preferably be 1) deposited with good step coverage, and 2) deposited at a temperature compatible with the temporary layer 140. Preferred materials include silicon, silicon oxides and silicon nitrides. In the embodiment shown, the spacer material is silicon oxide, which provides certain advantages in combining with other selected materials of the masking stack.

Preferred methods for spacer material deposition include chemical vapor deposition to form silicon oxide using, for example, O ₃ and TEOS, and silicon oxides using silicon precursor with, for example, oxygen or nitrogen precursors. Or atomic layer deposition which respectively forms nitrides. The thickness of layer 150 is preferably determined based on the desired width of spacers 152 (FIG. 8). Preferably, the step coverage is at least about 80%, more preferably at least about 90%. Atomic layer deposition allows for a high degree of control over the thickness of the deposited layer 150. This control is particularly advantageous when forming guides for the block copolymer, which self-organization of the block copolymer is affected by the thickness of the deposited block copolymer material and the spacers 152 This is because some block copolymer material overlies the spacers 152 and is connected with the copolymer material between the spacers 152 so that the height of the is preferably sufficiently close to the thickness of the block copolymer material (to be deposited). . Preferably, as mentioned below, having a copolymer material overlying spacers 152 provides a reservoir of copolymer material that can protect against depletion of copolymers during self-organization of the copolymer. Can provide.

Referring to FIG. 7, the silicon oxide spacer layer 150 is then subjected to an anisotropic etch to remove the spacer material from the horizontal surfaces 154 of the partially formed integrated circuit 100. Such etching, also known as spacer etching, can be performed using a fluorocarbon plasma including, for example, a CF ₄ / CHF ₃ , C ₄ F ₈ / CH ₂ F ₂ or CHF ₃ / Ar plasma.

Referring to FIG. 8, the mandrels and temporary placeholders 142 (FIG. 7) are then removed and leave free standing spacers 152. Mandrels 142 are selectively removed using an organic strip process. Preferred etching chemistries include oxygen-containing plasma etching, such as etching with SO ₂ .

As mentioned above, the height of the spacers 152 may affect the organization of the block copolymers as discussed below. As a result, the spacers 152 may be additionally trimmed using, for example, an anisotropic etch. In other embodiments, the height of the mandrels 142 (FIG. 6) and / or the thickness of the temporary layer 140 (FIG. 1) may be selected to form spacers 152 of the desired height.

With continued reference to FIG. 8, pitch multiplication was achieved. In the illustrated embodiment, the pitch of the spacers 152 is approximately half the pitch of the photoresist lines 122 and spacers 124 (FIG. 2) originally formed by photolithography. For example, when the photoresist lines 122 have a pitch of about 400 nm, spacers 152 having a pitch of about 200 nm or less may be formed. In some embodiments, when the photoresist lines 122 have a pitch of about 200 nm, spacers 152 having a pitch of about 100 nm or less may be formed.

Next, block copolymers are applied and block copolymer self-organization is facilitated to form a mask pattern for the substrate 110. Suitable methods for self-organized block copolymer patterns are described in Block, IEE Transactions in Nanotechnology, Vol 3, No. 3, September 2004. The entire disclosure of this reference is incorporated herein by reference.

With reference to FIG. 9, a film 160 of block copolymer material is deposited between and over the spacers 152. The copolymer comprises blocks of polymeric material that can be selectively etched with respect to one another and can be self-organized in a desired and predictable manner, for example, the blocks are preferably not mixed and are a single block. Will be separated under appropriate conditions to form regions containing predominantly species. In the exemplary embodiment shown, the copolymer is 70:30 PS, for example polystyrene (PS) and poly-methylmethacrylate (PMMA) to have a total molecular weight of 64 kg / mol. It is a diblock copolymer included in a: PMMA ratio. The diblock copolymer may be provided dissolved in a solvent such as, for example, toluene. Preferably, the copolymers have substantially the same size and configuration in order to increase the predictability and regularity of the patterns formed by self-organization of the copolymers. It will be appreciated that the overall size and ratio of constituent blocks and monomers of each diblock copolymer is preferably chosen to facilitate self-organization and form organized block regions with the desired dimensions. Block copolymers have an inherent polymer length scale in the membrane, including any coiling or kinking, which governs the size of the block regions, the average length from end to end of the copolymer. Longer copolymers can be used to form larger regions and shorter copolymers can be used to form smaller regions. The block copolymer can be deposited in a variety of ways, including, for example, spin-on coating, spin casting, brush coating or vapor deposition. have.

The thickness of the copolymer film 160 may be selected based on the desired pattern to be formed by the copolymers. Hybrid polymers, as shown in the plan view (FIG. 11), up to a polymer length scale and the environment in which the polymers are disposed, for example, the distance between the spacers 152 and a certain thickness associated with the height of the spacers 152. It will typically be directed to form alternating substantially thin plate regions, forming parallel lines. Such a thin plate can be used, for example, to pattern interconnects, or the transverse extension of the thin plate can be limited to form discrete features, eg transistor gates. The specific thickness above relates to the polymer length scale and the environment in which the polymers are placed, and the copolymers will typically be directed to form vertically expanding pillars, such as cylinders, spheres (FIG. 12). The advantage is that the cylinders can be used to pattern discrete features, for example vias or transistor gates. Therefore, there is an advantage that the pattern to be formed can be selected by appropriate selection of the copolymer film thickness. Alternatively, other variables, such as copolymer synthesis or process conditions, may be altered such that pillars or horizontally extending columns perpendicular to a given thickness through appropriate selection of the interface interaction between substrate surfaces and blocks of the copolymer. It is possible to facilitate the formation of a thin plate extending to. The thickness of the film 160 may be greater than, equal to, or less than the height of the spacer 152. As mentioned below, a thickness greater than the height of the spacers has the advantage of providing a copolymer reservoir. In another embodiment, a thickness equal to or more preferably less than the height of the spacers may be advantageous by forming separate islands of copolymers between the spacers 152, whereby air between islands Prevent cross-diffusion of coalescence.

In order to form a thin plate, the copolymer film thickness is preferably approximately smaller than the length scale of the copolymer. For example, in the illustrated embodiment, the copolymer length scale is about 35 nm, and the thickness of the films is preferably about 35 nm or less, more preferably about 30 nm or less, most preferably about 25 nm or less. In one embodiment, the thickness is about 20 nm.

Referring to FIG. 10, block copolymers of copolymer film 160 are allowed to self-organize. Self-organization can be facilitated and accelerated by annealing a partially fabricated integrated circuit 100. The temperature of the annealing is preferably chosen to be low enough to prevent adverse effects on the block copolymers or the partially fabricated integrated circuit 100. In the illustrated embodiment, the annealing is preferably performed at a temperature lower than about 250 ° C., more preferably lower than about 200 ° C., and most preferably lower than about 180 ° C. Annealing can also cause cross-linking of the copolymers, thereby stabilizing the copolymers for later etching and pattern transfer steps.

The resulting thin plate pattern after annealing is shown in FIG. 10. Regions 162 of one block species, eg, regions 162 of PS, and other block species, eg, regions 164 of PMMA, alternate between spacers 152. It will be appreciated that the sizes of the block regions are determined by the sizes of the block species forming them.

Referring to FIG. 11, a plan view of the partially fabricated integrated circuit of FIG. 10 is shown. PS domains 162 may be represented alternately with PMMA domains 164. Both domains 162 and 164 extend along the length of the spacers 152.

In other embodiments, referring to FIG. 12, the thickness of copolymer film 160 (FIG. 9) may be defined as columns having vertically extending cylinders (or square or cubic horizontal cross-sectional areas) including PS and PMMA. And other separate pillar shapes). From the top view, the resulting structure has regions of PS 162a surrounded by regions 164a of PMMA. The structure can be useful, for example, in forming contact vias. In addition, the pillars may be advantageously applied to patterning arrays of features, particularly dense arrays of features, such as capacitors for memory applications, including DRAM in some structures. In the structures, the columns may have rectangular or cubic horizontal cross-sectional areas, which may have advantages by providing a high surface area structure.

Referring to FIG. 13, the PMMA domains 164 of FIGS. 10 and 11 are selectively removed to leave spacers 152 and PS domains 162. The removal can be implemented, for example, by performing wet etching using acetic acid as an etchant. In other embodiments, dry or anisotropic etching may be appropriate where one of the domains may be etched at a faster rate than the other. It will be appreciated that depending on the size and process conditions of the copolymer used, the dimensions of the resulting features may vary. In some embodiments, the resulting pattern can advantageously include PS domains having a critical dimension of about 20 nm separated by spaces of about 20 nm. In other embodiments, the PS domains 162 and / or spacers 152 may instead be removed, thereby causing the PMMA domain 164 with or without spacers 152. Will be understood.

Referring to FIG. 14, the spacers 152 and the domains 162 may be used as a mask for processing the lower substrate 110. For example, the substrate 110 may be, for example, using an anisotropic etch to selectively etch the substrate for both the spacers 152 and the domains 162 to transfer the pattern of the mask to the substrate 110. It can be etched through the mask. In one example, where the spacers 152 are formed of silicon oxide and the substrate 110 is formed of silicon, the substrate 110 selectively removes the silicon layers, for example with respect to the photoresist. It may be selectively etched against the spacers 152 and the block domains 162 using the fluorine-based dry etch chemistry used. If the substrate 110 includes layers of different materials, if a single chemistry is not sufficient to etch all the different materials, then different chemistries, preferably dry etch chemistry, are performed to etch continuously through these different layers. It will be appreciated that reactions can be used. It will also be appreciated that depending on the chemical reaction or chemical reactions used, the spacers 152 and domains 162 may be etched. Thus, referring to FIG. 15, in some embodiments, the pattern formed by the spacers 152 and the domains 162 may provide good etch selectivity with respect to the substrate materials prior to etching the substrate 110. It may be transferred to the lower hard mask layer 170 having a.

Although the present invention is not limited to theory, different block species may self-aggregate due to thermodynamic considerations of a process similar to phase separation of materials. Self-organization is guided by the spacers 152 (FIG. 9), and the building blocks of the block copolymers promote their orientation along the length of the spacers 152. Self-organization may cause the copolymers usable for self-organization to be depleted if copolymer film 160 is extended to very large areas, such that regions in the middle of the expanded portion are formed without organized copolymers. It will be appreciated that more efficient packing of coalescing species can be made. In some embodiments, the copolymer film 160 is preferably thick enough to expand on the spacers 152 to provide a reservoir of copolymers for self-organization that occurs between the spacers 152. It will also be understood. In addition, the distance between the spacers 152 is preferably selected small enough to minimize the depletion effect that may occur for large expansions.

In other embodiments, the reservoir region on the spacers 152 may extend beyond the spacers 152. The expansion can have advantages in forming well defined block domains between the relatively wide separated spacers 152.

Referring to FIG. 16, the steps illustrated with reference to FIGS. 1 through 6 may be used to form spacers 152 on the sides of the mandrel 142, which becomes a partially manufactured integrated circuit 102. The spacers 152 and the mandrels 142 cover the hard mask layer 112 covering the substrate 110.

Referring to FIG. 17, a first layer 162 of block copolymer material is deposited between the spacers 152 and over the spacers 152 and the mandrel 142. Advantageously, the mandrels 142 provide a relatively large surface area that enables the formation of a large reservoir 164 of block copolymer material. The block copolymer material may be similar to the block copolymer material described above, including, for example, PS and PMMA, and may have a thickness selected as described above.

Referring to FIG. 18, copolymers are self-organizing and can be accelerated, for example, by annealing a partially fabricated integrated circuit 102. After self-organization, the first set 162 of alternating domains of one block species, eg, PS, and the other block species, eg, domains 164 of PMMA, are interposed between spacers 152. Is formed in the opening space of the.

Referring to FIG. 19, some block domains, for example block domains 164 are selectively removed, and the pattern defined by the remaining domains 162 is transferred to the lower hardmask layer 112 (eg, For example, by anisotropic etching selective to the hardmask layer 112) and the domains 162 are also removed, leaving a pattern of features 114 in the hardmask layer 112. In the plan view, it will be appreciated that the features 114 can be lines or cylinders, as shown by FIGS. 11 and 12.

Referring to FIG. 20, fill layer 116 is deposited around and on top of features 114 to fill the spaces between spacers 152. The fill layer 116 is preferably formed of a planarization material that can be spun and fill the gaps between the features 114. Examples of planarization materials for the fill layer 116 include photoresist or spin on dielectric (SOD). The fill layer 116 can be planarized by, for example, chemical mechanical polishing, or etched back to ensure that the mandrel 142 is exposed, as shown.

Referring to FIG. 21, the mandrels 142 are optionally removed. Referring to FIG. 22, a second layer 180 of copolymer material is deposited. The copolymer material is preferably filled in the opening spaces between the spacers 152 and also covers the remaining portions of the layer 116 to form a reservoir 184 of copolymer material over the regions. While in some embodiments the materials for layers 180 and 162 are different, it will be understood that the copolymer material may be the same as that deposited to form layer 162 (FIG. 17).

Referring to FIG. 23, copolymers of copolymer layer 180 self-organize to form a second set of alternating block domains 186 and 188, for example, during annealing. Referring to FIG. 24, one of the domains, for example, domains 186, is selectively removed to leave domains 188.

Referring to FIG. 25, the pattern defined by the domains 188 is transferred to the lower hardmask layer 112 (eg, by anisotropic etching selective to the hardmask layer 112) and the fill layer ( The remainder of 116 is removed. Depending on the process parameters and the interactions of the blocks with each other and between the block copolymer material and the exposed surfaces, features 114 and 188 may, in plan view, form lines or separate cylinders (respectively, respectively). 11 and 12).

Advantageously, in other embodiments, because features 114 and 188 are formed separately, the features can be made to construct different patterns by implementing the appropriate conditions of the desired type of pattern. For example, features 114 may form a pattern of cylinders, while features 188 may form a pattern of lines. This can be done, for example, by using different copolymer compositions to form the respective features 114 or 188, or, for example, a CMP or etching process to expose the mandrels 142 (FIG. 20). Can be implemented by decreasing the height of the spacers 152 to increase the tendency of the blocks to form lines. In addition, either the lines and / or the vertical pillars, the size and / or spacing between the features 114 or 188 can be usefully changed, for example, by appropriate choice of species and process conditions. .

Referring to FIG. 26, the spacers 152 and the domains 114 and 152 may be used as masks for processing the lower substrate 110. As shown, the pattern defined by the domains 114 and 152 can be transferred to the substrate 110 using, for example, an anisotropic etch selective to the material forming the substrate 110. As described above, in some embodiments, the pattern can be transferred to one or more intervening hardmask layers (not shown) first before being transferred to the substrate 110.

It will be understood that various modifications of the preferred embodiments are possible. For example, copolymers may be formed of two or more block species while described in the context of diblock copolymers. In addition, the block species of the illustrated embodiment are each formed of different monomers, while the block species may share monomer (s). For example, block species may be formed from the same different set of monomers, some of the monomers, or from the same monomer, except for different distributions in each block. Preferably, different sets of monomers form different blocks with different properties that can drive self-organization of the copolymers.

In some embodiments, the hardmask and / or the temporary layer covering the substrate can be omitted. For example, the photodefinable material may be composed of or replaced with a material that is compatible with temperatures and other conditions for space formation. However, in the illustrated embodiment, hardmask and spacer layers are preferred to enable the transfer of high quality patterns and to form high quality spacers.

Also, “processing” through the mask layer preferably includes etching the underlying layer, while processing through the mask layers may include performing any semiconductor manufacturing process on the underlying layers of the mask layers. For example, the processing may include ion implantation, diffusion doping, deposition, or wet etching over the underlying layers through the mask layers. Further, US Provisional Patent Application No. 60, filed Mar. 28, 2005, which may be used as a stop or barrier for chemical mechanical polishing (CMP), or incorporated herein by reference in its entirety. As described in / 666,031, CMP may be performed on any layers to enable both planarization and etching of the underlying layers.

In addition, while the preferred embodiments have been illustrated to apply to exemplary sequences for manufacturing integrated circuits, it will be appreciated that they may be applied to a variety of other applications where the formation of patterns with very small features is desired. For example, preferred embodiments may be applied to form masks for gratings, disk drives, storage media or templates, or other lithography techniques including X-ray or imprint lithography. Can be.

Accordingly, it will be understood by those skilled in the art that these and other various omissions, additions and modifications may be made to the methods and structures described above without departing from the scope of the invention. All such modifications and variations are intended to be included within the scope of the invention as defined by the appended claims.

Claims (86)

As a method for forming a pattern on a semiconductor substrate, Providing a plurality of pitch multiplied features overlying the semiconductor substrate; Providing a self-organizing material between the pitch multiplied features; And Separating chemical species forming the self-organizing material Pattern forming method comprising a. The method of claim 1, Providing the plurality of pitch multiplied features includes: Providing a plurality of mandrels over the substrate; Forming spacers on sidewalls of the mandrels; And Removing the mandrels, leaving free-standing spacers that make up the plurality of pitch multiplied features. Pattern forming method comprising a. The method of claim 2, Providing the plurality of mandrel, Forming a pattern in the photoresist layer; And Transferring the photoresist pattern to a temporary layer over the substrate, wherein features in the temporary layer constitute the mandrels Pattern forming method comprising a. The method of claim 1, The self-organizing material includes block copolymers. The method of claim 4, wherein Segregating the chemical species includes forming regions of repeating pattern, each region being formed of block species forming part of the block copolymer. The method of claim 4, wherein And said block copolymers comprise diblock copolymers. The method of claim 6, The diblock copolymers include polystyrene. The method of claim 7, wherein The diblock copolymers include polymethylmethacrylate. The method of claim 4, wherein Selectively removing block species that form part of the block copolymer. The method of claim 9, Transferring the pattern defined by the remaining block species forming part of the block copolymer to the semiconductor substrate. The method of claim 10, Transferring the pattern to the substrate defines features of a memory device. The method of claim 10, Transferring the pattern to the substrate defines features of a computer processor. The method of claim 1, The step of separating the chemical species comprises annealing. As a method for forming a mask pattern, Forming a plurality of spacers by pitch multiplication; Depositing a film between the spacers; And Annealing the film to form repeating patterns of features in the film Mask pattern forming method comprising a. The method of claim 14, And the features comprise vertical lamellars. The method of claim 14, And the features comprise isolated pillars. The method of claim 16, And the isolated pillars comprise vertical cylinders. The method of claim 14, And the features comprise spheres. The method of claim 14, And the film at least partially covers the spacers. The method of claim 14, And depositing the film comprises spincasting a solution. The method of claim 14, And the thickness of the film is about 35 nm or less. The method of claim 21, And the thickness is about 30 nm or less. The method of claim 22, And the thickness is about 25 nm or less. The method of claim 14, And the film comprises a solution comprising block copolymers. The method of claim 24, And annealing the film causes separation of the blocks forming the block copolymers. The method of claim 14, Exposing the film to an etchant to selectively remove film material from among the features of the repeating pattern. The method of claim 26, Processing a lower layer of material through the features of the repeating pattern. The method of claim 27, Processing the underlying layer of material comprises anisotropically etching the underlying substrate. The method of claim 27, Processing the underlying layer of material comprises transferring the repeating pattern to a hardmask layer. 30. The method of claim 29, further comprising transferring the repeating pattern to a substrate. As a method for manufacturing a semiconductor, Providing a plurality of lines having a pitch of about 200 nm or less; And Forming a pattern comprising block copolymers between the plurality of lines Semiconductor manufacturing method comprising a. The method of claim 31, wherein Providing the plurality of lines includes performing pitch multiplication to form the lines. The method of claim 31, wherein Wherein the pitch is about 100 nm or less. The method of claim 31, wherein And selectively removing at least one block forming said block copolymers. The method of claim 31, wherein Forming the pattern comprises annealing a film comprising the block copolymers. 36. The method of claim 35 wherein And the film has a thickness less than an approximate length scale of the block copolymers. The method of claim 31, wherein And the block copolymers are formed of blocks which cannot be mixed. The method of claim 31, wherein Wherein said lines comprise silicon. The method of claim 38, Wherein said lines comprise silicon oxide. As a mask forming method, Providing a pattern of spacers over a semiconductor substrate; Providing a uniform film of mask material extending between the pair of spacers; Converting the uniform film into a patterned film comprising a pattern defined by mask material moieties; And Exposing the mask material to an etchant to form a pattern of voids in the exposed mask material Mask formation method comprising a. The method of claim 40, Providing a pattern of spacers includes performing a pitch multiplication. The method of claim 40, Providing a pattern of spacers comprises providing a plurality of freestanding spacers. The method of claim 40, Providing a pattern of spacers comprises providing spacers on the sidewalls of the mandrel. The method of claim 43, Removing the mandrel after exposing the mask material. The method of claim 44, Depositing a second layer of mask material after removing the mandrels. The method of claim 45, Self-segregating mask material portions of the second layer of mask material, thereby forming a pattern defined by the mask material portions of the second layer of mask material; Magnetic separation occurs at a volume previously occupied by the mandrels. The method of claim 40, Converting the homogeneous film includes promoting self-separation of chemical species forming the mask prior to exposing the mask material, and promoting the magnetic separation comprises organizing the mask material into domains. Wherein each of said domains is formed predominantly from different portions forming said species. The method of claim 47, Chemical species are block copolymers, the portions are blocks forming the copolymer and exposing the mask material to an etchant selectively removes the block species forming the block copolymers. The method of claim 48, The homogeneous mask material has a sufficient thickness to allow vertical thin plates to be formed in the mask material. The method of claim 48, The homogeneous mask material has a sufficient thickness to allow vertical cylinders to be formed in the mask material. The method of claim 40, Exposing the mask material to the etchant comprises performing a dry etch. The method of claim 40, Exposing the mask material to the etchant comprises performing a wet etch. The method of claim 52, wherein The etching agent comprises a mask containing acetic acid (acetic acid). The method of claim 40, And the remaining mask material comprises lines having a critical dimension of about 50 nm or less. The method of claim 54, And the critical dimension is about 30 nm or less. The method of claim 55, And the critical dimension is about 20 nm or less. As a semiconductor processing method, Forming a first set of block domains over a semiconductor substrate, the first set comprising a plurality of separate groups of block domains, each group comprising a plurality of block domains, wherein the block domains substantially block Formed by like blocks of the copolymer; And Subsequently forming a second set of block domains in space between the separated groups of block domains Semiconductor processing method comprising a. The method of claim 57, Forming the first set includes: Providing a plurality of separate guides for copolymer alignment on the semiconductor substrate; Depositing a first layer of block copolymers in the spaces between the guides; And Forming said first set of block domains in said spaces from said block copolymers Semiconductor processing method comprising a. The method of claim 58, Forming the block domains comprises annealing the block copolymers. The method of claim 58, Transferring the pattern formed by the first set of block domains to an underlying hardmark layer to define features in the hardmask layer. The method of claim 60, Depositing a filler material around and on the features in the hardmask layer. 62. The method of claim 61, And partially removing the filler material to expose the separated guides. The method of claim 62, Partially removing the filler material comprises performing a chemical mechanical polishing (CMP) process. The method of claim 62, Partially removing the filler material comprises performing an etch back process. The method of claim 58, Exposing the guides to an etchant to open the central regions between the edges of the guides to form spaces between the separated groups of block domains. The method of claim 65, Prior to forming the second set of block domains in the spaces, depositing a second layer of block copolymers in the spaces. 67. The method of claim 66, The first and second layers of block copolymers comprise the same block copolymer. The method of claim 67, Wherein said block copolymer is formed of blocks of polystyrene and polymethylmethacrylate. 67. The method of claim 66, Wherein the guides comprise spacers disposed on respective sidewalls of the plurality of separate mandrels. 67. The method of claim 66, Exposing the guides to an etchant comprises selectively removing the mandrels. 67. The method of claim 66, Transferring the pattern formed by the second set of block domains to an underlying hardmask layer. 67. The method of claim 66, Transferring the pattern formed by the first and second set of block domains to a lower substrate. 67. The method of claim 66, Wherein said first set of block domains forms features selected from the group consisting of vertical thin plates, isolated pillars, or vertical cylinders. The method of claim 73, And said second set of block domains forms features selected from the group consisting of vertical thin plates, isolated pillars, or vertical cylinders. The method of claim 74, wherein Wherein said first and second set of block domains form a feature of the same kind. A partially manufactured integrated circuit, A plurality of guides for copolymer alignment covering the semiconductor substrate, the guides having a pitch of about 200 nm or less; And Block copolymers disposed between the plurality of copolymer guides Partially manufactured integrated circuit comprising a. 77. The method of claim 76, Wherein said guides for copolymer alignment are pitch multiplied spacers. 77. The method of claim 76, Wherein the pitch is about 100 nm or less. 77. The method of claim 76, Wherein said block copolymers are formed of two block types. The method of claim 79, Wherein the blocks define lines having a critical dimension of about 50 nm or less. The method of claim 80, Wherein the critical dimension is about 30 nm or less. 82. The method of claim 81 wherein Wherein the critical dimension is about 20 nm or less. The method of claim 79, Wherein said block portions comprise polymethylmethacrylate. The method of claim 79, And the block portions comprise polystyrene. 77. The method of claim 76, And the guides comprise silicon. 86. The method of claim 85, And the guides comprise silicon oxide.

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