CN111081534B - Method for forming semiconductor nanowire - Google Patents

Method for forming semiconductor nanowire Download PDF

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CN111081534B
CN111081534B CN201911360929.4A CN201911360929A CN111081534B CN 111081534 B CN111081534 B CN 111081534B CN 201911360929 A CN201911360929 A CN 201911360929A CN 111081534 B CN111081534 B CN 111081534B
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hard mask
mask layer
patterned
assembly
self
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CN111081534A (en
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李艳丽
伍强
杨渝书
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Shanghai IC R&D Center Co Ltd
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract

The invention provides a method for forming semiconductor nanowires, which comprises the steps of preparing periodically arranged island structures with uniform sizes through a guiding self-assembly process and corresponding photoetching and etching processes, and annealing the island structures, so that a catalyst layer in the island structures can catalyze semiconductor substrates in the island structures to form semiconductor nanowires with uniform thickness and ordered arrangement.

Description

Method for forming semiconductor nanowire
Technical Field
The invention relates to the field of semiconductors, in particular to a method for forming semiconductor nanowires.
Background
In recent years, with continuous research and study of the field of nanotechnology, materials with one-dimensional nanostructures, such as semiconductor nanowires, attract more and more eyeballs. The semiconductor nanowire has the characteristics of obvious quantum effect, ultra-large specific surface area and the like, and has good application prospects in the fields of MOS devices, sensors and the like.
Conventional semiconductor nanowires, such as silicon nanowires, are formed by catalyst growth of silicon nanowires by growing a layer of Ni on a silicon substrate, which at high temperatures liquefies and catalyzes the substrate silicon to form silicon nanowires. However, due to the influence of uniformity of the Ni film, the size of Ni at the time of liquefaction (i.e., the size of Ni-rich silicide formed by mutual dissolution of Ni and silicon on the silicon substrate) is not completely uniform and regularly arranged, so that the grown nanowires are uneven in thickness and disordered in arrangement.
Disclosure of Invention
The invention aims to provide a method for forming semiconductor nanowires, which is used for preparing island structures which are periodically arranged and uniform in size, and forming semiconductor nanowires which are uniform in thickness and orderly arranged under the actions of annealing and catalysis.
In order to solve the technical problems, the invention provides a method for forming a semiconductor nanowire, which comprises the following steps:
step S1: providing a semiconductor substrate, and sequentially forming a catalyst layer, a first hard mask layer and a patterned first guide self-assembly thereon;
step S2: etching the first hard mask layer by taking the patterned first guide self-assembly as a mask, wherein the patterned first hard mask layer is provided with a first groove, and a second hard mask layer with a material different from that of the first hard mask layer is filled in the first groove;
step S3: forming a third hard mask layer and a patterned second guide self-assembly layer above the first hard mask layer and the second hard mask layer in sequence, wherein the second guide self-assembly pattern and the first guide self-assembly pattern are overlapped with each other, and the third hard mask layer is made of a material different from the first hard mask layer and the second hard mask layer;
step S4: etching the third hard mask layer by taking the patterned second guide self-assembly as a mask to form a patterned third hard mask layer, and etching the second hard mask layer and the first hard mask layer by taking the patterned third hard mask layer as a mask to re-pattern the second hard mask layer and the first hard mask layer;
step S5: removing the third hard mask layer and removing the second hard mask layer or the first hard mask layer to form a mask pattern layer;
step S6: etching the catalyst layer and the semiconductor substrate by taking the mask pattern layer as a mask to form an island-shaped structure;
step S7: annealing the island structure to enable the catalyst layer in the island structure to catalyze the semiconductor substrate in the island structure to form nanowires.
Optionally, in the method for forming a semiconductor nanowire, the step of forming the patterned first directed self-assembly on the first hard mask layer includes:
step S11: forming a first photoresist layer on the first hard mask layer;
step S12: photoetching the first photoresist layer to form a patterned first photoresist layer, wherein the patterned first photoresist layer is provided with a second groove;
step S13: filling a first block copolymer in the second groove, and enabling the first block copolymer to perform self-assembly so as to form first guiding self-assembly with at least two structures;
step S14: and removing part of the structure in the first guiding self-assembly to form the patterned first guiding self-assembly.
Optionally, in the method for forming a semiconductor nanowire, the step of forming the patterned second directed self-assembly on the third hard mask layer includes:
step S31: forming a second photoresist layer on the third hard mask layer;
step S32: photoetching the second photoresist layer to form a patterned second photoresist layer, wherein the patterned second photoresist layer is provided with a third groove;
step S33: filling a second block copolymer in the third groove, and enabling the second block copolymer to perform self-assembly so as to form second guiding self-assembly with at least two structures;
step S34: and removing part of the structure in the second guiding self-assembly to form the patterned second guiding self-assembly.
Optionally, in the method for forming a semiconductor nanowire, a certain angle exists between the patterned first directed self-assembly and the patterned second directed self-assembly, and the range of the angle is: 0-90 deg. and not 0 deg..
Optionally, in the method for forming a semiconductor nanowire, a machine for forming the patterned first photoresist layer and the patterned second photoresist layer includes a KrF, arF or I-line lithography machine.
Optionally, in the method for forming a semiconductor nanowire, the method for removing the partial structure in the first directed self-assembly and the method for removing the partial structure in the second directed self-assembly include dry etching, and the gas of the dry etching includes O 2 。
Optionally, in the method for forming a semiconductor nanowire, the semiconductor substrate is made of at least one of Si, ge, sn, se, te and B.
Optionally, in the method for forming a semiconductor nanowire, the material of the catalyst layer is at least one of Au, ni, co, ti, in and Fe.
Optionally, in the method for forming a semiconductor nanowire, the island-shaped structure is a structure with periodic arrangement and uniform size.
Optionally, in the method for forming a semiconductor nanowire, in step S7, the annealing temperature is 1000 ℃ to 1200 ℃, and the annealing process is performed under a nitrogen and/or inert gas environment.
In summary, the present invention provides a method for forming a semiconductor nanowire, which forms a first guiding self-assembled pattern and a second guiding self-assembled pattern that overlap each other through corresponding photolithography and guiding self-assembly processes, then prepares an island structure with periodic arrangement and uniform size through corresponding etching processes, and anneals the island structure, so that a catalyst layer in the island structure can catalyze a semiconductor substrate in the island structure to form semiconductor nanowires with uniform thickness and ordered arrangement. Since the island structures are uniform in size such that the amount of catalyst present in each of the island structures is substantially the same, the catalyst-rich semiconductor compound formed during annealing is uniform in size; and the island structures are periodically arranged, so that the formed semiconductor compounds rich in the catalyst are also periodically arranged, and finally the semiconductor nanowires with uniform thickness and ordered arrangement can be formed.
Drawings
FIG. 1 is a microscopic image of a silicon nanowire;
FIG. 2 is a flow chart of a method for forming semiconductor nanowires according to an embodiment of the invention;
FIGS. 3 a-3 d are schematic diagrams illustrating a first patterned directed self-assembly forming process according to an embodiment of the present invention;
FIGS. 4 a-4 b are cross-sectional and perspective views of a first hard mask layer structure patterned in accordance with one embodiment of the present invention;
FIGS. 5 a-5 b are cross-sectional and perspective views of a second hard mask layer structure formed in accordance with one embodiment of the present invention;
FIGS. 6 a-6 d are schematic diagrams illustrating a process for forming a patterned second-oriented self-assembly according to one embodiment of the present invention;
FIGS. 7 a-7 b are cross-sectional and perspective views of a patterned third hard mask layer structure in accordance with one embodiment of the present invention;
FIGS. 8-10 are schematic views illustrating a process for forming island structures according to an embodiment of the invention;
FIGS. 11 a-11 c are schematic diagrams illustrating a process of catalyzing islands of a semiconductor substrate to generate semiconductor nanowires at a high temperature using a catalyst island in accordance with one embodiment of the present invention;
wherein in fig. 3 a-11 c:
10-semiconductor substrate, 101-semiconductor substrate island, 102-nanowire mandrel, 103-nanowire shell, 104-catalyst, 20-catalyst layer, 201-catalyst island, 30-first hard mask layer, 301-patterned first hard mask layer, 302-second patterned first hard mask layer, 40-patterned first photoresist layer, 41-patterned second photoresist layer, 50-first block copolymer, 51-second block copolymer, 501-first guided self-assembled hydrophobic portion, 502-first guided self-assembled hydrophilic portion, 511-second guided self-assembled hydrophobic portion, 512-second guided self-assembled hydrophilic portion, 60-second hard mask layer, 601-patterned second hard mask layer, 70-third hard mask layer, 701-patterned third hard mask layer.
Detailed Description
Conventional catalysts grow semiconductor nanowires, such as silicon nanowires, by growing a layer of Ni on a silicon substrate, which at high temperatures liquefies and catalyzes the substrate silicon to form silicon nanowires. However, due to the influence of uniformity of the Ni film, the size of Ni at the time of liquefaction (i.e., the size of Ni-rich silicide formed by mutual dissolution of Ni and silicon on the silicon substrate) is not completely uniform and regularly arranged, so that the grown nanowires are uneven in thickness and disordered in arrangement, see fig. 1.
In order to prepare the island-shaped structure which is periodically arranged and uniform in size, and form the semiconductor nanowires with uniform thickness and ordered arrangement under the actions of annealing and catalysis, the invention provides a method for forming the semiconductor nanowires.
Referring to fig. 2, the method for forming the semiconductor nanowire includes:
step S1: providing a semiconductor substrate, and sequentially forming a catalyst layer, a first hard mask layer and a patterned first guide self-assembly thereon;
step S2: etching the first hard mask layer by taking the patterned first guide self-assembly as a mask, wherein the patterned first hard mask layer is provided with a first groove, and a second hard mask layer with a material different from that of the first hard mask layer is filled in the first groove;
step S3: forming a third hard mask layer and a patterned second directed self-assembly over the first hard mask layer and the second hard mask layer, the second directed self-assembled pattern and the first directed self-assembled pattern overlapping each other, the third hard mask layer being of a different material than the first hard mask layer and the second hard mask layer;
step S4: etching the third hard mask layer by taking the patterned second guide self-assembly as a mask to form a patterned third hard mask layer, and etching the second hard mask layer and the first hard mask layer by taking the patterned third hard mask layer as a mask to re-pattern the second hard mask layer and the first hard mask layer;
step S5: removing the third hard mask layer and removing the second hard mask layer or the first hard mask layer to form a mask pattern layer;
step S6: etching the catalyst layer and the semiconductor substrate by taking the mask pattern layer as a mask to form an island-shaped structure;
step S7: annealing the island structure to enable the catalyst layer in the island structure to catalyze the semiconductor substrate in the island structure to form nanowires.
Referring to fig. 3a, in step S1, a semiconductor substrate 10 is first provided, wherein the material of the semiconductor substrate 10 may be at least one of Si, ge, sn, se, te and B, etc., preferably Si, i.e. the semiconductor substrate 10 is preferably a Si substrate. The catalyst layer 20 is formed on the upper surface of the semiconductor substrate 10, preferably by physical deposition, and more preferably by laser-induced plasma physical deposition. The material of the catalyst layer 20 may be at least one of Au, ni, co, ti, in and Fe, etc., and the thickness is preferably 10nm to 50nm.
With continued reference to fig. 3a, in step S1, a first hard mask layer 30 is formed on the upper surface of the catalyst layer 20, where the forming method includes physical deposition or chemical deposition, and the material of the first hard mask layer 30 is preferably SiN (silicon nitride), and the thickness is preferably 25nm to 60nm.
With continued reference to fig. 3a, in step S1, a patterned first directed self-assembly is then formed over the first hard mask layer 30. The forming process of the patterned first guiding self-assembly comprises the following steps:
step S11: forming a first photoresist layer on the first hard mask layer 30;
step S12: photoetching the first photoresist layer to form a patterned first photoresist layer 40, wherein the patterned first photoresist layer 40 is provided with a second groove;
step S13: filling a first block copolymer 50 in the second trench, and self-assembling the first block copolymer 50 to form a first guided self-assembly having at least two structures;
step S14: and removing part of the structure in the first guiding self-assembly to form the patterned first guiding self-assembly.
With continued reference to fig. 3a, in step S11, a first photoresist layer is formed on the upper surface of the first hard mask layer 30 by spin coating; in step S12, the first photoresist layer is subjected to photolithography exposure to form a patterned first photoresist layer 40, i.e. the first photoresist layer is provided with a second trench, and the second trench may be a trench with a larger size, and the size may range from several tens of nanometers to several micrometers. The photoetching can be performed by adopting an I-line, krF or ArF photoetching machine according to the size requirement of the second groove.
Referring to fig. 3b and 3c, in step S13, the second trench is filled with a first block copolymer 50, and the first block copolymer 50 may include a hydrophobic portion and a hydrophilic portion, such as PS-b-PMMA (where PS is Polystyrene, polystyrene; PMMA is Polymethyl methacrylate, polymethyl methacrylate), where PS is a hydrophobic portion, PMMA is a hydrophilic portion, and the patterned first photoresist layer 40 is hydrophobic. The first block copolymer 50 is self-assembled to form a first directed self-assembly having at least two structures, wherein the method of self-assembling the first block copolymer 50 is preferably heating. For example, during heating, the hydrophobic portions (e.g., PS) and the hydrophilic portions (e.g., PMMA) begin to self-assemble to form a first guided self-assembly, the hydrophobic portions (e.g., PS) will preferentially be adjacent to the hydrophobic patterned first photoresist layer 40, the hydrophilic portions (e.g., PMMA) will be between the hydrophobic portions (e.g., PS), and finally the first guided self-assembled hydrophobic portions 501 and the first guided self-assembled hydrophilic portions 502 will be formed.
Referring to fig. 3d, in step S14, a portion of the structure in the first directed self-assembly is removed to form the patterned first directed self-assembly. The method of removing can be ultraviolet exposure or etching, preferably selective etching, further, the selective etching is preferably dry etching, and the etching gas is preferably O 2 I.e. by O 2 And removing part of the structure in the first guiding self-assembly. While the partial structure in the first directed self-assembly refers to the first directed self-assembled hydrophilic portion 502, i.e., by selectionAnd (3) etching to remove the first guiding self-assembled hydrophilic part 502, and reserving the first guiding self-assembled hydrophobic part 501 to form a patterned first guiding self-assembly. The patterned first-guide self-assembly may be formed to a resolution of tens of nanometers, the line width (the first-guide self-assembly hydrophobic portion 501, for example, PS) may be formed to a resolution of tens of nanometers, the line width may be adjusted according to the requirements of the nanowire size, the minimum line width used in this embodiment is 30nm, and the size and line width of the trench in the patterned first-guide self-assembly may be 1:1 or not.
Referring to fig. 4a and 4b, in step S2, first, the patterned first hard mask layer 30 is etched to form a patterned first hard mask layer 301 using the patterned first guide self-assembly as a mask, the patterned first hard mask layer 301 having a first trench, and then, a mask material having a material different from that of the first hard mask layer is deposited on the surfaces of the patterned first hard mask layer 301 and the first trench by a chemical vapor deposition, a sputter deposition, or the like process until the deposited material fills each first trench; next, the filled material is planarized to the upper surface of the first mask layer 301 by a chemical mechanical polishing or the like process to form a second hard mask layer 60 filled in each of the first trenches (see fig. 5a and 5 b). I.e. the patterned first directed self-assembled pattern is transferred onto the first hard mask 50 by etching, and then the first trench is filled with a second hard mask layer 60 of a material different from the first hard mask layer 30, the material of the second hard mask layer 60 preferably being SiO 2 Provision is made for self-assembly of the patterned second guide. At this time, the first hard mask layer 30 and the second hard mask layer 60 are elongated.
Referring to fig. 6a to 6d, in step S3, a third hard mask layer 70 and a patterned second guide self-assembly are formed over the first hard mask layer 30 and the second hard mask layer 60, and the second guide self-assembly pattern and the first guide self-assembly pattern overlap each other, and the third hard mask layer 70 is made of a material different from the first hard mask layer 30 and the second hard mask layer 60. The third hard mask layer 70 is preferably APF (advanced patterning film ), and is preferably formed by chemical vapor deposition as a material having an etching ratio selective to the material of the first hard mask layer 30 and the second hard mask layer 60. A patterned second directed self-assembly is then formed on the upper surface of the third hard mask layer 70. The forming method of the patterned second guiding self-assembly comprises the following steps:
step S31: forming a second photoresist layer on the third hard mask layer 70;
step S32: photoetching the second photoresist layer to form a patterned second photoresist layer 41, wherein the patterned second photoresist layer 41 is provided with a third groove;
step S33: filling a second block copolymer 51 in the third trench, and self-assembling the second block copolymer 51 to form a second guided self-assembly having at least two structures;
step S34: and removing part of the structure in the second guiding self-assembly to form the patterned second guiding self-assembly.
Referring to fig. 6a, first, in step S31, a photoresist layer is coated on the third hard mask layer 70 to form a second photoresist layer; next, in step S32, the second photoresist layer is subjected to photolithography to form a patterned second photoresist layer 41 having a third trench, where the photolithography may use a photolithography machine such as I-line, krF, arF, or the like according to the size requirement of the third trench. The third grooves may have a size ranging from several tens of nanometers to several micrometers, and may be the same as or different from the second grooves.
Referring to fig. 6b and 6c, in step S33, the second block copolymer 51 is filled in the third trench, and the second block copolymer 51 may include a hydrophobic portion and a hydrophilic portion, for example, PS-b-PMMA, which may be the same as or different from the first block copolymer 50. The method for self-assembling the second block copolymer 51 is preferably heating, for example, during heating, the hydrophilic portion and the hydrophobic portion start to self-assemble to form a second self-assembled guide, the hydrophobic portion is preferably close to the hydrophobic patterned second photoresist layer 41, the hydrophilic portion is located between the hydrophobic portions, and finally the second self-assembled guide is formed with at least two structures, for example, the two structures include the second self-assembled guide hydrophobic portion 511 and the second self-assembled guide hydrophilic portion 512.
Referring to fig. 6d, in step S34, a portion of the structure in the second directed self-assembly is removed to form the patterned second directed self-assembly. The method of removing can be ultraviolet exposure or etching, preferably selective etching, further, the selective etching is preferably dry etching, and the etching gas is preferably O 2 . The partial structure in the second directed self-assembly refers to the second directed self-assembled hydrophilic portion 512, i.e. the second directed self-assembled hydrophilic portion 512 is removed by selective etching, and the second directed self-assembled hydrophobic portion 511 is reserved, so as to form a patterned second directed self-assembly. The patterned second-guide self-assembly may be formed to a resolution of tens of nanometers, the line width (second-guide self-assembly hydrophobic portion 511, for example, PS) may be formed to a resolution of tens of nanometers, the line width may be adjusted according to the requirements of the nanowire size, the minimum line width used in this embodiment is 30nm, and the size and line width of the trench in the patterned second-guide self-assembly may be 1:1 or not. And the second self-assembled pattern and the first self-assembled pattern overlap each other, i.e. a certain angle exists between the second self-assembled pattern and the first self-assembled pattern, and the angle ranges from 0 ° to 90 ° and is not 0 °, preferably 90 °, i.e. the second self-assembled pattern is preferably perpendicular to the first self-assembled pattern. The period and line size (line width) of the patterned second guide self-assembled pattern and the patterned first guide self-assembled pattern may be identical, or may be identical, that is, the period and line size of the two patterns may be identical, or may be identical.
Referring to fig. 7a and 7b, in step S4, the first pattern is patternedThe second directed self-assembly is used as a mask to etch the third hard mask layer 70 to form a patterned third hard mask layer 701, i.e., the patterned second directed self-assembled pattern is transferred to the third hard mask layer 70 by etching. Referring to fig. 8, the second hard mask layer 60 and the patterned first hard mask layer 301 are etched by using the patterned third hard mask layer 701 as a mask, so as to pattern the second hard mask layer and the first hard mask layer again, i.e. form a second patterned first hard mask layer 302 and a patterned second hard mask layer 601, where the second patterned first hard mask layer 302 and the patterned second hard mask layer 601 are all cut off from the stripe structure at multiple positions to form an island structure. The material of the second patterned first hard mask layer 302 is preferably SiN and the material of the second hard mask layer 60 is preferably SiO 2 The third hard mask layer 70 is preferably APF because of SiN and SiO 2 The selectivity to APF can be tuned to be uniform so that the pattern on the third hard mask layer 70 can be transferred to the patterned first hard mask layer 301 and second hard mask layer 60 by etching.
Referring to fig. 9, in step S5, the third hard mask layer 70 is removed, and the second hard mask layer 60 or the first hard mask layer 30 is removed to form a mask pattern layer. The removal method is preferably a wet etch, after which only the second patterned hard mask layer 302 or the patterned second hard mask layer 601 remains.
Referring to fig. 10, in step S6, the catalyst layer 20 and a portion of the depth of the semiconductor substrate 10 are etched using the mask pattern layer as a mask to form an island structure. The etching is preferably dry etching, and an etching gas, such as Cl, is selected by using a selectivity ratio among the mask pattern layer, the catalyst layer 20, and the semiconductor substrate 10 2 . I.e., the pattern of the mask pattern layer is transferred onto the catalyst layer 20 and the semiconductor substrate 10 by etching, and finally an island-like structure, i.e., catalyst islands 201+ semiconductor substrate islands 101, is formed. The semiconductor substrate island 101 is etched to a partial depth of the semiconductor substrate 10, the partial depth being 100nm to 500nm, and the semiconductor substrate island being left in the etched partial depthPart of the future. The island-shaped structures are small islands which are arranged periodically and have uniform sizes, namely a periodic island-shaped structure array is formed. The periodic island-like structure array can be a square periodic array, a hexagonal periodic array or any array between the square periodic array and the hexagonal periodic array.
Referring to fig. 11a to 11c, in step S7, the island structure is annealed so that a catalyst layer in the island structure can catalyze a semiconductor substrate in the island structure to form nanowires. I.e. the island structure is annealed at high temperature to form a semiconductor nanowire. The annealing temperature ranges from 1000 ℃ to 1200 ℃, and the annealing process is performed in a nitrogen and/or inert gas environment, wherein the inert gas comprises helium, argon or the like. In the annealing process, the catalyst layer in the island structure is first mutually dissolved with a part of the depth of the semiconductor substrate (namely, the semiconductor substrate in the island structure) to form a catalyst-rich semiconductor compound, and the semiconductor nanowires (30 nm-100 nm) which are periodically arranged and uniform in size can be generated after continuous annealing, wherein the top ends of the nanowires are catalysts 104, the nanowire shell layers 103 are non-luminous oxides, and the nanowire core shaft 102 is a luminous semiconductor nanocrystal (< 5 nm).
Since the island structures are formed to be uniform in size, that is, the catalyst islands 201 in the island structures are uniform in size so that the amount of catalyst present in each of the island structures is substantially the same, the catalyst-rich semiconductor compound formed is uniform in size during annealing. Since the size of the catalyst-rich semiconductor compound formed is critical to the thickness of the semiconductor nanowire, the larger the size of the catalyst-rich semiconductor compound, the thicker the semiconductor nanowire formed, and in the present invention, the size of the catalyst-rich semiconductor compound formed is uniform, and thus, the thickness of the finally formed semiconductor nanowire is also uniform. And the island structures are arranged periodically, so that the finally formed semiconductor nanowires are also arranged periodically, namely the semiconductor nanowires with uniform thickness and ordered arrangement are finally formed.
The patterned first guide self-assembly and the patterned second guide self-assembly formed in the invention can reach the resolution of tens of nanometers, namely, compared with the traditional process, the guide self-assembly can form smaller size at one time, thereby forming smaller catalyst islands 201 and finally catalyzing and generating finer nanowires.
Therefore, the method for forming the semiconductor nanowire prepares the island-shaped structure which is periodically arranged and uniform in size through the guiding self-assembly process and the corresponding photoetching and etching process, catalyzes the semiconductor substrate at high temperature, and forms the semiconductor nanowire with uniform thickness and ordered arrangement.
Finally, it should be noted that the above-mentioned embodiments are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Equivalent changes and modifications are intended to be within the scope of the present invention as defined in the appended claims.

Claims (9)

1. A method of forming a semiconductor nanowire, comprising the steps of:
step S1: providing a semiconductor substrate, and sequentially forming a catalyst layer, a first hard mask layer and a patterned first directed self-assembly thereon, wherein the step of forming the patterned first directed self-assembly on the first hard mask layer comprises: step S11: forming a first photoresist layer on the first hard mask layer; step S12: photoetching the first photoresist layer to form a patterned first photoresist layer, wherein the patterned first photoresist layer is provided with a second groove; step S13: filling a first block copolymer in the second groove, and enabling the first block copolymer to perform self-assembly so as to form first guiding self-assembly with at least two structures; step S14: removing a portion of the structure in the first directed self-assembly to form the patterned first directed self-assembly;
step S2: etching the first hard mask layer by taking the patterned first guide self-assembly as a mask, wherein the patterned first hard mask layer is provided with a first groove, and a second hard mask layer with a material different from that of the first hard mask layer is filled in the first groove;
step S3: forming a third hard mask layer and a patterned second guide self-assembly layer above the first hard mask layer and the second hard mask layer in sequence, wherein the second guide self-assembly pattern and the first guide self-assembly pattern are overlapped with each other, and the third hard mask layer is made of a material different from the first hard mask layer and the second hard mask layer;
step S4: etching the third hard mask layer by taking the patterned second guide self-assembly as a mask to form a patterned third hard mask layer, and etching the second hard mask layer and the first hard mask layer by taking the patterned third hard mask layer as a mask to re-pattern the second hard mask layer and the first hard mask layer;
step S5: removing the third hard mask layer and removing the second hard mask layer or the first hard mask layer to form a mask pattern layer;
step S6: etching the catalyst layer and the semiconductor substrate by taking the mask pattern layer as a mask to form an island-shaped structure;
step S7: annealing the island structure to enable the catalyst layer in the island structure to catalyze the semiconductor substrate in the island structure to form nanowires.
2. The method of forming a semiconductor nanowire of claim 1, wherein forming the patterned second directed self-assembly on the third hard mask layer comprises:
step S31: forming a second photoresist layer on the third hard mask layer;
step S32: photoetching the second photoresist layer to form a patterned second photoresist layer, wherein the patterned second photoresist layer is provided with a third groove;
step S33: filling a second block copolymer in the third groove, and enabling the second block copolymer to perform self-assembly so as to form second guiding self-assembly with at least two structures;
step S34: and removing part of the structure in the second guiding self-assembly to form the patterned second guiding self-assembly.
3. The method of forming a semiconductor nanowire of claim 1, wherein an angle exists between the patterned first directed self-assembly and the patterned second directed self-assembly, the angle ranging from: 0-90 deg. and not 0 deg..
4. The method of forming a semiconductor nanowire as claimed in claim 1 or 2, wherein the stage for forming the patterned first photoresist layer and the patterned second photoresist layer comprises a KrF, arF, or I-line lithography machine.
5. The method of forming a semiconductor nanowire as claimed in claim 1 or 2, wherein the method of removing a portion of the structure in the first directed self-assembly and removing a portion of the structure in the second directed self-assembly comprises a dry etch, the dry etch gas comprising O2.
6. The method of forming a semiconductor nanowire of claim 1, wherein the semiconductor substrate is at least one of Si, ge, sn, se, te and B.
7. The method of forming a semiconductor nanowire as claimed in claim 1, wherein the material of the catalyst layer is at least one of Au, ni, co, ti, in and Fe.
8. The method of forming a semiconductor nanowire as recited in claim 1, wherein said island-like structure is a periodically arranged, uniform-sized structure.
9. The method of forming a semiconductor nanowire as claimed in claim 1, wherein in the step S7, the annealing is performed at a temperature of 1000 ℃ to 1200 ℃ under nitrogen and/or inert gas atmosphere.
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CN105239156A (en) * 2015-09-15 2016-01-13 南京大学 Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration

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US8207028B2 (en) * 2008-01-22 2012-06-26 International Business Machines Corporation Two-dimensional patterning employing self-assembled material
US9299609B2 (en) * 2014-07-23 2016-03-29 Seagate Technology Llc Hard-mask defined bit pattern substrate

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Publication number Priority date Publication date Assignee Title
JP2004122283A (en) * 2002-10-01 2004-04-22 Japan Science & Technology Corp Manufacturing method of regular arrangement microstructure of nano size
CN105239156A (en) * 2015-09-15 2016-01-13 南京大学 Method for preparing plane semiconductor nanowire through epitaxial orientated growth, transfer and integration

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