CN111124300A

CN111124300A - Method and device for improving access efficiency of SSD DDR4, computer equipment and storage medium

Info

Publication number: CN111124300A
Application number: CN201911303637.7A
Authority: CN
Inventors: 李湘锦; 张鹏; 王宏伟
Original assignee: Shenzhen Union Memory Information System Co Ltd
Current assignee: Shenzhen Union Memory Information System Co Ltd
Priority date: 2019-12-17
Filing date: 2019-12-17
Publication date: 2020-05-08

Abstract

The invention relates to a method, a device, computer equipment and a storage medium for improving the access efficiency of SSD DDR 4; the method comprises the following steps: dividing the DDR4 according to a matrix with a set size; inverting the row and column of the divided matrix; the DDR4 with the rows and columns reversed is read and written. According to the DDR4 access method, DDR4 is divided according to the matrix with the set size, then row and column inversion is carried out, then reading and writing are carried out, frequent row changing operation is reduced, accordingly, the DDR4 access efficiency is improved, and the requirements can be better met.

Description

Method and device for improving access efficiency of SSD DDR4, computer equipment and storage medium

Technical Field

The invention relates to the technical field of solid-state storage access, in particular to a method and a device for improving SSD DDR4 access efficiency, a computer device and a storage medium.

Background

In an application scenario of the SSD, all the scenario accesses DDR are sequential read and sequential write, and some scenarios may have skip read (a large number of sequential write and a small number of skip read) and skip write (a large number of read and a small number of skip write), and the access efficiency of the DDR may be greatly reduced due to such access.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a method, a device, a computer device and a storage medium for improving the access efficiency of an SSD DDR 4.

In order to achieve the purpose, the invention adopts the following technical scheme:

the method for improving the access efficiency of the SSD DDR4 comprises the following steps:

dividing the DDR4 according to a matrix with a set size;

inverting the row and column of the divided matrix;

the DDR4 with the rows and columns reversed is read and written.

The further technical scheme is as follows: the DDR4 includes 1024 rows by 1024 columns.

The further technical scheme is as follows: the matrix of the set size is obtained by dividing 1024 rows × 1024 columns into 256 rows × 256 columns, and the total number is 16.

The further technical scheme is as follows: in the "reading and writing to the DDR4 with the row and column reversed", the reading and writing includes sequential reading, sequential writing, skip reading, or skip writing.

An apparatus to improve SSD DDR4 access efficiency, comprising: a dividing unit, an inverting unit, and a reading and writing unit;

the dividing unit is used for dividing the DDR4 according to a matrix with a set size;

the inversion unit is used for inverting the row and the column of the divided matrix;

and the read-write unit is used for reading and writing the DDR4 with the row and the column reversed.

The further technical scheme is as follows: in the read-write unit, the reading and writing includes sequential reading, sequential writing, skip reading, or skip writing.

A computer device comprising a memory having stored thereon a computer program and a processor which when executed implements a method of improving SSD DDR4 access efficiency as described above.

A storage medium storing a computer program comprising program instructions which, when executed by a processor, may implement a method of improving SSD DDR4 access efficiency as described above.

Compared with the prior art, the invention has the beneficial effects that: by dividing the DDR4 according to a matrix with a set size, then reversing rows and columns, and then performing reading and writing, frequent line change operations are reduced, so that the access efficiency of the DDR4 is improved, and the requirements can be better met.

The invention is further described below with reference to the accompanying drawings and specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic distribution diagram of a DDR4 memory bank;

fig. 2 is a schematic flowchart of a method for improving the access efficiency of the SSD DDR4 according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of DDR4 matrix partitioning and row-column inversion;

FIG. 4 is a schematic diagram of the distribution of DDR4 memory bank divided into 16 parts on average;

FIG. 5 is a schematic diagram of the distribution of DDR4 memory bank remapping after;

fig. 6 is a schematic block diagram of an apparatus for improving access efficiency of the SSD DDR4 according to an embodiment of the present invention;

FIG. 7 is a schematic block diagram of a computer device provided by an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to the embodiments shown in fig. 1 to 7, in which, referring to fig. 1, each row of the DDR4 has 1024 rows, and the number of rows is different according to the capacity, and the read/write mode with the largest performance is sequential read/write:

S0-S1024 are access steps, R0 is line 0, R1023 is line 1023; c0-c1023, columns 0 through 1023; s0: R0(c0-c1023), S2: R1(c0-c1023), S1023: R1023(c0-c 1023); if skip/skip occurs: s0: R0(c0), S2: R1(c0), S1023: R1023(c0), namely, only one data is read and written in each row, which can cause the DDR performance to be greatly reduced.

Referring to fig. 2 to 5, the present invention discloses a method for improving the access efficiency of the SSD DDR4, comprising the following steps:

s1, dividing the DDR4 according to a matrix with a set size;

s2, inverting the row and column of the divided matrix;

s3, the DDR4 with the row and column reversed is read and written.

In this embodiment, the DDR4 includes 1024 rows × 1024 columns.

Referring to fig. 3, the matrix with the set size is obtained by dividing 1024 rows × 1024 columns into 256 rows × 256 columns, counting 16 parts, and inverting the rows and columns.

Wherein in S3, the reading and writing includes sequential reading, sequential writing, skip reading, or skip writing.

Referring to the specific embodiments shown in fig. 4 to 5, before the present solution is adopted: the access is carried out in a mode of 1- >2- >3 … - >8, the line is changed every time, and the efficiency is low; after the scheme is adopted, DDR4 is segmented according to a small matrix, addresses are remapped and then accessed, and the line is changed after 4 times of access, so that the access efficiency is greatly improved.

The present embodiment provides the following analysis, which is not performed before the scheme is adopted: 1. reading the bandwidth of a row sequentially (1024), taking DDR4-1600 as an example: total-tRCD + tCL + tRP + 1024/2-ck (36+512) with a bandwidth of 93.5%; 2. write the bandwidth of a row sequentially (1024), taking DDR4-1600 as an example: total (tRCD + tCWL + tWR + tRP + 1024/2) (45+512) ck, with a bandwidth of 91.9%; 3. skipping 1024 rows of bandwidth, assuming that each row reads 16B for a total of 1024 rows, total is (36+16/2) × 1024, with a bandwidth of 18.2%; after the improvement of the scheme is adopted: 4. reading 16B × 1024, if a method of dividing 16 shares is adopted (or the division can be increased for higher increase, such as 32/64), the total is (36+16 × 4/2) × 256, the bandwidth is 45.07%, and the DDR4 bandwidth is greatly increased; 5. write 16B × 1024, total (45+16 × 4/2) × 256, bandwidth 41.56%, DDR4 bandwidth is greatly increased.

According to the DDR4 access method, DDR4 is divided according to the matrix with the set size, then row and column inversion is carried out, then reading and writing are carried out, frequent row changing operation is reduced, accordingly, the DDR4 access efficiency is improved, extra resource consumption of project strategies is low, control is simple, cost is low, benefits are high, and the requirements can be better met.

Referring to fig. 6, the present invention also discloses a device for improving the access efficiency of the SSD DDR4, including: a dividing unit 10, an inverting unit 20, and a reading and writing unit 30;

the dividing unit 10 is configured to divide the DDR4 according to a matrix with a set size;

the inverting unit 20 is configured to invert rows and columns of the divided matrix;

the read-write unit 30 is used for reading and writing the DDR4 with the row and column reversed.

Wherein the DDR4 includes 1024 rows by 1024 columns.

The matrix of the set size is obtained by dividing 1024 rows × 1024 columns into 256 rows × 256 columns, and the total number is 16.

In the read/write unit 30, the reading and writing includes sequential reading, sequential writing, skip reading, or skip writing.

It should be noted that, as will be clear to those skilled in the art, for the specific implementation process of the above apparatus for improving the access efficiency of the SSD DDR4, reference may be made to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, no further description is provided herein.

The above-described means for improving the access efficiency of the SSD DDR4 may be implemented in the form of a computer program that can be run on a computer device as shown in fig. 7.

Referring to fig. 7, fig. 7 is a schematic block diagram of a computer device according to an embodiment of the present application; the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of a plurality of servers.

Referring to fig. 7, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.

The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer programs 5032 include program instructions that, when executed, cause the processor 502 to perform a method of improving SSD DDR4 access efficiency.

The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.

The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 may be enabled to perform a method for improving the access efficiency of the SSD DDR 4.

The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 7 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

It should be understood that, in the embodiment of the present Application, the Processor 502 may be a Central Processing Unit (CPU), and the Processor 502 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program comprises program instructions that, when executed by a processor, implement the above-described method of improving SSD DDR4 access efficiency.

The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, which can store various computer readable storage media.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.

Claims

1. The method for improving the access efficiency of the SSD DDR4 is characterized by comprising the following steps:

dividing the DDR4 according to a matrix with a set size;

inverting the row and column of the divided matrix;

the DDR4 with the rows and columns reversed is read and written.

2. The method for improving SSD DDR4 access efficiency of claim 1, wherein the DDR4 comprises 1024 rows by 1024 columns.

3. The method for improving the access efficiency of the SSD DDR4 of claim 2, wherein the matrix with the set size is formed by dividing 1024 rows by 1024 columns into 256 rows by 256 columns, and the total number of the matrix is 16.

4. The method for improving the access efficiency of the SSD DDR4 of claim 1, wherein in the "reading and writing the DDR4 with reversed ranks", the reading and writing comprises sequential reading, sequential writing, skip reading, or skip writing.

5. An apparatus for improving SSD DDR4 access efficiency, comprising: a dividing unit, an inverting unit, and a reading and writing unit;

6. The apparatus for improving SSD DDR4 access efficiency of claim 5, wherein the DDR4 comprises 1024 rows by 1024 columns.

7. The apparatus of claim 6, wherein the matrix of the set size is a total of 16 parts of 1024 rows by 1024 columns divided by 256 rows by 256 columns.

8. The apparatus of claim 5, wherein in the read/write unit, reading and writing comprises sequential reading, sequential writing, skip reading, or skip writing.

9. A computer device comprising a memory having stored thereon a computer program and a processor that when executed implements the method of improving SSD DDR4 access efficiency of any of claims 1-4.

10. A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement the method of improving SSD DDR4 access efficiency of any of claims 1-4.