CN106483505A - A kind of general FPGA original position data transposition method of partition - Google Patents
A kind of general FPGA original position data transposition method of partition Download PDFInfo
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- CN106483505A CN106483505A CN201610841829.3A CN201610841829A CN106483505A CN 106483505 A CN106483505 A CN 106483505A CN 201610841829 A CN201610841829 A CN 201610841829A CN 106483505 A CN106483505 A CN 106483505A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/9004—SAR image acquisition techniques
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/0007—Image acquisition
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
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Abstract
The present invention relates to a kind of general FPGA original position data transposition method of partition, the situation that existing matrix original position transposition method covers is not comprehensively it is impossible to be common to various data cases, and do not account for the difficulty of FPGA Project Realization, and FPGA code transplantability is poor.The ratio of distance points M and orientation points N is set up FPGA original position transposition processing method model as standard by the present invention, big matrix division methods are refined, generalization, modular matrix transpose implementation method is proposed on the basis of basic implementation method, various situations can be flexibly applied to, it is easy to weigh FPGA code design difficulty and treatment effeciency, be easy to FPGA engineer applied and code migrating.
Description
Technical field
The present invention relates to a kind of general FPGA original position data transposition method of partition, belong to Space Microwave remote sensing technology neck
Domain.
Background technology
The Project Realization of synthetic aperture radar, needs to complete the high speed storing of big data quantity and real-time processing, current main-stream
FPGA is integrated with a large amount of arithmetic elements and the IP kernel of achievable certain function, in Digital Signal Processing such as complex multiplication, FFT process
In step, tool has great advantage, and can be with parallel processing multichannel data, it has also become the signal processor of synthetic aperture radar
Kernel processor chip.
Real time sar imaging handling process needs the data adjusted the distance successively to orientation to process, complete
Become matrix transpose at least one times.Simplest matrix transpose is based on FPGA internal RAM and realizes, and will lead to the data of storage by distance
Cross address saltus step to read, realize reading by orientation.But because FPGA internal resource is limited, only pass through FPGA internal resource
The buffer size of current high-volume view data cannot be met.
Currently widely use DDR3 SDRAM (third generation double data rate synchronous DRAM) complete data delay
Deposit, DDR3 SRAM has the features such as amount of storage is big, and read-write speed is high.But due to DDR3 SRAM device self-characteristic, frequently
Row address switching can substantially reduce its read-write efficiency, therefore data is stored in line by line DDR3 SRAM again by row read efficiency very
Low, how the data in DDR3 SDRAM being efficiently completed in former memory space transposition as far as possible is Radar Signal Processing imaging
The difficult point that algorithm engineering is realized.
Original position transposition refers to, in the case of being not take up more storages, in former memory space, matrix is completed transposition.Existing
Original position transposition method less, be currently based on the matrix transpose of DDR3 SRAM mainly using carrying out to big matrix dividing, again to drawing
The method that the little square formation separating is sequentially completed transposition, thus reducing DDR3 SRAM row switching times, improves treatment effeciency.But
In practical engineering application, this single division methods can not cover various situations, the unequal matrix for row, column number, draws
The situation of dividing is more, there is no unitized FPGA original position data transposition software module.
Patent《SAR imaging signal processing data transposition method based on FPGA》Data in (publication number 102279386A)
Transposition method is：Factorization algorithm is carried out to the data in DDR2 SRAM, is divided into diagonal pattern matrix-block, symmetrical non-diagonal mould
Each several part matrix-block reading internal memory is completed transposition and is written back by formula matrix-block and asymmetric non-diagonal mode matrix block three class successively
DDR2 SRAM.This matrix division methods can not cover various situations, is not particularly suited for ranks number difference very little or very big
Situation, and this patent is unfavorable for FPGA Project Realization, code for the transposition processing method of symmetrical non-diagonal mode matrix block
Versatility is poor.
Content of the invention
The technology solve problem of the present invention is：Provide a kind of general FPGA original position data transposition method of partition, in conjunction with
FPGA Project Realization feature establishes processing method preference pattern, and the data volume that can neatly be directed to Radar Signal Processing is carried out
Judge, provide most suitable original position transposition method in conjunction with Practical Project situation, unified the FPGA original position number based on DDR3 SRAM
According to the various applicable cases of transposition, solve currently processed method poor universality, be of limited application, software transportability difference etc. lacks
Point, is that the Project Realization of radar Real-time processing has laid key foundation.
The technical solution of the present invention is：
A kind of general FPGA original position data transposition method of partition, as follows as shown in Figure 1：
(1) set up transposition method model
The ratio of distance points M and orientation points N is set up FPGA original position transposition processing method model as standard, just
In balance Project Realization difficulty and treatment effeciency.Propose method model be：
WhenFor basic square formation transposition method；
WhenOrFor method 1；
WhenOrFor method 2；
WhenOrFor method 3；
(2) determine P, Q value
In above-mentioned criterion, P, Q are integer, and meet Value can affect to method 1 and method
2 selection, needs incorporation engineering to realize difficulty and the determination of algorithm process efficiency, for method 1 and method 2, is processing sequential foot
In the case of enough,Value close to 2 be more conducive to systems of selection 2；
(3) basic square formation transposition method
When M, N are equal, using basic square formation transposition method, square formation is divided into the little square formation of L rank.Described little square formation
It is divided into two classes：A class is the square formation on diagonal, successively the data in A class square formation is read into FPGA internal RAM line by line, reads ground
Location redirects, by L, the data reading in RAM, then writes back raw address in DDR3SDRAM line by line；B class is the side symmetrical with regard to diagonal
Battle array, needs every time to read with regard to two symmetrical B class square formations of diagonal to FPGA internal RAM, redirects reading by reading address by L
Data in RAM is respectively completed the transposition of the data within two square formations, and two square formation exchange positions are being write back
DDR3SDRAM；
(4) method 1：Divide square formation
WhenOrWhen, using method 1, data is divided into one with smaller value in M, N is
The square formation of exponent number and a minor matrix, the square formation marking off carries out piecemeal process according to basic square formation transposition method, for many
The data field going out individually is divided into little square formation, one by one read in FPGA internal RAM complete transposition in writing back DDR3 SRAM with original place
The symmetrical position in location；
(5) method 2：Expand square formation
WhenOrWhen, using method 2, data matrix is extended for higher value in M, N be
The square formation of exponent number, then directly carries out piecemeal process according to basic square formation transposition method and completes original position transposition, in subsequent treatment
In ignore the data field of expansion；
(6) method 3：Divide multiple square formations
When M, N difference is more than one times, using method 3, divide the matrix into multiple with smaller value in M, N as exponent number
Square formation, the expanding data of not enough integer square formation is divided into integer, to each square formation directly according to basic square formation transposition side
Method carries out piecemeal process and completes original position transposition.
Compared with the prior art, the invention has the advantages that：
A kind of general FPGA original position data transposition method of partition of the present invention, on the basis of legacy data storage
Carry out data division it is not necessary to additionally take DDR3 SRAM storage, can substantially save memory space, reduce hardware rule
Mould.
Technical scheme (1) sets up transposition method model, first using the ratio of distance points M and orientation points N as mark
Standard establishes FPGA original position transposition processing method model, the FPGA original position data transposition based on DDR3 SRAM for this Unified Model
Various applicable cases, big matrix division methods are refined, beneficial to engineering carry out, solve existing processing method versatility
Differ from the shortcoming it is impossible to meet various application scenarios.
Technical scheme (2) determines the value of P, Q, is easy to designer and weighs FPGA code design at the FPGA software design initial stage
Difficulty and treatment effeciency, provide appropriate method, and compared to existing method, more conducively subsequent software is write.
Four kinds of methods described in technical scheme (3), (4), (5), (6) cover the FPGA original position based on DDR3 SRAM
The various applicable cases of data transposition, overcome that existing patent coverage condition is complete, consider ranks number difference very little or relatively
The shortcoming of big situation；Overcome the incomplete shortcoming of existing method poor universality, implementation method.
Method described in technical scheme (4), (5), (6) by data ranks, make to segment by situation not etc., and passes through square
Various situations are all simplified to the square formation transposition method being easy to Project Realization described in technical scheme (2) by battle array division, therefore exist
In FPGA Project Realization, the data matrix that ranks do not wait can call square formation transposition processing module after division, overcome and work as
Front transposition algorithm engineering realizes the big shortcoming of difficulty, beneficial to the realization of soft project, is easy to code migrating.
Brief description
Fig. 1 realizes schematic diagram for the present invention's；
Fig. 2 is square formation piecemeal transposition method in the present invention；
Fig. 3 is the piecemeal transposition method of method 1 in the present invention；
Fig. 4 is the piecemeal transposition method of method 2 in the present invention；
Fig. 5 is the piecemeal transposition method of method 3 in the present invention.
Specific embodiment
A kind of general FPGA original position data transposition method of partition：
(1) pretreated echo data Pulse by Pulse is sequentially stored into DDR3 SRAM and respectively advances row cache by FPGA, needs to deposit
Arteries and veins group number N needed for enough piece images.
(2) every two field picture distance is substituted into method choice model to the ratio processing points M and orientation process points N to enter
Row judges, described judgment models are：
WhenFor basic square formation transposition method；
WhenOrFor method 1；
WhenOrFor method 2；
WhenOrFor method 3；
(3) incorporation engineering realizes difficulty and algorithm process efficiency determines the value of P, Q, and P, Q are integer, and meets
(4) when M, N are equal, using basic square formation transposition method, as shown in Figure 2.Square formation is divided into the little side of L rank
Battle array, L generally takes 32 or 64.Described little square formation is divided into two classes：A class is the square formation on diagonal, successively by the data in A class square formation
Read into FPGA internal RAM line by line, read address and redirect, by L, the data reading in RAM, then write back original place in DDR3 SDRAM line by line
Location；B class is the square formation symmetrical with regard to diagonal, needs every time to read with regard to two symmetrical B class square formations of diagonal in FPGA
Portion RAM, is respectively completed the transposition of the data within two square formations by reading address and redirecting, by L, the data reading in RAM, by two
Individual square formation exchange position writes back DDR3 SDRAM, writes the position of B_12, write after the internal transposition of B_12 after the internal transposition of such as B_11
Position to B_11；
(5) whenOrUsing method 1, data is divided into one with smaller value in M, N is
The square formation of exponent number and a minor matrix, as shown in figure 3, A is the little square formation on diagonal in the square formation marking off, B is to mark off
Square formation in regard to the symmetrical little square formation of diagonal；A class and B matroid carry out piecemeal according to the square formation transposition method in accompanying drawing 1
Process；Have more after dividing for square formation is partly individually divided into little square formation C, reads in FPGA internal RAM one by one and completes transposition and exist
Write back symmetrical with raw address position in DDR3 SRAM；
(6) whenOrUsing method 2, data matrix is extended for higher value in M, N be
The square formation of exponent number, as shown in figure 4, dotted portion is the data expanding, can directly apply mechanically the square formation transposition side in Fig. 1 after expansion
Method, processes to the A matroid on diagonal with regard to the symmetrical B matroid of diagonal successively, ignores expansion in subsequent treatment
The data field filled.Code module can be processed with directly transplanting square formation transposition during Project Realization.
(7) whenOrWhen i.e. M, N difference is more than one times, using method 3, divide the matrix into
Multiple square formations with smaller value in M, N as exponent number, as shown in figure 5, original matrix is divided into tri- square formations of A, B, C, M is than N or N
When ratio than M is not integer, expanding data ensures to be divided into integer square formation.Each square formation applies mechanically the side in Fig. 2 again
Battle array transposition method divides little square formation and completes transposition, and in Project Realization, each square formation can process code mould with directly transplanting square formation transposition
Block.
The embodiment of the present invention：TakeL=32.
Situation 1：Distance points M=768, N=512, now meetUsing method two, N is extended to
768 so that data becomes the square formation for 768 ranks, in the little square formation that the square formation after expanding is divided into 24*24 32 ranks, calls
Square formation transposition module completes transposition.
Situation 2：Distance points M=2048, N=256, nowTake method three, for exponent number, matrix is drawn with N
The square formation being divided into 8 exponent numbers to be 256, each square formation is further subdivided into the 8 little square formations taking advantage of 8 32 ranks, calls square formation transposition module
Complete transposition, transposition result is put into the address symmetrical with raw address ranks.
Claims (3)
1. a kind of general FPGA original position data transposition method of partition is it is characterised in that comprise the following steps：
(1) pretreated echo data Pulse by Pulse is sequentially stored into DDR3SRAM and respectively advances row cache by FPGA, needs to deposit enough one
Arteries and veins group number N needed for width image；
(2) ratio of distance points M and orientation points N is set up FPGA original position transposition processing method model, institute as standard
Stating judgment models is：
WhenFor basic square formation transposition method；
WhenOrFor method 1；
WhenOrFor method 2；
WhenOrFor method 3；
P, Q are integer, and meet
(3) when M, N are equal, using basic square formation transposition method, square formation is divided into the little square formation of L rank；Described little square formation
It is divided into two classes：A class is the square formation on diagonal, successively A class square formation is read into FPGA internal RAM, is redirected by address and complete A
Data transposition within class square formation, is written back raw address in DDR3SDRAM；During B matroid transposition, need every time to read with regard to right
Two symmetrical square formations of linea angulata, to FPGA internal RAM, redirect, by address, the transposition being respectively completed the data within two square formations,
Two square formation exchange positions are being write back DDR3SDRAM；
(4) whenOrWhen, using the method 1 described in step (2), by data be divided into one with M,
In N, smaller value is the square formation of exponent number and a minor matrix, and the square formation marking off is according to the basic square formation transposition described in step (2)
Method carries out piecemeal process, is individually divided into little square formation for the data field having more, and reads in FPGA internal RAM one by one and completes transposition
The position symmetrical with raw address in writing back DDR3SRAM；
(5) whenOrWhen, using the method 2 described in step (2), by data matrix be extended for M,
In N, higher value is the square formation of exponent number, then directly carries out piecemeal process according to the basic square formation transposition method described in step (2)
Complete original position transposition, subsequent treatment is ignored the data field of expansion；
(6) when M, N difference is more than one times, using method 3, divide the matrix into multiple with smaller value in M, N as exponent number
Square formation, the expanding data of not enough integer square formation is divided into integer, to each square formation directly according to basic described in step (2)
Square formation transposition method carry out piecemeal process complete original position transposition.
2. general FPGA original position data transposition method of partition according to claim 1 it is characterised in that：Described P, Q are equal
For integer, and meet The value selection that can affect to method 1 and method 2, need incorporation engineering to realize difficult
Degree and algorithm process efficiency determine, for method 1 and method 2, in the case that process sequential is enough,Value close to 2, then
It is more conducive to system of selection 2.
3. general FPGA original position data transposition method of partition according to claim 1 it is characterised in that：Described L meets
Condition：L≤M and L≤N, the value of L and processing data amount and FPGA internal resource are related, take 32 or 64.
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| CN111124300A (en) * | 2019-12-17 | 2020-05-08 | 深圳忆联信息系统有限公司 | Method and device for improving access efficiency of SSD DDR4, computer equipment and storage medium |
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