CN103412284A - Matrix transposition method in SAR imaging system based on DSP chip - Google Patents
Matrix transposition method in SAR imaging system based on DSP chip Download PDFInfo
- Publication number
- CN103412284A CN103412284A CN2013103858645A CN201310385864A CN103412284A CN 103412284 A CN103412284 A CN 103412284A CN 2013103858645 A CN2013103858645 A CN 2013103858645A CN 201310385864 A CN201310385864 A CN 201310385864A CN 103412284 A CN103412284 A CN 103412284A
- Authority
- CN
- China
- Prior art keywords
- square formation
- unit
- matrix
- little square
- transposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Complex Calculations (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention discloses a matrix transposition method in an SAR imaging system based on a DSP chip. The problems that radar real-time imaging storage space is small, and the requirement for real-time performance is high are mainly solved. The implementation process of the matrix transposition method comprises the steps that (1) an original matrix is transversely divided; (2) a rough classification matrix is longitudinally divided; (3) small unit matrixes are obtained; (4) storage space is created; (5) the small unit matrixes are classified; (6) transposition is carried out on the small diagonal unit matrixes; (7) transposition is carried out on the small non-diagonal unit matrixes; (8) the transpositioned matrixes are combined. The matrix transposition method aims at the transposition operation of a large-scale radar return original data matrix, the large matrix is roughly and finely divided into two classes of small unit matrixes, different transposition methods are applied to processing the matrixes, a large amount of storage space is saved, and operation efficiency is improved. The matrix transposition method is simple, easy to implement and suitable for the transposition operation of various radar real-time imaging systems and other systems.
Description
Technical field
The invention belongs to communication technical field, further relate to matrix transpose method in a kind of imaging system of synthetic-aperture radar (Synthetize Aperture Radar SAR) based on digital signal processor (Digital Signal Processor DSP) chip in the Radar Digital Signal Processing field.The present invention can be used for extensive radar return data are carried out to quick transposition, to solve the deficiency of synthetic aperture radar image-forming requirement of real-time and storage resources.
Background technology
Radar return data matrix transposition data volume is large, requirement of real-time is high, but it is in short supply under actual conditions, to process storage space, so how in limited storage space, to realize, the quick transposition method of extensive matrix becomes problem demanding prompt solution, this is also for realizing that real-time SAR imaging lays a good foundation
A kind of method of matrix transpose is disclosed in the patent " a kind of method of matrix transpose " of Xin Dong Divine Land, Jiangsu Science and Technology Ltd. application (publication number: CN102253925A, application number: 201010174342.7, applying date: on 05 18th, 2010).At first the method will treat that the matrix of transposition is divided into submatrix, then from each a submatrix, take out data line and the data of taking-up are put into to register one by one until all go data and discharge in order, then the data that read one by one in order register are put in the correspondence position of matrix after transposition.The deficiency that this patented claim exists is because register space is too little, and to utilize the extensive matrix transpose of the method to need a very large storage space, so the method is not suitable for extensive matrix transpose computing.
Patent " matrix transpose method of synthetic aperture radar image-forming system and the transposition device " (publication number: CN103048644A of University of Electronic Science and Technology's application, application number: 201210553860.9, the applying date: the matrix transpose method and the transposition device that disclose a kind of synthetic aperture radar image-forming system on Dec 19th, 2012).At first Technologies Against Synthetic Aperture Radar echo matrix data input of the method, then cut apart this matrix and the generation of read/write address, then the echo matrix data is write to the transposition output that SDRAM echo matrix data read in output buffer unit and echo matrix data.The deficiency that this patented claim exists is, the data of SDRAM read in the wide constraint that all is subjected to bus with output speed, and the matrix transpose device need to be opened up large storage space for intermediate variable in SDRAM, so each data-moving can expend the plenty of time, this can't meet the real-time of matrix transpose.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, a kind of quick transposition method for extensive radar return data matrix in the radar real time imagery is provided, to realize completing the real time radar imaging processing under storage space condition in short supply.
Realize that technical thought of the present invention is: do not open up large storage space and deposit the matrix transpose intermediate variable, by extensive radar return data original matrix rough segmentation piece, again the minor matrix of piecemeal is carefully divided, obtain the two little square formations in class unit, and with diverse ways, the little square formation of this two class is carried out to transpose process, finally by the matrix stores after transposition on corresponding DDR3 address.
The concrete steps that realize the object of the invention are as follows:
(1) laterally divide original matrix:
To be stored in vertical continuous radar return data original matrix in the dsp chip external memory space, the number of processing core according to dsp chip laterally is divided into M rough segmentation matrix.
(2) vertically divide the rough segmentation matrix:
Each rough segmentation matrix vertically is divided into to N preliminary square formation, the M * N after slightly being divided preliminary square formation.
(3) obtain the little square formation in unit:
Each preliminary square formation carefully is divided into to the little square formation in the equal-sized unit of parking space that a plurality of sizes and DSP internal storage space are opened up.
(4) open up storage space:
Open up four internal storage space addresses identical with the little square formation size in unit.
(5) to the little square formation classification in unit:
By the little square formation in unit be positioned in each preliminary square formation on diagonal line, be divided into the little square formation classification in unit, diagonal angle, will be positioned at the little square formation in unit on off-diagonal, be divided into the little square formation classification in unit, non-diagonal angle.
(6) the little square formation transpose process in unit, diagonal angle:
6a) from the little square formation classification in unit, diagonal angle, getting the little square formation in unit, a diagonal angle;
6b) by the direct memory instruction of dsp chip inside, by the little square formation in unit, diagonal angle of getting, from the external memory space address, being transported to step (4) in the internal storage space address that opens up;
6c) to taking the little square formation in unit, Zhong De diagonal angle, internal storage space address, carry out transpose process, after transposition, be stored in another piece internal storage space address of having opened up;
6d), by the direct memory instruction of dsp chip inside, by the little square formation in unit, diagonal angle after transposition, in memory space address, be transported to internally in the former external memory space address of depositing of this little square formation in unit, diagonal angle the internal storage space address of release busy;
6e) judge whether the little square formation in unit, diagonal angle takes; If do not take, perform step 6a); If take, execution step (7).
(7) the little square formation transpose process in unit, non-diagonal angle:
7a) from the little square formation classification in unit, non-diagonal angle, get the little square formation in unit, two non-diagonal angles about the diagonal line symmetry;
7b) by the direct memory instruction of dsp chip inside, by the little square formation in unit, two non-diagonal angles of getting, from the external memory space address, be transported to two internal storage space addresses that step (4) opens up;
7c) to taking the little square formation in unit, Zhong Defei diagonal angle, two internal storage space addresses, carry out transpose process respectively, after transposition, be stored in another two internal storage space addresses of having opened up;
7d) by the direct memory instruction of dsp chip inside, by the little square formation in unit, two non-diagonal angles after transposition, intersect and be transported in former external memory space address of depositing, the internal storage space address of release busy;
7e) judge whether the little square formation in unit, non-diagonal angle takes; If do not take, execution step 7a); If take, perform step (8).
(8) combination transposed matrix:
8a) extract successively longitudinal data row that are stored in each preliminary square formation in the rough segmentation matrix in dsp chip external memory space address;
8b), by the longitudinal data row that extract, arrange according to the order of preliminary square formation, form longitudinal data row of radar return data transposition matrix;
Whether the longitudinal data row that 8c) judge preliminary square formation take, if do not take, perform step 8a) extract the next column of preliminary square formation; If take, obtain the longitudinal data piece of radar return data transposition matrix, execution step 8d);
8d) by the longitudinal data piece of radar return data transposition matrix, according to dsp chip M the order of processing core, arrange, obtain the transposed matrix of radar return data.
Compared with prior art, the present invention has the following advantages:
First, the present invention divides original extensive matrix thickness respectively, avoided the requirement of opening up very large storage space in the transposition process, overcome thus in prior art because register space is too little, be not suitable for the deficiency of extensive matrix transpose computing, make the present invention have advantages of the larger scope of application.
Second, the present invention is by being divided into the two little square formations in class unit to the original matrix thickness, to dividing rear little square formation, carry out different transposition computings again, overcome the shortcoming that needs to open up for intermediate variable large storage space in the prior art, make the present invention have advantages of a large amount of storage spaces of saving.
The 3rd, the present invention divide to process radar return data original matrix, has overcome the shortcoming that data-moving during prior art is processed in real time expends the plenty of time, makes the present invention have advantages of that processing speed is fast, further improves the real-time of radar imagery.
The accompanying drawing explanation
Fig. 1 is process flow diagram of the present invention;
Fig. 2 is the schematic diagram that radar return raw data matrix thickness of the present invention is divided;
Fig. 3 is of the present invention to the little square formation classification in unit schematic diagram;
Fig. 4 is unit, diagonal angle of the present invention little square formation transpose process schematic diagram;
Fig. 5 is unit, non-diagonal angle of the present invention little square formation transpose process schematic diagram;
Fig. 6 is combination transposed matrix schematic diagram of the present invention.
Specific implementation method
Below in conjunction with accompanying drawing, the present invention is described further.
With reference to accompanying drawing 1, concrete steps of the present invention are as follows:
Step 1, laterally divide original matrix.
To be stored in vertical continuous radar return data original matrix in the dsp chip external memory space, the number of processing core according to dsp chip laterally is divided into M rough segmentation matrix.
Radar return raw data matrix in example of the present invention is stored in the external memory space of dsp chip TMS320C6678, vertically continuously, vertically counts as nrn, laterally counts as nan.The characteristic that has eight parallel cores according to dsp chip TMS320C6678, laterally be divided into eight rough segmentation matrixes by the echo raw data and give eight cores.
Step 2, vertically divide the rough segmentation matrix.
Because the rough segmentation matrix is not square formation, each rough segmentation matrix vertically is divided into to N preliminary square formation again,
Wherein, N is the number of preliminary square formation, and nan is laterally counting of original echo data matrix, and nrn is vertically counting of original echo data matrix, and M is the number of rough segmentation matrix, also equals the number that dsp chip is processed core.
The number of processing core due to dsp chip of the present invention is 8, so M=8 in embodiments of the invention.
With reference to Fig. 2, can find out clearly, the present invention by vertically being divided into eight rough segmentation matrixes, more laterally is divided into the preliminary square formation of N by radar return data original matrix.Fig. 2 is the schematic diagram that radar return raw data matrix thickness is divided, in Fig. 2, the first half refers to that original matrix is divided into rough segmentation matrix 1, rough segmentation matrix 2, rough segmentation matrix 3, rough segmentation matrix 4, rough segmentation matrix 5, rough segmentation matrix 6, rough segmentation matrix 7, rough segmentation matrix 8, totally 8 rough segmentation matrixes.The latter half of Fig. 2 is that each rough segmentation matrix vertically is divided into to a1, a2......, aN, N preliminary square formation altogether.By the horizontal and vertical division to original matrix, original matrix is divided into to 8 * N preliminary square formation.
Step 3, obtain the little square formation in unit.
By horizontal division and vertical drawing in two steps, the radar return raw data matrix has been divided into M * N preliminary square formation.Each preliminary square formation carefully is divided into to the little square formation in the equal-sized unit of parking space that a plurality of sizes and DSP internal storage space are opened up.In example of the present invention, for 16384 * 8192 floating type plural number original echo matrixes, the size of each preliminary square formation is 2048 * 2048, more preliminary square formation is subdivided into to the little square formation in unit of 128 * 128 sizes, and each preliminary square formation has 16 * 16 little square formations in unit.
According to the size of residual memory space in the internal storage space L2 of 512KB size, in the embodiment of the present invention, the little square formation size in unit is decided to be 128 * 128.In transposition computing of the present invention, only need to additionally open up the array of four 128 * 128 floating type complex magnitude, two little square formations in unit of putting original 128 * 128 sizes of taking out wherein, another two little square formations in unit of depositing after transposition.
Step 4, open up storage space.
In internal storage space L2, open up four spaces identical with the little square formation in unit size, wherein deposit from the little square formation in unit of taking out DDR3 for two, another two little square formations in unit of depositing after transposition.
In the embodiment of the present invention, total size is in the L2 of 512KB, to open up the space of 4 128 * 128 floating type complex magnitude in space.
Step 5, to the little square formation classification in unit.
By the little square formation in unit be positioned in preliminary square formation on diagonal line, be divided into the little square formation classification in unit, diagonal angle, will be positioned at the little square formation in unit on off-diagonal, be divided into the little square formation classification in unit, non-diagonal angle.Process like this is that under the condition of array in the not opening up external memory space matrix of storing pilot process, to the little square formation transposition in each unit, and the mode of corresponding stored realizes whole original echo transpose of a matrix.
With reference to Fig. 3, can find out clearly, the present invention is divided into the little square formation of the little square formation in unit, diagonal angle and unit, non-diagonal angle by the little square formation in unit.Fig. 3 is to the little square formation in unit classification schematic diagram, and the little square formation of unit that will be positioned in Fig. 3 on the diagonal line of preliminary matrix is divided into the little square formation in unit, diagonal angle, and the little square formation in the unit on remaining off-diagonal is divided into the little square formation in unit, non-diagonal angle.By this classification, the little square formation in different classes of unit can be done different transposition calculation process.
Step 6, the little square formation transpose process in unit, diagonal angle.
6a) from the little square formation classification in unit, diagonal angle of the DDR3 that is stored in external memory space, getting the little square formation in unit, a diagonal angle;
6b) by the direct memory instruction of dsp chip inside, by the little square formation in unit, diagonal angle of getting, from the external memory space address, being transported in internal storage space L2 and opening up in the internal storage space address;
6c) in the DSP program segment, call TI built-in function plural number floating type matrix transpose function DSPF_sp_mat_trans_cplx the little square formation in unit, diagonal angle is carried out to transpose process, after transposition, be stored in another piece internal storage space address of having opened up.
The concrete steps of the little square formation transposition in unit, diagonal angle are:
The first step, appoint fetch bit element a on the capable n column position of m in the little square formation in unit.
Second step, take out and be arranged in the element b on the capable m column position of unit little square formation n.
The 3rd step, exchange element a and the memory location of element b in the little square formation in unit, and element a is put in the little square formation in unit on the capable m column position of n, and element b is put in the little square formation in unit on the capable n column position of m.
The 4th step, in the little square formation of judging unit, whether the position of all elements exchanges completely, if do not exchanged, carries out the first step; Otherwise, finish transpose process.
6d) by the direct memory instruction of dsp chip inside, by the little square formation in unit, diagonal angle after transposition, in memory space address, be transported to internally in the former external memory space address D DR3 deposited of this little square formation in unit, diagonal angle the internal storage space address of release busy;
6e) judge whether the little square formation in unit, diagonal angle takes; If do not take, perform step 6a); If take, execution step (7).
With reference to Fig. 4, the little square formation in unit, a diagonal angle is carried out to the transposition computing.Fig. 4 is unit, diagonal angle little square formation transpose process schematic diagram, by figure, be positioned on preliminary diagonal of a matrix to the little square formation of angular unit, from the address of DDR, moving in the L2 address, and carry out the transposition computing in L2, then deposit on original DDR address.By such processing, all little square formations in unit, diagonal angle have completed the transposition computing.
Step 7, the little square formation transpose process in unit, non-diagonal angle.
7a) from the little square formation classification in unit, non-diagonal angle, utilize DMA from the original echo matrix of DDR3 the external memory space address, getting the little square formation in unit, two non-diagonal angles about the diagonal line symmetry, the little square formation of the capable m row of the little square formation of n row as capable as m and n;
7b), by the direct memory instruction of dsp chip inside, by the little square formation in unit, two non-diagonal angles of getting, be transported in two internal storage space addresses of opening up in L2;
7c) in the DSP program segment, call plural floating type matrix transpose function DSPF_sp_mat_trans_cplx in the TI storehouse and respectively the little square formation in unit, non-diagonal angle in these two storage arrays is carried out to transposition, after transposition, be stored in another two internal storage space addresses of having opened up.
The concrete steps of each little square formation transposition in unit, non-diagonal angle are:
The first step, appoint to take out to be arranged in the element a on the capable n column position of unit little square formation m.
Second step, take out and be arranged in the element b on the capable m column position of unit little square formation n.
The 3rd step, exchange element a and the memory location of element b in the little square formation in unit, and element a is put in the little square formation in unit on the capable m column position of n, and element b is put in the little square formation in unit on the capable n column position of m.
The 4th step, in the little square formation of judging unit, whether the position of all elements exchanges completely, if do not exchanged, carries out the first step; Otherwise, finish transpose process.
7d) by the direct memory instruction of dsp chip inside, by the little square formation in unit, two non-diagonal angles after transposition, intersect and be transported in former external memory space address of depositing, the internal storage space address of release busy;
7e) judge whether the little square formation in unit, non-diagonal angle takes; If do not take, execution step 7a); If take, the little square formation transposition in unit, non-diagonal angle completes.
With reference to Fig. 5, the little square formation in unit, a non-diagonal angle is carried out to the transposition computing.Fig. 5 is unit, non-diagonal angle little square formation transpose process schematic diagram, the little square formation of angular unit is moved to the L2 address from the address of DDR by two of being arranged in preliminary diagonal of a matrix symmetry in figure are non-, and in L2, carry out respectively the transposition computing, then intersection is deposited on the other side's DDR address.All little square formations in unit, non-diagonal angle have just completed the transposition computing by such processing.
Step 8, the combination transposed matrix.
After in the embodiment of the present invention, the little square formation in unit was all carried out the transpose process end, the preliminary square formation of 2048 * 2048 sizes had just obtained transposition, the radar return raw data matrix vertically become continuously horizontal continuous radar return transposed matrix.If obtain longitudinal data row of radar return transposed matrix, need data splitting.
The specific implementation of combination transposed matrix is according to following steps:
8a) extract successively longitudinal data row that are stored in each preliminary square formation in the rough segmentation matrix in dsp chip external memory space address;
8b), by the longitudinal data row that extract, arrange according to the order of preliminary square formation, form longitudinal data row of radar return data transposition matrix;
Whether the longitudinal data row that 8c) judge preliminary square formation take, if do not take, perform step 8a) extract the next column of preliminary square formation; If take, obtain the longitudinal data piece of radar return data transposition matrix, execution step 8d);
8d) by the longitudinal data piece of radar return data transposition matrix, according to dsp chip M the order of processing core, arrange, obtain the transposed matrix of radar return data.
With reference to Fig. 6, the preliminary square formation after transposition is combined into to radar return data transposition matrix.Fig. 6 is combination transposed matrix schematic diagram, in figure, be positioned at after a Data in Azimuth Direction transposition of rough segmentation matrix the continuation column data that become four preliminary square formations, so extract a Data in Azimuth Direction of radar return data transposition matrix, need to get respectively the column vector of preliminary square formation, and according to DSP, process these column vectors of sequential combination of core, namely obtain the Data in Azimuth Direction of distance to continuous echo matrix.
So far, based on matrix transpose method in the SAR imaging system of dsp chip, complete.
The present invention is based on the SAR real time imagery and processes, and the basic step that briefly introduces SAR imaging is: the first step solves the inertial navigation parameter of echo data matrix, adjust the distance to continuous echo data apart from pulse pressure, and non-space-variant and space-variant compensation; Second step to orientation to continuously, transforms to the echo data matrix transpose apart from time domain-orientation Doppler domain; The 3rd step is apart to continuously by the echo data matrix transpose, carries out range migration correction; The 4th step to orientation to continuously, arrives the echo data matrix transpose apart from time domain-orientation time domain by data transformation, and estimating Doppler frequency modulation rate is also carried out orientation to pulse pressure.Whole SAR Real Time Image System needs the computing of cubic matrix transposition, if can improve the matrix transpose arithmetic speed, will improve greatly the efficiency of real time imagery.
Below by test, contrast the present invention and take memory space requirements and comparison operation time with traditional transposition method, further illustrate effect of the present invention.
Test 1: the present invention takies storage space with traditional transposition method and contrasts.
This test is based on the development board of TMS320C6678, and radar return data original matrix distance is to 16384 * 8192 floating type complex matrixs of continuous (vertically continuously), and distance is 16384 to counting, and orientation is 8192 to counting.
Storage size to the TMS320C6678 development board is analyzed.TMS320C6678 is the digital signal processor of a Resources on Chip that has high-performance and enrich, and has eight and processes cores, and dominant frequency is up to 1.0GHz.
With reference to table 1, the storer of TMS320C6678 comprises the second-level storage (L2) of the level data memory (L1D) of the one-level program storage (L1P) of a 32KB, a 32KB, a 512KB, the multinuclear of 4096KB is shared storage space (MSMC), the external memory space of external 2GB (DDR3).
The storage size of table 1:TMS320C6678 development board
| The size of storage space (byte) | |
| External memory area DDR3 | 2G |
| One-level program storage area L1P | 32K |
| One-level data storage area L1D | 32K |
| Secondary storage area L2 | 512K |
| Multinuclear is shared storage space MSMC | 4M |
Radar return data original matrix needs the 1GB storage space, so the DDR3 of 2GB just deposits two groups of echo data matrixes of ping-pong.If adopt the transposition function in the TI storehouse to carry out transposition to whole original matrix, need in DDR3, open up the array that a size is 16384 * 8192 floating type plural numbers, this has wasted external memory space greatly, and in the DDR3 of this development board also without unnecessary storage space.
Adopted transposition method in the present invention only need to wherein deposit from the little square formation in unit of taking out DDR3 for two in total size in the L2 of 512KB, opening up the array of 4 128 * 128 floating type complex magnitude, another two little square formations in unit of depositing after transposition.
Test 2: the present invention and the traditional time-consuming contrast of transposition method
This test is based on the development board of TMS320C6678, and radar return data original matrix distance is to 16384 * 8192 continuous floating type complex matrixs, and distance is 16384 to counting, and orientation is 8192 to counting.
Relatively utilize the EDMA interval to get orientation to a column data, call in the TI storehouse and after matrix transpose function transposition, get continuously again orientation to a column data, utilize after transposition method transposition of the present invention and get orientation again and get discontinuous Data in Azimuth Direction row in 16384 * 8192 radar return data original matrix to these three kinds of distinct methods of a column data, statistics comparison operation are consuming time.
With reference to table 2, utilizing the EDMA interval to get orientation adds orientation to this method matrix transpose of a column data and is the 2.0656e+009 clock period to the Fourier transform time used, call in the TI storehouse after matrix transpose function transposition, get continuously again orientation to this method matrix transpose of a column data add orientation to the Fourier transform time used be the 9.5852e+009 clock period, utilize after transposition method transposition of the present invention and get again orientation and to this method matrix transpose of a column data, add orientation and be the 1.0311e+009 clock period to the Fourier transform time used.
As can be known from Table 2, call in the TI storehouse this method of orientation to a column data of getting continuously again after complex matrix transposition function transposition, consuming time the longest, be secondly to utilize the EDMA interval to get the method for orientation to a column data, what the used time economized most is to get orientation to a column data after utilizing transposition method of the present invention.
Table 2: the used time of getting the non-continuous data row with three kinds of diverse ways compares
One 8192 complex vector located FFT need 228 after tested, 220 clock period, it is consuming time as can be known that time described in table 2 deducts FFT, utilize transposition method of the present invention after complex matrix transposition function transposition, to get orientation method nearly ten times of times of saving to a column data than calling in the TI storehouse, Billy gets orientation with the EDMA interval and saves nearly half the time to the method for a column data again.
Claims (3)
1. matrix transpose method in the imaging system of the SAR based on dsp chip, comprise the steps:
(1) laterally divide original matrix:
To be stored in vertical continuous radar return data original matrix in the dsp chip external memory space, the number of processing core according to dsp chip laterally is divided into M rough segmentation matrix;
(2) vertically divide the rough segmentation matrix:
Each rough segmentation matrix vertically is divided into to N preliminary square formation, the M * N after slightly being divided preliminary square formation;
(3) obtain the little square formation in unit:
Each preliminary square formation carefully is divided into to the little square formation in the equal-sized unit of parking space that a plurality of sizes and DSP internal storage space are opened up;
(4) open up storage space:
Open up four internal storage space addresses identical with the little square formation size in unit;
(5) to the little square formation classification in unit:
By the little square formation in unit be positioned in each preliminary square formation on diagonal line, be divided into the little square formation classification in unit, diagonal angle, will be positioned at the little square formation in unit on off-diagonal, be divided into the little square formation classification in unit, non-diagonal angle;
(6) the little square formation transpose process in unit, diagonal angle:
6a) from the little square formation classification in unit, diagonal angle, getting the little square formation in unit, a diagonal angle;
6b) by the direct memory instruction of dsp chip inside, by the little square formation in unit, diagonal angle of getting, from the external memory space address, being transported to step (4) in the internal storage space address that opens up;
6c) to taking the little square formation in unit, Zhong De diagonal angle, internal storage space address, carry out transpose process, after transposition, be stored in another piece internal storage space address of having opened up;
6d), by the direct memory instruction of dsp chip inside, by the little square formation in unit, diagonal angle after transposition, in memory space address, be transported to internally in the former external memory space address of depositing of this little square formation in unit, diagonal angle the internal storage space address of release busy;
6e) judge whether the little square formation in unit, diagonal angle takes; If do not take, perform step 6a); If take, execution step (7);
(7) the little square formation transpose process in unit, non-diagonal angle:
7a) from the little square formation classification in unit, non-diagonal angle, get the little square formation in unit, two non-diagonal angles about the diagonal line symmetry;
7b) by the direct memory instruction of dsp chip inside, by the little square formation in unit, two non-diagonal angles of getting, from the external memory space address, be transported to two internal storage space addresses that step (4) opens up;
7c) to taking the little square formation in unit, Zhong Defei diagonal angle, two internal storage space addresses, carry out transpose process respectively, after transposition, be stored in another two internal storage space addresses of having opened up;
7d) by the direct memory instruction of dsp chip inside, by the little square formation in unit, two non-diagonal angles after transposition, intersect and be transported in former external memory space address of depositing, the internal storage space address of release busy;
7e) judge whether the little square formation in unit, non-diagonal angle takes; If do not take, execution step 7a); If take, perform step (8);
(8) combination transposed matrix:
8a) extract successively longitudinal data row of each preliminary square formation in the rough segmentation matrix that is stored in dsp chip external memory space address;
8b), by the longitudinal data row that extract, arrange according to the order of preliminary square formation, form longitudinal data row of radar return data transposition matrix;
Whether the longitudinal data row that 8c) judge preliminary square formation take, if do not take, perform step 8a) extract the next column of preliminary square formation; If take, obtain the longitudinal data piece of radar return data transposition matrix, execution step 8d);
8d) by the longitudinal data piece of radar return data transposition matrix, according to dsp chip M the order of processing core, arrange, obtain the transposed matrix of radar return data.
2. according to matrix transpose method in the imaging system of the SAR based on dsp chip described in claim 1, it is characterized in that, in the described N of step (2) preliminary square formation, N must meet following formula:
Wherein, N is the number of preliminary square formation, and nan is laterally counting of radar return data original matrix, and M is the number of rough segmentation matrix, and nrn is vertically counting of radar return data original matrix.
3. according to matrix transpose method in the imaging system of the SAR based on dsp chip described in claim 1, it is characterized in that step 6c), step 7c) concrete steps of described transpose process are as follows:
The first step, appoint to take out to be arranged in the element a on the capable n column position of unit little square formation m;
Second step, take out and be arranged in the element b on the capable m column position of unit little square formation n;
The 3rd step, exchange element a and the memory location of element b in the little square formation in unit, and element a is put in the little square formation in unit on the capable m column position of n, and element b is put in the little square formation in unit on the capable n column position of m;
The 4th step, in the little square formation of judging unit, whether the position of all elements exchanges completely, if do not exchanged, carries out the first step; Otherwise, finish transpose process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310385864.5A CN103412284B (en) | 2013-08-29 | 2013-08-29 | Matrix transposition method in SAR imaging system based on DSP chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310385864.5A CN103412284B (en) | 2013-08-29 | 2013-08-29 | Matrix transposition method in SAR imaging system based on DSP chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103412284A true CN103412284A (en) | 2013-11-27 |
| CN103412284B CN103412284B (en) | 2015-05-20 |
Family
ID=49605311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310385864.5A Expired - Fee Related CN103412284B (en) | 2013-08-29 | 2013-08-29 | Matrix transposition method in SAR imaging system based on DSP chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103412284B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103761709A (en) * | 2014-01-07 | 2014-04-30 | 西安电子科技大学 | Parallel real-time SAR image spot and noise reducing method based on multiple DSPs |
| CN105527609A (en) * | 2015-12-02 | 2016-04-27 | 西安电子工程研究所 | PD radar system matrix transposition method based on DSP |
| CN106483505A (en) * | 2016-09-22 | 2017-03-08 | 西安空间无线电技术研究所 | A kind of general FPGA original position data transposition method of partition |
| CN106933756A (en) * | 2015-12-31 | 2017-07-07 | 北京国睿中数科技股份有限公司 | For the quick transposition methods of DMA and device of variable matrix |
| CN108053855A (en) * | 2017-11-29 | 2018-05-18 | 北京时代民芯科技有限公司 | A kind of matrix transposition method based on SDRAM chips |
| CN108872990A (en) * | 2018-09-11 | 2018-11-23 | 中国科学院电子学研究所 | Real time sar imaging transposition processing method |
| CN109298850A (en) * | 2018-06-04 | 2019-02-01 | 中国电子科技集团公司第十四研究所 | Big data transposition method based on C6678 platform |
| CN109471612A (en) * | 2018-09-18 | 2019-03-15 | 北京中科寒武纪科技有限公司 | Arithmetic unit and method |
| CN111208504A (en) * | 2020-02-28 | 2020-05-29 | 成都汇蓉国科微系统技术有限公司 | PD radar waveform configuration method and device based on DSP |
| CN111221574A (en) * | 2018-11-26 | 2020-06-02 | 北京华航无线电测量研究所 | Large matrix fast transposition multi-core parallel processing method |
| CN112986997A (en) * | 2021-04-09 | 2021-06-18 | 中国科学院空天信息创新研究院 | Unmanned aerial vehicle-mounted SAR real-time imaging processing method and device and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5644517A (en) * | 1992-10-22 | 1997-07-01 | International Business Machines Corporation | Method for performing matrix transposition on a mesh multiprocessor architecture having multiple processor with concurrent execution of the multiple processors |
| US20090063529A1 (en) * | 2007-09-01 | 2009-03-05 | Fred Gehrung Gustavson | Method and structure for fast in-place transformation of standard full and packed matrix data formats |
| CN102279386A (en) * | 2011-05-12 | 2011-12-14 | 西安电子科技大学 | SAR (Synthetic Aperture Radar) imaging signal processing data transposing method based on FPGA (Field Programmable Gata Array) |
| CN103048644A (en) * | 2012-12-19 | 2013-04-17 | 电子科技大学 | Matrix transposing method of SAR (synthetic aperture radar) imaging system and transposing device |
-
2013
- 2013-08-29 CN CN201310385864.5A patent/CN103412284B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5644517A (en) * | 1992-10-22 | 1997-07-01 | International Business Machines Corporation | Method for performing matrix transposition on a mesh multiprocessor architecture having multiple processor with concurrent execution of the multiple processors |
| US20090063529A1 (en) * | 2007-09-01 | 2009-03-05 | Fred Gehrung Gustavson | Method and structure for fast in-place transformation of standard full and packed matrix data formats |
| CN102279386A (en) * | 2011-05-12 | 2011-12-14 | 西安电子科技大学 | SAR (Synthetic Aperture Radar) imaging signal processing data transposing method based on FPGA (Field Programmable Gata Array) |
| CN103048644A (en) * | 2012-12-19 | 2013-04-17 | 电子科技大学 | Matrix transposing method of SAR (synthetic aperture radar) imaging system and transposing device |
Non-Patent Citations (2)
| Title |
|---|
| 林桐等: "实时SAR成像系统矩阵原位转置的实现", 《计算机工程》 * |
| 白海龙等: "基于DDR2 SDRAM的SAR成像转置存储器的FPGA实现", 《通信设备》 * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103761709B (en) * | 2014-01-07 | 2016-08-03 | 西安电子科技大学 | Parallel REAL TIME SAR IMAGES based on multi-DSP fall speckle denoising method |
| CN103761709A (en) * | 2014-01-07 | 2014-04-30 | 西安电子科技大学 | Parallel real-time SAR image spot and noise reducing method based on multiple DSPs |
| CN105527609A (en) * | 2015-12-02 | 2016-04-27 | 西安电子工程研究所 | PD radar system matrix transposition method based on DSP |
| CN106933756A (en) * | 2015-12-31 | 2017-07-07 | 北京国睿中数科技股份有限公司 | For the quick transposition methods of DMA and device of variable matrix |
| CN106483505A (en) * | 2016-09-22 | 2017-03-08 | 西安空间无线电技术研究所 | A kind of general FPGA original position data transposition method of partition |
| CN106483505B (en) * | 2016-09-22 | 2019-03-12 | 西安空间无线电技术研究所 | A kind of general original position FPGA data transposition method of partition |
| CN108053855B (en) * | 2017-11-29 | 2021-01-08 | 北京时代民芯科技有限公司 | Matrix transposition method based on SDRAM chip |
| CN108053855A (en) * | 2017-11-29 | 2018-05-18 | 北京时代民芯科技有限公司 | A kind of matrix transposition method based on SDRAM chips |
| CN109298850A (en) * | 2018-06-04 | 2019-02-01 | 中国电子科技集团公司第十四研究所 | Big data transposition method based on C6678 platform |
| CN108872990A (en) * | 2018-09-11 | 2018-11-23 | 中国科学院电子学研究所 | Real time sar imaging transposition processing method |
| CN108872990B (en) * | 2018-09-11 | 2021-03-26 | 中国科学院电子学研究所 | Real-time imaging transposition processing method for synthetic aperture radar |
| CN109471612A (en) * | 2018-09-18 | 2019-03-15 | 北京中科寒武纪科技有限公司 | Arithmetic unit and method |
| CN111221574A (en) * | 2018-11-26 | 2020-06-02 | 北京华航无线电测量研究所 | Large matrix fast transposition multi-core parallel processing method |
| CN111208504A (en) * | 2020-02-28 | 2020-05-29 | 成都汇蓉国科微系统技术有限公司 | PD radar waveform configuration method and device based on DSP |
| CN112986997A (en) * | 2021-04-09 | 2021-06-18 | 中国科学院空天信息创新研究院 | Unmanned aerial vehicle-mounted SAR real-time imaging processing method and device and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103412284B (en) | 2015-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103412284B (en) | Matrix transposition method in SAR imaging system based on DSP chip | |
| CN109284817B (en) | Deep separable convolutional neural network processing architecture/method/system and medium | |
| CN103955447B (en) | FFT accelerator based on DSP chip | |
| CN102208005B (en) | 2-dimensional (2-D) convolver | |
| CN107392309A (en) | A kind of general fixed-point number neutral net convolution accelerator hardware structure based on FPGA | |
| CN108537331A (en) | A kind of restructural convolutional neural networks accelerating circuit based on asynchronous logic | |
| CN102279386B (en) | SAR (Synthetic Aperture Radar) imaging signal processing data transposing method based on FPGA (Field Programmable Gata Array) | |
| CN105224505B (en) | FFT accelerator installations based on the operation of matrix transposition | |
| CN105527609A (en) | PD radar system matrix transposition method based on DSP | |
| CN106021182A (en) | Line transpose architecture design method based on two-dimensional FFT (Fast Fourier Transform) processor | |
| CN109613536B (en) | Satellite-borne SAR real-time processing device and method | |
| CN201226025Y (en) | Processor for pulse Doppler radar signal | |
| CN103955446A (en) | DSP-chip-based FFT computing method with variable length | |
| CN105137428A (en) | Dechirp signal polar format imaging algorithm FPGA (Field Programmable Gate Array) realization method | |
| CN102902657A (en) | Method for accelerating FFT (Fast Fourier Transform) by using GPU (Graphic Processing Unit) | |
| CN100538886C (en) | Rapid read-write method and the device of Multidimensional numerical on dynamic RAM | |
| US9098449B2 (en) | FFT accelerator | |
| CN104679670A (en) | Shared data caching structure and management method for FFT (fast Fourier transform) and FIR (finite impulse response) algorithms | |
| CN109948113A (en) | A kind of Two-dimensional FFT accelerator based on FPGA | |
| CN109446478A (en) | A kind of complex covariance matrix computing system based on iteration and restructural mode | |
| CN103838704A (en) | FFT accelerator with high throughput rate | |
| Jin et al. | GPU-based parallel implementation of SAR imaging | |
| EP3905036B1 (en) | Reconfigurable circuit, corresponding device, system and method | |
| Wang et al. | Video SAR high-speed processing technology based on FPGA | |
| Jin et al. | Design of spaceborne SAR imaging processing and fast Verification Based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150520 Termination date: 20210829 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |