CN115657946A - Off-chip DDR bandwidth unloading method under RAID sequential writing scene, terminal and storage medium - Google Patents
Off-chip DDR bandwidth unloading method under RAID sequential writing scene, terminal and storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of computers, in particular to an off-chip DDR bandwidth unloading method, a terminal and a storage medium under a RAID sequential writing scene. The method comprises the following steps: moving the new data D' from the DDR to an on-chip cache space U of the RAID management chip; calling a RAID calculation engine to read D ' from the on-chip cache U, and writing the D ' and the calculated new check data P ' back to V and X in the off-chip DDR respectively; the D 'and P' data in V and X spaces in the off-chip DDR are destaged. The invention partially unloads the storage bandwidth requirement on the off-chip DDR by introducing the on-chip cache, thereby improving the upper limit of the bandwidth of the upper computer in the sequential writing scene.
Description
Technical Field
The invention relates to the technical field of computers, in particular to an off-chip DDR bandwidth unloading method, a terminal and a storage medium under a RAID sequential writing scene.
Background
The RAID technology organically combines a plurality of independent storage media (SSD or HDD hard disks) into a whole, presents the upper computer as a storage device with data redundancy protection, and responds to management and read/write IO requests of the upper computer. Taking RAID0 as an example, it changes one IO request of an upper computer into concurrent operation on a plurality of independent storage media, thereby improving the overall bandwidth and latency performance. A RAID group typically consists of n data disks and m parity disks. RAID may be classified into different RAID levels according to different organization and algorithms, and RAID0 (n = k, m = 0), RAID1 (n =1, m = 1), RAID10 (n = k, m = k), RAID5 (n = k, m = 1), RAID6 (n = k, m = 2), and the like are common.
In the process that the processing module responds to sequential write IO requests of RAID5 and RAID6 of the upper computer, the RAID processing module generally performs "full stripe" aggregation on multiple sequential write IOs. In the case of a full stripe, new parity data is calculated from the complete new data and both are directly overwritten. As shown in FIG. 8, the steps of the full stripe write process for RAID5 (4 + 1) are shown, which mainly includes three steps,
1. moving the new data D' from the host DDR to the local off-chip DDR space;
2. calling a RAID calculation engine to read D 'from the local DDR and writing the calculated new check data P' back to the local DDR space;
3. and (5) dropping the data in the sum to the disk.
In the RAID processing process in the prior art, the processing performance is affected by the total sequential write bandwidth of the hard disk and the bandwidth of the local storage. In order to solve the technical problem, an off-chip DDR bandwidth unloading method, a terminal and a storage medium under a RAID sequential writing scene are provided.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides an off-chip DDR bandwidth unloading method, a terminal and a storage medium in a RAID sequential writing scene.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
in a first aspect, in an embodiment provided by the present invention, an off-chip DDR bandwidth offload method in a RAID sequential write scenario is provided, where the method includes the following steps:
moving the new data D' from the DDR to an on-chip cache space U of the RAID management chip;
calling a RAID calculation engine to read D ' from the on-chip cache U, and writing the D ' and the calculated new check data P ' back to V and X in the off-chip DDR respectively;
the D 'and P' data in V and X spaces in the off-chip DDR are landed.
As a further aspect of the present invention, the RAID full stripe write process includes a "write-through" mode and a "write-meeting" mode.
As a further aspect of the present invention, when the host is in the write-through mode, the moving the new data D' from the host DDR to the on-chip cache space U of the RAID management chip further includes:
full stripe aggregation across IO ports;
after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM;
memory spaces V and X are applied in the off-chip DDR.
As a further scheme of the present invention, when in the "write-through" mode, the invoking RAID calculation engine reads D ' from the on-chip cache U, and writes D ' and the calculated new check data P ' back to V and X in the off-chip DDR, respectively, and then further includes: and releasing the on-chip cache space U.
As a further aspect of the present invention, when in the "write through" mode, the destaging D 'and P' data in V and X spaces in the off-chip DDR further comprises: releasing storage spaces V and X in the off-chip DDR; and then answers the host.
As a further scheme of the present invention, when the slave DDR is in the "write-back" mode, the moving of the new data D' to the on-chip cache space U of the RAID management chip further includes, before that, full stripe aggregation across the IO ports;
and after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM.
As a further scheme of the present invention, when the slave DDR is in the write-back mode, the slave DDR moves the new data D' to the on-chip cache space U of the RAID management chip, and then the slave DDR also includes a response host;
whether Cache data hit in the DDR is queried or not is judged, and a result a list is obtained;
performing completion operation on the a list to obtain storage spaces V and X in the off-chip DDR;
wherein the a list comprises three results of miss, partial hit and full hit.
As a further scheme of the present invention, when the RAID calculation engine is in the write-back mode, the RAID calculation engine is called to read D ' from the on-chip cache U, and the D ' and the calculated new check data P ' are written back to V and X in the off-chip DDR, respectively, and then the method further includes releasing the on-chip cache space U.
In a second aspect, in a further embodiment provided by the present invention, a terminal is provided, which includes a memory and a processor, where the memory stores a computer program, and the processor, when loading and executing the computer program, implements the steps of the off-chip DDR bandwidth offload method in a RAID sequential write scenario.
In a third aspect, in a further embodiment provided by the present invention, a storage medium is provided, where a computer program is stored, and when the computer program is loaded and executed by a processor, the steps of the off-chip DDR bandwidth offload method in the RAID sequential write scenario are implemented.
The technical scheme provided by the invention has the following beneficial effects:
according to the off-chip DDR bandwidth unloading method, the terminal and the storage medium under the RAID sequence writing scene, new data D' are moved to an on-chip cache space U of a RAID management chip from a host DDR; calling a RAID calculation engine to read D ' from the on-chip cache U, and writing the D ' and the calculated new check data P ' back to V and X in the off-chip DDR respectively; the D 'and P' data in V and X spaces in the off-chip DDR are landed. The invention partially unloads the storage bandwidth requirement of the off-chip DDR by introducing the on-chip cache, thereby improving the upper limit of the bandwidth of the upper computer in the sequential writing scene.
These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a flowchart of an off-chip DDR bandwidth offloading method under a RAID sequential write scenario according to an embodiment of the present invention;
fig. 2 is a structural diagram of an application apparatus of an off-chip DDR bandwidth offloading method in a RAID sequential write scenario according to an embodiment of the present invention;
FIG. 3 is a graph comparing the effects of the present invention and the prior art;
fig. 4 is a diagram illustrating scene definitions of "Write Through (WT)" and "Write Back (WB)" in an off-chip DDR bandwidth offloading method under a RAID sequential write scenario according to an embodiment of the present invention;
fig. 5 is a full stripe write processing flow in a write-through mode in the off-chip DDR bandwidth offload method in a RAID sequential write scenario according to an embodiment of the present invention;
fig. 6 is a flow of full stripe write processing in a write back mode in the off-chip DDR bandwidth offload method in a RAID sequential write scenario according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a terminal according to an embodiment of the present invention;
fig. 8 is a prior art.
In the figure: a processor-401, a communication interface-402, a memory-403, and a communication bus-404.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The flow diagrams depicted in the figures are merely illustrative and do not necessarily include all of the elements and operations/steps, nor do they necessarily have to be performed in the order depicted. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution order may be changed according to the actual situation.
It is to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Specifically, the embodiments of the present invention will be further explained below with reference to the drawings.
Referring to fig. 1, fig. 1 is a flowchart of an off-chip DDR bandwidth offloading method in a RAID sequential write scenario according to an embodiment of the present invention, and as shown in fig. 1, the off-chip DDR bandwidth offloading method in the RAID sequential write scenario includes steps S10 to S30. The method is applied to RAID full stripe write processing.
S10, moving the new data D' from the DDR to an on-chip cache space U of the RAID management chip;
s20, calling a RAID calculation engine to read D ' from the on-chip cache U, and writing the D ' and the calculated new check data P ' back to V and X in the off-chip DDR respectively;
s30, the D 'and P' data in V and X space in the off-chip DDR are landed.
The invention reduces the storage requirement of the off-chip DDR by introducing the on-chip cache.
The RAID5 (n +1 disk group RAID) and RAID6 (n +2 disk group RAID) amplification factors are calculated as follows:
the RAID full stripe write process includes a "write through" mode and a "write through" mode.
In an embodiment of the present invention, when the host DDR is in a write-through mode, the moving new data D' to the on-chip cache space U of the RAID management chip further includes:
aggregating full stripes across IO ports;
after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM;
memory spaces V and X are applied in the off-chip DDR.
In an embodiment of the present invention, when in the write-through mode, the invoking RAID calculation engine reads D ' from the on-chip cache U, and writes D ' and the calculated new check data P ' back to V and X in the off-chip DDR, respectively, and then further includes: and releasing the on-chip cache space U.
In an embodiment of the present invention, when in the "write through" mode, the destaging D 'and P' data in V and X spaces in the off-chip DDR further comprises: releasing storage spaces V and X in the off-chip DDR; and then answers the host.
In an embodiment of the present invention, when the slave DDR is in the "write-back" mode, the moving of the new data D' to the on-chip cache space U of the RAID management chip further includes full stripe aggregation across the IO ports;
and after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM.
In an embodiment of the present invention, when the slave DDR is in the "write-back" mode, the slave DDR moves the new data D' to the on-chip cache space U of the RAID management chip, and then the slave DDR further includes a response host;
whether Cache data hit in the DDR is queried or not is judged, and a result a list is obtained;
and (4) performing a complement operation on the a list, and obtaining storage spaces V and X in the off-chip DDR.
Wherein the a list includes three results, miss, partial hit and full hit.
In an embodiment of the present invention, when the RAID calculation engine is in the "write back" mode, the calling RAID calculation engine reads D ' from the on-chip cache U, and writes D ' and the calculated new check data P ' back to V and X in the off-chip DDR, respectively, and then further includes releasing the on-chip cache space U.
In the embodiment of the present invention, when the data is in the "write back" mode, the step of dropping the data of D 'and P' in the space of V and X in the off-chip DDR is further included, and then the step of updating the Cache management mapping table and releasing the corresponding iCache page table is further included; memory space V and X in the off-chip DDR is released.
In the RAID processing process, the on-chip cache is used for partially unloading the storage bandwidth requirement of the off-chip DDR, so that the bandwidth of the upper computer in a sequential writing scene is improved.
It should be understood that although the steps are described above in a certain order, the steps are not necessarily performed in the order described. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, some steps of this embodiment may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
In one embodiment, referring to fig. 5, in an embodiment of the present invention, a terminal is further provided, which includes a processor 401, a communication interface 402, a memory 403, and a communication bus 404, where the processor 401, the communication interface 402, and the memory 403 complete communication with each other through the communication bus 404.
A memory 403 for storing a computer program;
the processor 401 is configured to execute the off-chip DDR bandwidth offload method in the RAID sequential write scenario when executing the computer program stored in the memory 403, and when executing the instruction, the processor implements the steps in the foregoing method embodiment:
s10, moving the new data D' from the DDR to an on-chip cache space U of the RAID management chip;
s20, calling a RAID calculation engine to read D ' from the on-chip cache U, and writing the D ' and the calculated new check data P ' back to V and X in the off-chip DDR respectively;
s30, the D 'and P' data in V and X space in the off-chip DDR are landed.
The invention reduces the storage requirement of the off-chip DDR by introducing the on-chip cache.
The RAID5 (n +1 disk group RAID) and RAID6 (n +2 disk group RAID) amplification factors are calculated as follows:
the RAID full stripe write process includes a "write through" mode and a "write through" mode.
In an embodiment of the present invention, when the host DDR is in a write-through mode, the moving new data D' to the on-chip cache space U of the RAID management chip further includes:
aggregating full stripes across IO ports;
after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM;
memory spaces V and X are applied in the off-chip DDR.
In an embodiment of the present invention, when in the "write through" mode, the invoking RAID calculation engine reads D ' from the on-chip cache U, and writes D ' and the calculated new check data P ' back to V and X in the off-chip DDR, respectively, and then further includes: and releasing the on-chip cache space U.
In an embodiment of the present invention, when in the "write through" mode, the destaging D 'and P' data in V and X spaces in the off-chip DDR further comprises: releasing storage spaces V and X in the off-chip DDR; and then answers the host.
In an embodiment of the present invention, when the slave DDR is in the "write-back" mode, the moving of the new data D' to the on-chip cache space U of the RAID management chip further includes full stripe aggregation across the IO ports;
and after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM.
In an embodiment of the present invention, when the slave DDR is in the write-back mode, the slave DDR moves the new data D' to the on-chip cache space U of the RAID management chip, and then the slave DDR further includes a response host;
querying whether Cache data in the DDR hits or not to obtain a result a list;
and (4) performing a complement operation on the a list, and obtaining storage spaces V and X in the off-chip DDR.
Wherein the a list includes three results, miss, partial hit and full hit.
In an embodiment of the present invention, when the RAID calculation engine is in the "write back" mode, the calling RAID calculation engine reads D ' from the on-chip cache U, and writes D ' and the calculated new check data P ' back to V and X in the off-chip DDR, respectively, and then further includes releasing the on-chip cache space U.
In the embodiment of the present invention, when the data is in the "write back" mode, the step of destaging the data of D 'and P' in the space of V and X in the off-chip DDR further includes updating the Cache management mapping table and releasing the corresponding iCache page table; memory space V and X in the off-chip DDR is released.
The communication bus mentioned in the above terminal may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this is not intended to represent only one bus or type of bus.
The communication interface is used for communication between the terminal and other equipment.
The Memory may include a Random Access Memory (RAM) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the device can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
The terminal comprises user equipment and network equipment. Wherein the user equipment includes but is not limited to computers, smart phones, PDAs, etc.; the network device includes, but is not limited to, a single network server, a server group consisting of a plurality of network servers, or a Cloud Computing (Cloud Computing) based Cloud consisting of a large number of computers or network servers, wherein Cloud Computing is one of distributed Computing, a super virtual computer consisting of a collection of loosely coupled computers. The terminal can be operated independently to realize the invention, and can also be accessed into the network and realize the invention through the interactive operation with other terminals in the network. The network where the terminal is located includes, but is not limited to, the internet, a wide area network, a metropolitan area network, a local area network, a VPN network, and the like.
The terminal comprises user equipment and network equipment. Wherein the user equipment includes but is not limited to computers, smart phones, PDAs, etc.; the network device includes, but is not limited to, a single network server, a server group consisting of a plurality of network servers, or a Cloud Computing (Cloud Computing) based Cloud consisting of a large number of computers or network servers, wherein Cloud Computing is one of distributed Computing, a super virtual computer consisting of a collection of loosely coupled computers. The terminal can be operated independently to realize the invention, and can also be accessed into the network and realize the invention through the interactive operation with other terminals in the network. The network where the terminal is located includes, but is not limited to, the internet, a wide area network, a metropolitan area network, a local area network, a VPN network, and the like.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In an embodiment of the present invention, there is also provided a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps in the above-described method embodiment:
s10, moving the new data D' from the DDR to an on-chip cache space U of the RAID management chip;
s20, calling a RAID calculation engine to read D ' from the on-chip cache U, and writing the D ' and the calculated new check data P ' back to V and X in the off-chip DDR respectively;
s30, the D 'and P' data in V and X space in the off-chip DDR are landed.
The invention reduces the storage requirement of the off-chip DDR by introducing the on-chip cache.
The RAID5 (n +1 disk group RAID) and RAID6 (n +2 disk group RAID) amplification factors are calculated as follows:
the RAID full stripe write process includes a "write through" mode and a "write through" mode.
In an embodiment of the present invention, when the host DDR is in a write-through mode, the moving new data D' to the on-chip cache space U of the RAID management chip further includes:
aggregating full stripes across IO ports;
after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM;
memory spaces V and X are applied in off-chip DDR.
In an embodiment of the present invention, when in the "write through" mode, the invoking RAID calculation engine reads D ' from the on-chip cache U, and writes D ' and the calculated new check data P ' back to V and X in the off-chip DDR, respectively, and then further includes: and releasing the on-chip cache space U.
In an embodiment of the present invention, when in the "write through" mode, the destaging D 'and P' data in V and X spaces in the off-chip DDR further comprises: releasing storage spaces V and X in the off-chip DDR; and then answers the host.
In an embodiment of the present invention, when the slave DDR is in the "write-back" mode, the moving of the new data D' to the on-chip cache space U of the RAID management chip further includes full stripe aggregation across the IO ports;
and after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM.
In an embodiment of the present invention, when the slave DDR is in the "write-back" mode, the slave DDR moves the new data D' to the on-chip cache space U of the RAID management chip, and then the slave DDR further includes a response host;
whether Cache data hit in the DDR is queried or not is judged, and a result a list is obtained;
and (4) performing a complement operation on the a list, and obtaining storage spaces V and X in the off-chip DDR.
Wherein the a list includes three results, miss, partial hit and full hit.
In an embodiment of the present invention, when the RAID calculation engine is in the "write back" mode, the calling RAID calculation engine reads D ' from the on-chip cache U, and writes D ' and the calculated new check data P ' back to V and X in the off-chip DDR, respectively, and then further includes releasing the on-chip cache space U.
In the embodiment of the present invention, when the data is in the "write back" mode, the step of destaging the data of D 'and P' in the space of V and X in the off-chip DDR further includes updating the Cache management mapping table and releasing the corresponding iCache page table; memory space V and X in the off-chip DDR is released.
It will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. An off-chip DDR bandwidth unloading method under a RAID sequence writing scene is applied to RAID full-stripe writing processing, and is characterized by comprising the following steps:
moving the new data D' from the DDR to an on-chip cache space U of the RAID management chip;
calling a RAID calculation engine to read D ' from the on-chip cache U, and writing the D ' and the calculated new check data P ' back to V and X in the off-chip DDR respectively;
the D 'and P' data in V and X spaces in the off-chip DDR are destaged.
2. The off-chip DDR bandwidth offload method in a RAID sequential write scenario of claim 1, wherein the RAID full stripe write process comprises a write-through mode and a write-conference mode.
3. The off-chip DDR bandwidth offloading method under RAID sequence write scenario of claim 2, wherein when in "write through" mode, the slave host DDR moves new data D' to an on-chip cache space U of a RAID management chip, before further comprising:
full stripe aggregation across IO ports;
after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM;
memory spaces V and X are applied in the off-chip DDR.
4. The off-chip DDR bandwidth offload method under RAID sequential write scenario of claim 3, wherein when in "write through" mode, said invoking RAID calculation engine reads D ' from on-chip cache U, and writes D ' and calculated new check data P ' back to V and X in the off-chip DDR, respectively, and then further comprises: and releasing the on-chip cache space U.
5. The off-chip DDR bandwidth offload method in RAID sequential write scenario of claim 4, wherein when in "write-through" mode, said destaging D 'and P' data in V and X space in off-chip DDR further comprises: releasing storage spaces V and X in the off-chip DDR; and then answers the host.
6. The off-chip DDR bandwidth offloading method under RAID sequence write scenario of claim 2, wherein when in "write back" mode, the slave DDR moves new data D' into an on-chip cache space U of the RAID management chip, before further comprising full stripe aggregation across IO ports;
and after the aggregation is successful, applying for a storage space U with the size of new data D' in the on-chip SRAM.
7. The off-chip DDR bandwidth offloading method under RAID sequence write scenario of claim 6, wherein when in "write back" mode, the slave host DDR moves new data D' to the on-chip cache space U of the RAID management chip, and then further comprises, answering the host;
whether Cache data hit in the DDR is queried or not is judged, and a result a list is obtained;
completing the list a to obtain storage spaces V and X in the off-chip DDR;
wherein the a list includes three results, miss, partial hit and full hit.
8. The off-chip DDR bandwidth offloading method under RAID sequential write scenario of claim 7, wherein when in "write back" mode, said invoking RAID calculation engine reads D ' from an on-chip cache U and writes D ' and calculated new parity data P ' back to V and X in the off-chip DDR, respectively, and then further comprising releasing an on-chip cache space U.
9. A terminal comprising a memory storing a computer program and a processor that when loaded and executed performs the steps of the off-chip DDR bandwidth offload method in a RAID sequential write scenario of any one of claims 1-8.
10. A storage medium storing a computer program which, when loaded and executed by a processor, implements the steps of the off-chip DDR bandwidth offload method in a RAID sequential write scenario of any one of claims 1-8.
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|---|---|---|---|---|
| CN115826882A (en) * | 2023-02-15 | 2023-03-21 | 苏州浪潮智能科技有限公司 | Storage method, device, equipment and storage medium |
| CN116126251A (en) * | 2023-04-04 | 2023-05-16 | 北京忆恒创源科技股份有限公司 | Method for realizing multi-concurrency writing, controller and solid-state storage device |
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