CN111115566A - Stress compensation method for MEMS wafer level packaging - Google Patents
Stress compensation method for MEMS wafer level packaging Download PDFInfo
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- CN111115566A CN111115566A CN201911358916.3A CN201911358916A CN111115566A CN 111115566 A CN111115566 A CN 111115566A CN 201911358916 A CN201911358916 A CN 201911358916A CN 111115566 A CN111115566 A CN 111115566A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00325—Processes for packaging MEMS devices for reducing stress inside of the package structure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0006—Interconnects
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a stress compensation method for MEMS wafer level packaging, which comprises the steps of processing a silicon wafer with a cap layer, and processing a silicon dioxide pattern structure which is completely mirror-symmetrical with the front side on the back side of the silicon wafer; then the silicon chip of the cap layer and the silicon chip of the device layer are processed by Si-SiO2Bonding the two layers together to form an SOI (silicon on insulator) sheet, and then finishing the processing of a device layer; when processing the silicon chip of the substrate layer, processing SiO which is completely mirror-symmetrical with the front side on the back side2/W/SiO2a/Au film layer structure; and finally, bonding the SOI wafer processed by the back mirror image film layer structure and the substrate layer silicon wafer together to finish packaging. The invention utilizes a mirror symmetry compensation method to balance the film stress at two sides of the piece to be bonded, and solves the MEMS wafer-level bonding packaging processThe problems of large bonding alignment deviation and low bonding strength caused by excessive wafer deflection in the process.
Description
Technical Field
The invention relates to a stress compensation method for MEMS wafer level packaging, and belongs to the field of micro-machining of micro-electro-mechanical systems (MEMS). To a method of reducing deflection of a sheet to be bonded using a mirror compensation method.
Background
The fundamental goal of MEMS device packaging is to serve a group of components with a specific function with minimal size and weight, minimal price and as simple a structure as possible. The MEMS wafer level packaging technology is a technology which takes a silicon wafer as a unit before a single MEMS chip is separated, realizes mechanical and electrical connection between different layers of the MEMS chip through the technical approaches of wafer bonding or film deposition and the like, and realizes independent sealing of each MEMS chip microstructure on the wafer. Compared with the device level packaging, the wafer level packaging ensures that the movable structure on the chip is not influenced by the subsequent procedures such as scribing and the like, improves the yield of the device, and can greatly save the packaging cost and reduce the packaging size. At present, the MEMS wafer level packaging technology has become the mainstream packaging technology of MEMS devices.
In the process of processing the MEMS wafer, a metal electrode film layer needs to be processed for realizing electrical connection, and insulating layer dielectric film layers, namely Si-SiO, need to be processed for realizing insulation between electrode layers2The bonding requires the processing of SiO2A film layer is formed, and an Au thin film layer is required to be processed by Au-Si bonding; the film layers have lattice mismatch, temperature change, deformation, phase change, structural defect and the like in the deposition processThe residual stress is inevitably generated in the thin film by the factors. The excessive residual stress can cause the wafer to be greatly deflected, the excessive deflection of the wafer to be bonded can bring great difficulty to bonding alignment, and the problems of local non-bonding and poor consistency on the wafer bonded wafer can be brought in the bonding process. The single-sided large stress can also reduce the mechanical strength of bonding, weaken the impact resistance and mechanical vibration resistance of the chip and further influence the reliability of the chip. In addition, the non-equilibrium stress can also affect the overall temperature stability of the device.
Disclosure of Invention
The technical problem solved by the invention is as follows: in order to solve the problems of large bonding alignment deviation and low bonding strength caused by overlarge wafer deflection in the MEMS wafer-level bonding packaging process, and the problems that the mechanical reliability of bonding packaging and the full-temperature stability of devices are reduced due to unbalanced stress, the invention provides a stress compensation method for MEMS wafer-level packaging.
The technical scheme of the invention is as follows:
a stress compensation method for MEMS wafer level packaging, the bonding packaging structure comprises: the device comprises a capping layer, a device layer and a substrate layer; the front surface of the sealing cap layer comprises a cavity structure and is used for Si-SiO2Bonded SiO2The back of the seal cap layer is provided with thermal oxidation SiO synchronously processed with the front2The device layer comprises a device structure, and the front surface of the substrate layer comprises a cavity structure, an Au film layer structure, a W electrode film layer structure and SiO2An insulating layer structure; Si-SiO is arranged between the front surface of the sealing cap layer and the back surface of the device layer2Directly bonding to form an SOI (silicon on insulator) sheet, and forming a package by Au-Si eutectic bonding between the front surface of the device layer of the SOI sheet and the front surface of the substrate layer after the device structure is processed;
processing SiO which is completely mirror-symmetrical with the front side on the back side of the sealing cap layer2A film layer structure;
then the packaging layer and the device layer are processed by Si-SiO2Directly bonding to form an SOI sheet;
processing a film layer structure which is completely mirror-symmetrical with the front side on the back side of the substrate layer silicon wafer;
and finally, bonding the substrate layer silicon wafer and the SOI which completes the processing of the device layer together to form the package.
Preferably, the specific steps are as follows:
(1) photoetching a mirror image symmetrical pattern of the back side and the front side of the cap layer silicon wafer;
(2) after photoetching is finished, the back side and the front side of the silicon chip with the cap layer are subjected to mirror symmetry SiO2Etching the pattern structure;
(3) passing the etched silicon chip of the cap layer and the device layer through Si-SiO2Bonded together to form an SOI wafer;
(4) according to SiO on the front side of the silicon wafer of the substrate layer2/W/SiO2Au film structure, respectively depositing SiO on the back of the substrate layer silicon wafer2、W、SiO2、Au；
(5) According to the pattern structure of the front surface of the silicon wafer of the substrate layer, respectively arranging SiO on the back surface of the silicon wafer of the substrate layer2、W、SiO2And patterning Au to process a film layer structure which is mirror-symmetrical with the front surface.
(6) And bonding the SOI wafer subjected to mirror symmetry film layer structure processing and the substrate layer silicon wafer together to complete packaging.
Preferably, step (1), photoetching is carried out on the back surface of the capping layer, and the photoresist can adopt AZ5214 or AZ4620, and the thickness of the photoresist is 1.7-3 μm; after exposure and development, the film is hardened for 30-60min at 80-120 ℃ by an oven or a hot plate.
Preferably, in step (2), SiO2The etching is carried out by adopting wet etching or dry etching; and with SiO of the front side2The films are etched using the same etching method and the same etching parameters.
Preferably, in the step (4), SiO on the back of the silicon wafer of the substrate layer2Film deposition, using PECVD or LPCVD to deposit, and SiO with the silicon chip front side of the substrate layer2And the films are deposited by the same deposition method and the same deposition parameters.
Preferably, in the step (4), the W, Au film on the back surface of the silicon wafer on the substrate layer is deposited by magnetron sputtering or electron beam evaporation, and the same deposition method and the same deposition parameters are adopted for the W, Au film on the front surface of the silicon wafer on the substrate layer.
Preferably, in the step (5), SiO on the back side of the silicon wafer of the substrate layer2、W、SiO2Patterning the Au film by wet etching or dry etching; and SiO with the front surface of the silicon wafer of the substrate layer2、W、SiO2And patterning Au by adopting the same method and the same process parameters.
Compared with the prior art, the invention has the beneficial effects that:
(1) the invention can effectively improve the bonding alignment precision and reduce the influence of alignment deviation on the device performance by using a relatively flat piece to be bonded;
(2) according to the invention, two wafers with smaller deflection are bonded, so that the problem that the local part of the wafer is not bonded can be effectively avoided, and the on-chip consistency of the bonding process is improved;
(3) the mirror symmetry stress distribution of the invention can improve the mechanical strength of bonding and the mechanical reliability of the chip;
(4) the balanced stress distribution on the two sides of the chip reduces the influence of the difference of the thermal expansion coefficients of different materials on the structural deformation of the chip under the temperature change, thereby improving the full-temperature stability of the chip.
Drawings
FIG. 1 is a schematic view of a package structure according to the present invention;
FIG. 2 is a process flow diagram of the present invention.
Detailed Description
The invention is further illustrated by the following examples.
The invention provides a stress compensation method for MEMS wafer level packaging, and a bonding packaging structure comprises the following steps: the device comprises a capping layer, a device layer and a substrate layer; the front surface of the sealing cap layer comprises a cavity structure and is used for Si-SiO2Bonded SiO2The back of the seal cap layer is provided with thermal oxidation SiO synchronously processed with the front2The device layer comprises a device structure, and the front surface of the substrate layer comprises a cavity structure, an Au film layer structure, a W electrode film layer structure and SiO2Insulating layer junctionStructuring; Si-SiO is arranged between the front surface of the sealing cap layer and the back surface of the device layer2Directly bonding to form an SOI (silicon on insulator) sheet, and forming a package by Au-Si eutectic bonding between the front surface of the device layer of the SOI sheet and the front surface of the substrate layer after the device structure is processed; processing SiO which is completely mirror-symmetrical with the front side on the back side of the sealing cap layer2A film layer structure, and passing the packaging layer and the device layer through Si-SiO2Directly bonding to form an SOI (silicon on insulator) wafer, processing a film layer structure which is completely mirror-symmetrical with the front surface on the back surface of the substrate layer silicon wafer, and finally bonding the substrate layer silicon wafer and the SOI which completes the processing of the device layer together to form a package; the packaging structure is schematically shown in fig. 1.
The stress compensation method for MEMS wafer level packaging specifically includes the steps as shown in fig. 2, including:
(1) photoetching a mirror image symmetrical pattern of the back side and the front side of the cap layer silicon wafer;
(2) after photoetching is finished, the back side and the front side of the silicon chip with the cap layer are subjected to mirror symmetry SiO2Etching the pattern structure;
(3) passing the etched silicon chip of the cap layer and the device layer through Si-SiO2Bonded together to form an SOI wafer;
(4) according to SiO on the front side of the silicon wafer of the substrate layer2/W/SiO2Au film structure, respectively depositing SiO on the back of the substrate layer silicon wafer2、W、SiO2、Au；
(5) According to the pattern structure of the front surface of the silicon wafer of the substrate layer, respectively arranging SiO on the back surface of the silicon wafer of the substrate layer2、W、SiO2And patterning Au to process a film layer structure which is mirror-symmetrical with the front surface.
(6) And bonding the SOI wafer subjected to mirror symmetry film layer structure processing and the substrate layer silicon wafer together to complete packaging.
Firstly, photoetching the back surface of the sealing cap layer, wherein the photoresist can adopt AZ5214 or AZ4620, and the thickness of the photoresist is 1.7-3 mu m; hardening the film for 30-60min at 80-120 ℃ by using an oven or a hot plate after the whirl coating.
Second, SiO2The etching of (3) can adopt wet etching or dry etching; and with SiO of the front side2And the film adopts the same etching method and the same etching parameters.
Thirdly, SiO on the back of the silicon wafer of the substrate layer2The film can be deposited by PECVD or LPCVD, and other chemical or physical vapor deposition methods can also be adopted; and SiO with the front surface of the silicon wafer of the substrate layer2The film adopts the same deposition method and the same deposition parameters; the W, Au film on the back of the silicon wafer of the substrate layer can be deposited by magnetron sputtering or electron beam evaporation, and other physical vapor deposition methods can also be adopted; and the W, Au film on the front side of the silicon wafer of the substrate layer adopts the same deposition method and the same deposition parameters.
Fourthly, SiO on the back of the silicon chip of the substrate layer2、W、SiO2The Au film can be patterned by wet etching or dry etching; and SiO with the front surface of the silicon wafer of the substrate layer2、W、SiO2And patterning Au by adopting the same method and the same process parameters.
The invention can effectively improve the bonding alignment precision and reduce the influence of alignment deviation on the device performance by using a relatively flat piece to be bonded; according to the invention, two wafers with smaller deflection are bonded, so that the problem that the local part of the wafer is not bonded can be effectively avoided, and the on-chip consistency of the bonding process is improved; the mirror symmetry stress distribution of the invention can improve the mechanical strength of bonding and the mechanical reliability of the chip;
the balanced stress distribution on the two sides of the chip reduces the influence of the difference of the thermal expansion coefficients of different materials on the structural deformation of the chip under the temperature change, thereby improving the full-temperature stability of the chip.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (7)
1. A stress compensation method for MEMS wafer level packaging is characterized in that a bonding packaging structure comprises the following steps: the device comprises a capping layer, a device layer and a substrate layer; the front surface of the sealing cap layer comprises a cavity structure and is used for Si-SiO2Bonded SiO2The back of the seal cap layer is provided with thermal oxidation SiO synchronously processed with the front2The device layer comprises a device structure, and the front surface of the substrate layer comprises a cavity structure, an Au film layer structure, a W electrode film layer structure and SiO2An insulating layer structure; Si-SiO is arranged between the front surface of the sealing cap layer and the back surface of the device layer2Directly bonding to form an SOI (silicon on insulator) sheet, and forming a package by Au-Si eutectic bonding between the front surface of the device layer of the SOI sheet and the front surface of the substrate layer after the device structure is processed;
processing SiO which is completely mirror-symmetrical with the front side on the back side of the sealing cap layer2A film layer structure;
then the packaging layer and the device layer are processed by Si-SiO2Directly bonding to form an SOI sheet;
processing a film layer structure which is completely mirror-symmetrical with the front side on the back side of the substrate layer silicon wafer;
and finally, bonding the substrate layer silicon wafer and the SOI which completes the processing of the device layer together to form the package.
2. The method of claim 1, further comprising the steps of:
(1) photoetching a mirror image symmetrical pattern of the back side and the front side of the cap layer silicon wafer;
(2) after photoetching is finished, the back side and the front side of the silicon chip with the cap layer are subjected to mirror symmetry SiO2Etching the pattern structure;
(3) passing the etched silicon chip of the cap layer and the device layer through Si-SiO2Bonded together to form an SOI wafer;
(4) according to SiO on the front side of the silicon wafer of the substrate layer2/W/SiO2Au film structure, respectively depositing SiO on the back of the substrate layer silicon wafer2、W、SiO2、Au；
(5) According to the pattern structure of the front surface of the silicon wafer of the substrate layer, respectively arranging SiO on the back surface of the silicon wafer of the substrate layer2、W、SiO2And patterning Au to process a film layer structure which is mirror-symmetrical with the front surface.
(6) And bonding the SOI wafer subjected to mirror symmetry film layer structure processing and the substrate layer silicon wafer together to complete packaging.
3. The stress compensation method for the MEMS wafer level package as claimed in claim 2, wherein: step (1), photoetching the back surface of the sealing cap layer, wherein the photoresist can adopt AZ5214 or AZ4620, and the thickness of the photoresist is 1.7-3 mu m; after exposure and development, the film is hardened for 30-60min at 80-120 ℃ by an oven or a hot plate.
4. The stress compensation method for the MEMS wafer level package as claimed in claim 2, wherein: in step (2), SiO2The etching is carried out by adopting wet etching or dry etching; and with SiO of the front side2The films are etched using the same etching method and the same etching parameters.
5. The stress compensation method for the MEMS wafer level package as claimed in claim 2, wherein: in the step (4), SiO on the back of the silicon wafer of the substrate layer2Film deposition, using PECVD or LPCVD to deposit, and SiO with the silicon chip front side of the substrate layer2And the films are deposited by the same deposition method and the same deposition parameters.
6. The stress compensation method for the MEMS wafer level package as claimed in claim 2, wherein: in the step (4), the W, Au film on the back surface of the silicon wafer on the substrate layer is deposited by magnetron sputtering or electron beam evaporation, and the same deposition method and the same deposition parameters are adopted for the W, Au film on the front surface of the silicon wafer on the substrate layer.
7. The stress patch of claim 2 for MEMS wafer level packagingThe compensation method is characterized by comprising the following steps: in the step (5), SiO on the back of the silicon wafer of the substrate layer2、W、SiO2Patterning the Au film by wet etching or dry etching; and SiO with the front surface of the silicon wafer of the substrate layer2、W、SiO2And patterning Au by adopting the same method and the same process parameters.
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Cited By (1)
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