CN101388364B - Electric isolation region forming method adopting low temperature process, single chip integration method - Google Patents
Electric isolation region forming method adopting low temperature process, single chip integration method Download PDFInfo
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Abstract
A method of forming electrical isolated areas by adopting low temperature technology, a monolithic integrated process and a chip are provided. The integration of MEMS and an integrated circuit component can be realized through firstly etching relevant part of a component layer of an insulating silicon chip through adopting the wet etching, the plasma dry etching or the deep-slot ion etching method to form relative isolated grooves, separating the chip into a plurality of electrical isolated areas by the isolated grooves, then generating an insulating dielectric layer on the component layer through adopting the lower-temperature process under 400 DEG C, leveling the surface of the insulating dielectric layer on the isolated grooves, then forming relative connecting holes on the relative position of the insulating dielectric layer of each electric isolated area which requires the electric connection through adopting the wet etching or the dry etching, finally depositing a metal layer onthe insulating dielectric layer, and forming a metal connecting wire which can metallically and mutually connect the connecting holes after the necessary etching, thereby realizing the necessary electric connection of relative electric isolated areas.
Description
Technical field
The present invention relates to a kind ofly go up to adopt low temperature process to form the method for electric isolation region, adopting low temperature process to form electric isolation region on the Silicon-On-Insulator substrate micro electro mechanical device adopted low temperature process formation electric isolation region with the single chip integrated method of integrated circuit (IC)-components and on the Silicon-On-Insulator substrate and the micro electro mechanical device and the integrated circuit (IC)-components monolithic integrated chip that form at Silicon-On-Insulator substrate (SOI).
Background technology
MEMS (micro electro mechanical system) (MEMS) is a new and high technology of high speed development in recent years, and it adopts advanced semiconductor preparing process, realizes the prepared in batches of MEMS device.Compare with the traditional fabrication technology, the device of MEMS fabrication techniques has obvious advantages at aspects such as volume, power consumption, weight and prices.
At present, the MEMS device is independently finished element manufacturing by different manufacturers according to its preparation flow separately usually with integrated circuit (IC) on different substrates, and then hybrid package is finished integrated to obtain corresponding holonomic system.This kind method benefit is that preparation technology's difficulty is little, and MEMS designs and preparation can be optimized separately, so this kind method obtained extensive use in a lot of fields, for example resistance pressure type transducer etc.Yet for some application that is subject to disturb, the transducer of types such as the piezoelectricity of high impedance output and electric capacity for example with the MEMS device with the integrated circuit monolithic is integrated more has superiority, can effectively reduce the interference noise influence and significantly improve the device overall performance.
Realize that MEMS device and the single chip integrated manufacture method of integrated circuit have three kinds: the first, finish the making of MEMS device earlier, and then on same substrate, finish the making of integrated circuit; The second, MEMS device and integrated circuit single-step process in manufacturing process is intersected mutually and is carried out; The third method i.e. " back semiconductor technology " (post-IC) is finished the integrated circuit of standard earlier, and then finish the making of MEMS device on same substrate.The third integrated way has many benefits, both can make full use of existing ripe standard integrated circuit preparation flow, can be because of not making MEMS device contamination integrated circuit processing equipment, and also help improving rate of finished products and reduce investment equipment.But the third integrated way also has shortcoming, because after the integrated circuit preparation is finished, can not bear high temperature more than 400 ℃ as the aluminium of metal electrode, can not adopt high-temperature technology in MEMS preparation of devices process subsequently like this, so just increase the single chip integrated technology difficulty of integrated circuit and MEMS.
Adopt Silicon-On-Insulator (Silicon on Insulator, the high-temperature technology that needs when SOI) substrate can be avoided making the MEMS device as the substrate of integrated circuit and MEMS device, usually, the SOI substrate by very thick body layer-of-substrate silicon, quite thin insulating oxide silicon intermediate layer (being buried silicon oxide layer), and very thin monocrystalline silicon top layer (being device layer) constitute.ADI (ADI) promptly utilizes the SOI-MEMS of the said firm technology to make the integrated accelerometer transducer at present, it is by MEMS device area and integrated circuit zone on the same SOI substrate of electric isolation, realize that simultaneously the MEMS device is connected with the necessary electricity of integrated circuit (IC)-components, yet the isolation technology that this technology adopts is the composite membrane that high-temperature oxydation silicon and polysilicon constitute, and can't accomplish post-IC technology completely.Also be that the composite membrane that utilizes high-temperature oxydation silicon and polysilicon to form is isolated MEMS device and integrated circuit when in addition, Microelectronic Institute of Peking University develops integrated gyrosensor on monocrystalline substrate.
Owing to all be to adopt high-temperature technology to form electric isolation, therefore all be difficult to accomplish post-IC technology completely, how to address this problem the real technical task that those skilled in the art need to be resolved hurrily that become.
Summary of the invention
The object of the present invention is to provide a kind of low temperature process that on the Silicon-On-Insulator substrate, adopts to form the method for electric isolation region.
Another object of the present invention is to provide a kind of adopts low temperature process to form electric isolation region on the Silicon-On-Insulator substrate and with micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components.
In order to achieve the above object, the low temperature process that adopts on the Silicon-On-Insulator substrate provided by the invention forms the method for electric isolation region, it comprises step: 1) adopt the appropriate section corrosion of the device layer that wet etching method has a Silicon-On-Insulator substrate according to designing requirement, and make corrosion proceed to the buried silicon oxide layer that described Silicon-On-Insulator substrate has to stop forming corresponding isolation channel, described Silicon-On-Insulator substrate is divided into a plurality of electric isolation regions by described isolation channel simultaneously; 2) adopt the low temperature process that is lower than 400 ℃ to generate an insulating medium layer being formed with on the device layer of described isolation channel, and the insulating medium layer that is in described isolation channel position is had an even surface, make the insulating medium layer that is generated only cover the bottom of described isolation channel; 3) adopt wet etching or dry etching method to form corresponding connecting hole according to the design needs in the insulating medium layer relevant position of each electric isolation region of needs electricity connection; 4) has deposit one metal level on the insulating medium layer of connecting hole, and make described metal level fill and cover each connecting hole, adopt wet etching or dry etching each connecting hole to be carried out metal interconnected metal connecting line to described metal level again, and then realize that the necessary electricity of corresponding each electric isolation region connects to form.
Preferably, when adopting the formed isolation channel degree of depth of wet etching less than 5 microns, in described step 4), adopt conventional thick photoresist to carry out the photoetching of large scale lines to form the metal connecting line, when adopting the formed isolation channel degree of depth of wet etching, in described step 4) formation metal connecting line process, adopt spraying process to be coated with photoresist greater than 5 microns.
Described dielectric layer material can be a kind of in silica, silicon nitride, polyimides (polyimide), Parylene (parylene), photoresist and the formed combination of air.
It is a kind of with micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components that the present invention also provides, it comprises step: 1) a Silicon-On-Insulator substrate is provided, and the device layer surface that it has has the second area that is used to make the first area of integrated circuit and is used to make micro electro mechanical device; 2) generate corresponding integrated circuit device by standard semiconductor technology in described first area according to the design needs; 3) adopt the aforementioned method that on the Silicon-On-Insulator substrate, adopts low temperature process to form electric isolation region to make both become electric isolation region described first area and second area electric isolation, and generate will the integrated circuit (IC)-components of described first area with carry out the metal connecting line that necessary electricity is connected at the MEMS of described second area device, and in the process of the metal connecting line that generates necessity, produce the figure of corresponding micro electro mechanical device according to designing needs; 4) adopt deep trouth reactive ion etching method or wet etching method to remove corresponding substrate part at the corresponding second area of the substrate surface place that described Silicon-On-Insulator substrate has to expose the buried silicon oxide layer appropriate section that described Silicon-On-Insulator substrate has; 5) adopt dry etching or wet etching to remove the buried silicon oxide layer appropriate section that is exposed out; 6) figure according to the micro electro mechanical device of producing adopts deep trouth reactive ion etching method etching to wear the corresponding device layer segment to form the micro electro mechanical device of corresponding suspension.
Wherein, formed micro electro mechanical device is a kind of in acceierometer sensor, integrated gyrosensor, integrated resonator, integrated microactrator, the integrated microrelay.
In addition, of the present invention another with micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components, comprise step: 1) a Silicon-On-Insulator substrate is provided, and the device layer surface that it has has the second area that is used to make the first area of integrated circuit and is used to make micro electro mechanical device; 2) generate corresponding integrated circuit device by standard semiconductor technology in described first area according to the design needs; 3) adopt the aforementioned method that on the Silicon-On-Insulator substrate, adopts low temperature process to form electric isolation region to make both become electric isolation region described first area and second area electric isolation, and generate will the integrated circuit (IC)-components of described first area with carry out the metal connecting line that necessary electricity is connected at the MEMS of described second area device, and in the process of the metal connecting line that generates necessity, produce the figure of corresponding micro electro mechanical device according to designing needs; 4) figure according to the micro electro mechanical device of producing adopts deep trouth reactive ion etching method etching to wear the corresponding device layer segment; 5) adopt wet etching, the corrosion of gas phase hydrofluoric acid and wet etching and gas phase hydrofluoric acid to corrode a kind of in the method that combines and remove the buried silicon oxide layer that is under the micro electro mechanical device to form the micro electro mechanical device of corresponding suspension.
Wherein, formed micro electro mechanical device is a kind of in acceierometer sensor, integrated gyrosensor, integrated resonator, integrated microactrator, the integrated microrelay.
In sum, the invention provides a kind of technology that on the SOI substrate, realizes electric isolation by low temperature process, and in the post-IC technology that this technology is applied to MEMS device and integrated circuit (IC) monolithic are integrated, this technology need not the standard integrated circuit technology is carried out any change, only need to carry out the preparation of MEMS device on the SOI substrate of standard integrated circuit technology finishing, so can make full use of existing ripe IC standard preparation flow, improve device yield and reduction investment greatly, well solve the problem of " product diversification " and " production technology variation " of restriction MEMS industrialized development equipment.
Description of drawings
For making the present invention be convenient to understand, will set forth the present invention in conjunction with following signal legend:
Figure 1A-1E is that the low temperature process that adopts on the Silicon-On-Insulator substrate of the present invention forms the embodiment one flow process schematic diagram of the method for electric isolation region;
Fig. 2 A-2E is that the low temperature process that adopts on the Silicon-On-Insulator substrate of the present invention forms the embodiment two flow process schematic diagrames of the method for electric isolation region;
Fig. 3 A-3D is the embodiment one flow process schematic diagram with micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components of the present invention;
Fig. 4 A-4E is the embodiment two flow process schematic diagrames with micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components of the present invention;
Fig. 5 A-5B is micro electro mechanical device of the present invention and integrated circuit (IC)-components monolithic integrated chip, and wherein, Fig. 5 A is the floor map of the MEMS device of formation, and Fig. 5 B is the generalized section along AA line among Fig. 5 A.
Embodiment
Below will be elaborated to the method that on the Silicon-On-Insulator substrate, adopts low temperature process to form electric isolation region of the present invention by specific embodiment.
Embodiment one:
See also Figure 1A-1E, the described method that adopts low temperature process to form electric isolation region on the Silicon-On-Insulator substrate can may further comprise the steps:
At first, shown in Figure 1A and Figure 1B, adopt deep trouth reactive ion etching method or dry plasma etch method that the device layer 21c appropriate section that one Silicon-On-Insulator (SOI) substrate 21 has is corroded according to designing requirement, and make corrosion proceed to the buried silicon oxide layer 21b (being between the device layer 21c and substrate 21a of described Silicon-On-Insulator substrate 21) that described Silicon-On-Insulator substrate 21 has to end to form corresponding isolation channel 33, described Silicon-On-Insulator substrate 21 is divided into electric isolation region 22 and 23 by described isolation channel 33 simultaneously, for example, normally on device layer 21c, be formed for earlier the mask layer 51 of deep trouth reactive ion etching (DRIE), this layer can directly be a photoresist, or for form the silica by low temperature (being lower than 400 ℃) technology deposit of figure by chemical wet etching, such as but not limited to using physical vapor deposition (PVD) technology (as sputter, evaporation) forms, silica with formation such as chemical vapor depositions (plasma-reinforced chemical vapor deposition PECVD and aumospheric pressure cvd APCVD), adopt the single-crystal silicon device layer 21c of deep trouth reactive ion etching method etching SOI substrate 21 then, its part is carved leave an isolation channel 33, and etching stopping is on buried silicon oxide layer 21b, so that described SOI substrate 21 is divided into electric isolation region 22 and 23.
Then, shown in Fig. 1 C, after removing the mask layer 51 that is used for deep etching, adopt the low temperature process that is lower than 400 ℃ to generate an insulating medium layer 31 being formed with on the device layer 21c of described isolation channel 33, and make the insulating medium layer 31 that is in described isolation channel 33 positions fill and cover fully described isolation channel 33, and it is had an even surface, the material of described insulating medium layer 31 can be with physical vapor deposition (PVD) technology (as sputter, evaporation) silica that forms, materials such as silicon nitride, also can be silica with formation such as chemical vapor depositions (plasma-reinforced chemical vapor deposition PECVD and aumospheric pressure cvd APCVD), materials such as silicon nitride, also can be with low-pressure chemical vapor phase deposition and form the Parylene material that (LPCVD) generates, the organic substance material that forms with spin-coating method or spraying process (as polyimides etc.).Generally poor than the insulating barrier (for example silica of thermal oxidation or LPCVD) that adopts high-temperature technology to generate by the conformality of the described insulating medium layer 31 of above-mentioned low temperature process deposit, do not reach complete filling to described isolation channel 33, generally can have the hole 52 that forms by air in the centre, but hole 52 does not influence the insulation characterisitic of isolation channel 33, and 31 surfaces of the insulating medium layer on the isolation channel 33 can accomplish to seal, and the surface of formation relatively flat, help follow-up processing.
Then, shown in Fig. 1 D, adopt wet etching or dry etching method to form corresponding connecting hole 53 according to the design needs at the electric isolation region 22 of needs electricity connection and 23 insulating medium layer 31 relevant positions, obviously, connecting hole 53 is in the both sides of described isolation channel 33.
At last, shown in Fig. 1 E, deposit one metal level on insulating medium layer 31 with connecting hole 53, and make described metal level fill and cover each connecting hole 53, adopt wet etching or dry etching forming the metal connecting line 32 that each connecting hole 53 is carried out the respective metal interconnection to described metal level again, and then realize that corresponding electric isolation region 22 is connected with 23 necessary electricity.
Embodiment two:
See also Fig. 2 A-2E, the described method that adopts low temperature process to form electric isolation region on the Silicon-On-Insulator substrate also can may further comprise the steps:
At first, shown in Fig. 2 A, adopt wet etching that the device layer 21c appropriate section that one Silicon-On-Insulator substrate 21 has is corroded according to designing requirement, and make corrosion proceed to the buried silicon oxide layer 21b (being between the device layer 21c and substrate 21a of described Silicon-On-Insulator substrate 21) that described Silicon-On-Insulator substrate 21 has to end to form corresponding isolation channel 33, described Silicon-On-Insulator substrate 21 is divided into electric isolation region 22 and 23 by described isolation channel simultaneously, for example, on device layer 21c, be formed for earlier wet etching mask layer 61, this layer can be photoresist, or for form the silica or the silicon nitride by low temperature (being lower than 400 ℃) technology (being lower than 400 ℃) deposit of figure by chemical wet etching, can adopt potassium hydroxide (KOH) or Tetramethylammonium hydroxide (TMAH) wet etching method to corrode the single-crystal silicon device layer 21c of SOI substrate 21 fully then, and stop on the buried silicon oxide layer 21b, at SOI substrate 21 top layers is under the situation of (100) monocrystalline silicon, if isolation channel 33 directions are along＜110〉direction, so because the characteristic of KOH or TMAH anisotropic corrosion, this moment, isolation channel 33 was trapezoidal shown in Fig. 2 B.
Then, shown in Fig. 2 C, the employing low temperature process generates an insulating medium layer 31 on the device layer 21c of described isolation channel 33 being formed with, and the insulating medium layer that is in described isolation channel 33 positions is had an even surface, and make the insulating medium layer 31 that is generated only cover the bottom of described isolation channel 33, the material of described insulating medium layer 31 can be with physical vapor deposition (PVD) technology (as sputter, evaporation) silica that forms, materials such as silicon nitride, also can be silica with formation such as chemical vapor depositions (plasma-reinforced chemical vapor deposition PECVD and aumospheric pressure cvd APCVD), materials such as silicon nitride, also can be with low-pressure chemical vapor phase deposition and form the Parylene material that (LPCVD) generates, with the organic substance material of spin-coating method or spraying process formation
(as polyimides etc.).
Then, shown in Fig. 2 D, adopt wet etching or dry etching method to form corresponding connecting hole 62 at the electric isolation region 22 of needs electricity connection and 23 insulating medium layer 31 relevant positions according to the design needs.
At last, shown in Fig. 2 E, deposit one metal level on insulating medium layer 31 with connecting hole 62, and make described metal level fill and cover each connecting hole 62, adopt wet etching or dry etching to form the metal connecting line 32 that each connecting hole 62 is carried out the respective metal interconnection to described metal level again, and then realize that corresponding electric isolation region 22 is connected with 23 necessary electricity, in the photo-etching technological process that forms metal connecting line 32, if described isolation channel 33 is superficial, for example the degree of depth can be carried out the photoetching of large scale lines (for example lines more than 10 microns) with the thick photoresist of routine below 5 microns; If described isolation channel 33 is deep, for example the degree of depth can replace spin-coating method commonly used be coated with the smooth problem of air spots that photoresist brings to overcome described isolation channel 33 with spraying process greater than 5 microns.
Below will to of the present invention micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components be elaborated by specific embodiment.
Embodiment one:
See also Fig. 3 A-3D, described micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components mainly can be may further comprise the steps:
At first, one Silicon-On-Insulator (SOI) substrate 21 is provided, the device layer 21c surface that it has has the second area 22 that is used to make the first area 23 of integrated circuit and is used to make micro electro mechanical device, and described SOI silicon chip 21 also has buried silicon oxide layer 21b and substrate 21a.
Then, generate corresponding integrated circuit device by standard semiconductor technology in described first area 23 according to the design needs, for example be field-effect transistor, resistance capacitance etc., for simplicity of illustration, the integrated circuit (IC)-components that is generated is to be the integrated circuit part of representative with MOS (metal-oxide-semiconductor) memory (MOSFET), and described MOSFET device comprises field oxide 26a, gate oxide 26b, source leakage doped region 24, grid conductive layer 25, dielectric insulation layer 26c, metal conducting layer 27 etc.
Then, as shown in Figure 3A, make both become electric isolation region with second area 22 electric isolation described first area 23 according to the aforementioned method that on the Silicon-On-Insulator substrate, adopts low temperature process to form electric isolation region, and generation is carried out the metal connecting line 32 that necessary electricity is connected with described first area 23 with described second area 22, and in the process that generates necessary metal connecting line 32, on metal, produce the figure 54 of corresponding micro electro mechanical device according to the design needs, more specifically, at first remove the dielectric insulation layer 26c (as silica) that when making integrated circuit (IC)-components, is created on described second area 22 with device layer 21c as described in exposing, produce isolation channel 33 according to above stated specification then, insulating medium layer 31 and metal connecting line 32, simultaneously when making connecting hole, also in the lump the figure 54 of micro electro mechanical device (MEMS) device is made, the MEMS device can be acceierometer sensor, integrated gyrosensor, integrated resonator, integrated microactrator or integrated microrelay etc.
Then, shown in Fig. 3 B, adopt deep trouth reactive ion etching method or wet etching method to remove corresponding substrate part at corresponding second area 22 places, substrate 21a surface that described Silicon-On-Insulator substrate 21 has, promptly formed back of the body chamber 34 thus to expose the buried silicon oxide layer appropriate section that described Silicon-On-Insulator substrate 21 has.
Then, shown in Fig. 3 C, adopt dry etching or wet etching to remove the buried silicon oxide layer appropriate section that is exposed out, promptly remove the buried silicon oxide layer segment in the back of the body chamber 34.
At last, shown in Fig. 3 D, figure 54 according to the micro electro mechanical device of producing adopts deep trouth reactive ion etching method etching to wear the corresponding device layer segment to form the micro electro mechanical device of corresponding suspension, for example, utilizing the method for dry etching is that part 35 etchings removal shown in mask is gone up device layer 21c promptly forms needed MEMS device with patterned insulating barrier 31.
Embodiment two:
See also Fig. 4 A-4E, described micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components mainly also can be may further comprise the steps:
At first, provide a Silicon-On-Insulator substrate 21, the device layer 21c surface that it has has the second area 22 that is used to make the first area 23 of integrated circuit and is used to make micro electro mechanical device.
Then, generate corresponding integrated circuit device by standard semiconductor technology in described first area 23 according to the design needs, for example be field-effect transistor, resistance capacitance etc., for simplicity of illustration, the integrated circuit (IC)-components that is generated is to be the integrated circuit part of representative with MOS (metal-oxide-semiconductor) memory (MOSFET), and described MOSFET device comprises field oxide 26a, gate oxide 26b, source leakage doped region 24, grid conductive layer 25, dielectric insulation layer 26c, metal conducting layer 27 etc.
Then, shown in Fig. 4 A, make both become electric isolation region with second area 22 electric isolation described first area 23 according to the aforementioned method that on the Silicon-On-Insulator substrate, adopts low temperature process to form electric isolation region, and generation is carried out the metal connecting line 32 that necessary electricity is connected with described first area 23 with described second area 22, and in the process that generates necessary metal connecting line 32, produce the figure 55 of corresponding micro electro mechanical device according to the design needs, more specifically, remove earlier the dielectric insulation layer 26c (as silica) that when making integrated circuit (IC)-components, is created on described second area 22 with device layer 21c as described in exposing, produce isolation channel 33 according to above stated specification then, insulating medium layer 31 and metal connecting line 32, simultaneously when making connecting hole, also in the lump the figure 55 of micro electro mechanical device (MEMS) device is made, the MEMS device can be acceierometer sensor, integrated gyrosensor, integrated resonator, integrated microactrator or integrated microrelay etc.
Then, shown in Fig. 4 B and 4C, figure 55 according to the micro electro mechanical device of producing adopts deep trouth reactive ion etching method etching to wear corresponding device layer 21c part, common described deep trouth reactive ion etching method comprises that elder generation generates one deck masking layer 28 in the surface low-temperature deposit, and described masking layer 28 can be with materials such as the silica of physical vapor deposition (PVD) technology (as sputter, evaporation) formation, silicon nitrides; Also can be the materials such as silica, silicon nitride that wait formation with chemical vapor deposition (plasma-reinforced chemical vapor deposition PECVD and aumospheric pressure cvd APCVD); Also can be with low-pressure chemical vapor phase deposition and form the Parylene material that (LPCVD) generates, or the organic substance material that forms with spin-coating method or spraying process (as polyimides etc.), and window 56 is left in photoetching, dry etching insulating barrier 28, to expose the MEMS device area, utilizing deep trouth reactive ion etching method is mask with patterned insulating medium layer 31, and part 57 etchings were removed shown in device layer 21c was gone up.
Then, shown in Fig. 4 D and 4E, adopt wet etching, a kind of in the method that the corrosion of corrosion of gas phase hydrofluoric acid and wet etching and gas phase hydrofluoric acid combines removes the buried silicon oxide layer 21c that is under the micro electro mechanical device to form the micro electro mechanical device of corresponding suspension, in the present embodiment, adopt wet etching earlier, corrosion of gas phase hydrofluoric acid and wet etching are removed with a kind of buried silicon oxide layer with MEMS device bottom that gas phase hydrofluoric acid corrodes in the method that combines, thereby the structure division that makes the MEMS device is (such as mass, around property beam or interdigital etc.) obtaining discharging can free movement, utilize dry etching or wet etching that the insulating medium layer on masking layer 28 and the MEMS device 31 is removed then, so just obtained final MEMS device.
Below will be elaborated to micro electro mechanical device of the present invention and integrated circuit (IC)-components monolithic integrated chip by specific embodiment.
See also Fig. 5 A and 5B, described micro electro mechanical device and integrated circuit (IC)-components monolithic integrated chip comprise at least: Silicon-On-Insulator substrate 21, integrated circuit district, metal interconnected district, and micro electronmechanical district.
Described SOI substrate 21 is made up of three parts, promptly be positioned at the single-crystal silicon device layer 21c of described SOI substrate 21 upper surfaces, be positioned at the substrate 21a of described SOI substrate 21 lower surfaces, buried silicon oxide layer 21b between device layer 21c and substrate 21a, substrate 21a is as mechanical support layer, thickness is generally the hundreds of micron, buried silicon oxide layer 21b stops layer and sacrifice layer certainly as corrosion, thickness is generally the hundreds of nanometer to several microns, single-crystal silicon device layer 21c is usually as the structure sheaf and the integrated circuit substrate of MEMS device, its thickness can offer isolation channel 33 so that described Silicon-On-Insulator substrate 21 is divided into electric isolation region 22 and 23 at described device layer 21c by several microns to more than 100 microns according to application need.
Described integrated circuit district is included in the integrated circuit (IC)-components of electric isolation region 23 generations of described isolation channel 33 1 sides, for example described integrated circuit (IC)-components is a field-effect transistor, resistance capacitance etc., for simplicity of illustration, the integrated circuit (IC)-components that is generated is to be the integrated circuit part of representative with MOS (metal-oxide-semiconductor) memory (MOSFET), described MOSFET device comprises field oxide 26a, gate oxide 26b, doped region 24 is leaked in the source, grid conductive layer 25, dielectric insulation layer 26c, metal conducting layer 27 etc., in the present embodiment, the integrated circuit (IC)-components that is generated is integrated accelerometer transducer 20 necessary integrated circuit (IC)-components.
Described metal interconnected district is included in first connecting hole that described integrated circuit district offers, second connecting hole of offering at the electric isolation region 22 of described isolation channel 33 opposite sides, the insulating medium layer 31 of the described isolation channel 33 of leap of the low temperature process generation that is lower than 400 ℃ is adopted on the device layer 21c surface of the described Silicon-On-Insulator substrate 21 between described first connecting hole and second connecting hole, and the metal interconnecting wires 32 that on described insulating medium layer 31, generates with described first connecting hole and the connection of second connecting hole, described insulating medium layer 31 can and cover described isolation channel 33 by whole fillings and cross over described isolation channel 33, also the insulating medium layer 31 that can be filled in isolation channel 33 on electricity is isolated, the inside of isolation channel 33 can be by dielectric 31 complete filling, also can assign to cross over described isolation channel 33 by covering described isolation channel 33 base portion, in addition, when filling, can have the cavity that forms by air, but must be smooth at insulating medium layer 31 upper surfaces that are in isolation channel 33 places, the so just unlikely technologies such as metal line that influence, have, described dielectric layer material can be silicon nitride again, polyimides (polyimide), Parylene (parylene), a kind of in the formed combination of photoresist and air.
Described micro electronmechanical district is included in the micro electro mechanical device of electric isolation region 22 generations of described isolation channel 33 opposite sides, micro electro mechanical device can be acceierometer sensor, integrated gyrosensor, integrated resonator, integrated microactrator or integrated microrelay etc., in the present embodiment, to generate integrated acceierometer sensor 20 (being the mechanical structure part) is that example describes, obviously, described mechanical structure part is isolated with described integrated circuit (IC)-components is filled in isolation channel 33 on electricity insulating medium layer 31, then is connected by the metal interconnecting wires 32 realization electricity that are laid on the insulating medium layer 31 of crossing over isolation channel 33 between integrated accelerometer transducer 20 and the integrated circuit (IC)-components.Described integrated accelerometer transducer 20 is processed on device layer 21c by dry etching or wet etching technology according to application need, mechanical beams structure for example, plate structure, interdigital structure etc.Integrated accelerometer transducer 20 comprises by deflection structure 42 and is fixed on acceleration sensitive mass 41 on the SOI buried silicon oxide layer 21b that responsive mass 41 will be parallel to the in-plane motion of SOI substrate 21 when being subjected to the acceleration effect; Interdigital 43 are suspended on the responsive mass 41, but form the movable plate electrode of interdigital capacitor; Interdigital 44a and 44b are the fixed polar plate of interdigital capacitor, are fixed on the buried regions silica 21b of SOI substrate 21.Movable electrode interdigital 43 simultaneously with the fixing interdigital 44a of electrode and 44b respectively with the adjacent (da＞db) of different polar plate spacing da with db, form a pair of differential capacitance 45a and 45b, when responsive mass 41 is done the plane when moving in the effect lower edge of X-axis acceleration X-axis, the differential capacitance of differential capacitance 44a and 44b changes, this capacitance variations is handled through the integrated circuit 23 of back, is converted into final electrical signal and changes.
In sum, the invention provides a kind of technology that on the SOI substrate, realizes electric isolation by low temperature process, and in the post-IC technology that this technology is applied to MEMS device and integrated circuit (IC) monolithic are integrated, this technology need not the standard integrated circuit technology is carried out any change, only need to carry out the preparation of MEMS device on the SOI substrate of standard integrated circuit technology finishing, so can make full use of existing ripe IC standard preparation flow, improve device yield and reduction investment greatly, well solve the problem of " product diversification " and " production technology variation " of restriction MEMS industrialized development equipment.In addition, with respect to the sensing system of hybrid package, have advantages such as size is little, performance is high, price is low, technology is simple with the monolithic integrated sensor system of above-mentioned way manufacturing.
Although disclose specific embodiments of the invention and accompanying drawing for the purpose of illustration, its purpose only is to help to understand content of the present invention and implement according to this, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various replacements, variation and modification all are possible.Therefore, the present invention should not be limited to most preferred embodiment and the disclosed content of accompanying drawing, and the scope of protection of present invention is as the criterion with the scope that claims define.
Claims (8)
1. one kind is adopted low temperature process to form the method for electric isolation region on the Silicon-On-Insulator substrate, it is characterized in that comprising step:
1) adopt wet etching method that the device layer appropriate section that one Silicon-On-Insulator substrate has is corroded according to designing requirement, and make corrosion proceed to the buried silicon oxide layer that described Silicon-On-Insulator substrate has to end to form corresponding isolation channel, described Silicon-On-Insulator substrate is divided into a plurality of electric isolation regions by described isolation channel simultaneously;
2) adopt the low temperature process that is lower than 400 ℃ to generate an insulating medium layer being formed with on the device layer of described isolation channel, and the insulating medium layer that is in described isolation channel position is had an even surface, make the insulating medium layer that is generated only cover the bottom of described isolation channel;
3) adopt wet etching or dry etching method to form corresponding connecting hole according to the design needs in the insulating medium layer relevant position of each electric isolation region of needs electricity connection;
4) has deposit one metal level on the insulating medium layer of connecting hole, and make described metal level fill and cover each connecting hole, adopt wet etching or dry etching each connecting hole to be carried out the metal connecting line that respective metal interconnects to described metal level again, and then realize that the necessary electricity of corresponding each electric isolation region connects to form.
2. the low temperature process that adopts on the Silicon-On-Insulator substrate as claimed in claim 1 forms the method for electric isolation region, it is characterized in that: when adopting the formed isolation channel degree of depth of wet etching less than 5 microns, in described step 4), adopt conventional thick photoresist to carry out the photoetching of large scale lines to form the metal connecting line.
3. the low temperature process that adopts on the Silicon-On-Insulator substrate as claimed in claim 1 forms the method for electric isolation region, it is characterized in that: when adopting the formed isolation channel degree of depth of wet etching, in described step 4) formation metal connecting line process, adopt spraying process to be coated with photoresist greater than 5 microns.
4. as the arbitrary described method that adopts low temperature process to form electric isolation region on the Silicon-On-Insulator substrate of claim 1 to 3, it is characterized in that: described dielectric layer material is a kind of in the formed combination of silica, silicon nitride, polyimides, Parylene, photoresist and air.
5. one kind with micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components, it is characterized in that comprising step:
1) provide a Silicon-On-Insulator substrate, the device layer surface that it has has the second area that is used to make the first area of integrated circuit and is used to make micro electro mechanical device;
2) generate corresponding integrated circuit device by standard semiconductor technology in described first area according to the design needs;
3) adopt any one method that forms electric isolation region of claim 1 to 4 to make both become electric isolation region described first area and second area electric isolation, and generate described first area and described second area are carried out the metal connecting line that necessary electricity is connected, and in the process of the metal connecting line that generates necessity, produce the figure of corresponding micro electro mechanical device according to designing needs;
4) adopt deep trouth reactive ion etching method or wet etching method to remove corresponding substrate part at the corresponding second area of the substrate surface place that described Silicon-On-Insulator substrate has to expose the buried silicon oxide layer appropriate section that described Silicon-On-Insulator substrate has;
5) adopt dry etching or wet etching to remove the buried silicon oxide layer appropriate section that is exposed out;
6) figure according to the micro electro mechanical device of producing adopts deep trouth reactive ion etching method etching to wear the corresponding device layer segment to form the micro electro mechanical device of corresponding suspension.
6. as claimed in claim 5 with micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components, it is characterized in that: formed micro electro mechanical device is a kind of in acceierometer sensor, integrated gyrosensor, integrated resonator, integrated microactrator, the integrated microrelay.
7. one kind with micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components, it is characterized in that comprising step:
1) provide a Silicon-On-Insulator substrate, the device layer surface that it has has the second area that is used to make the first area of integrated circuit and is used to make micro electro mechanical device;
2) generate corresponding integrated circuit device by standard semiconductor technology in described first area according to the design needs;
3) adopt any one method that forms electric isolation region of claim 1 to 4 to make both become electric isolation region described first area and second area electric isolation, and generate described first area and described second area are carried out the metal connecting line that necessary electricity is connected, and in the process of the metal connecting line that generates necessity, produce the figure of corresponding micro electro mechanical device according to designing needs;
4) figure according to the micro electro mechanical device of producing adopts deep trouth reactive ion etching method etching to wear the corresponding device layer segment;
5) adopt wet etching, the corrosion of gas phase hydrofluoric acid and wet etching and gas phase hydrofluoric acid to corrode a kind of in the method that combines and remove the buried silicon oxide layer that is under the micro electro mechanical device to form the micro electro mechanical device of corresponding suspension.
8. as claimed in claim 7 with micro electro mechanical device and the single chip integrated method of integrated circuit (IC)-components, it is characterized in that: formed micro electro mechanical device is a kind of in acceierometer sensor, integrated gyrosensor, integrated resonator, integrated microactrator, the integrated microrelay.
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| CN102315834B (en) * | 2011-05-04 | 2015-03-18 | 中国科学院宁波材料技术与工程研究所 | Current oscillator and preparation method thereof |
| CN102367165B (en) * | 2011-08-31 | 2015-01-21 | 华东光电集成器件研究所 | Method for interconnecting electrodes of MEMS (micro electro mechanical system) device based on SOI (silicon-on-insulator) |
| CN102344114B (en) * | 2011-11-04 | 2014-03-12 | 西北工业大学 | Preparation method for deep trench isolation channel |
| CN102381681B (en) * | 2011-11-29 | 2014-07-02 | 北京大学 | Micromechanical structure and integrated circuit monolithic integrated processing method |
| CN102381680B (en) * | 2011-11-29 | 2014-10-08 | 北京大学 | Micromechanical structures and integrated circuit monolithic integrated processing method |
| CN102431956B (en) * | 2011-11-29 | 2014-08-27 | 北京大学 | Monolithic integration processing method for unequal-height silicon structure and integrated circuit |
| CN102583225B (en) * | 2012-03-09 | 2015-05-06 | 上海先进半导体制造股份有限公司 | Fabricating method for one-dimensional large-scale multistage-step structure |
| CN105448642B (en) * | 2014-08-29 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN104310301B (en) * | 2014-11-12 | 2023-08-08 | 苏州盛维新电子科技有限公司 | MEMS adjustable optical attenuator chip integrated with micro-pad and manufacturing method thereof |
| CN105819392B (en) * | 2015-01-06 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1595633A (en) * | 2004-06-29 | 2005-03-16 | 北京大学 | A method for integrating CMOS circuit and bulk silicon MEMS uniwafer |
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2007
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| Publication number | Priority date | Publication date | Assignee | Title |
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