CN111104774A - Method for generating wafer map - Google Patents
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- CN111104774A CN111104774A CN201911330262.3A CN201911330262A CN111104774A CN 111104774 A CN111104774 A CN 111104774A CN 201911330262 A CN201911330262 A CN 201911330262A CN 111104774 A CN111104774 A CN 111104774A
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- wafer
- exposure unit
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
Abstract
The invention provides a method for generating a wafer map, wherein the wafer comprises a plurality of repeated exposure units, and the method for generating the wafer map comprises the following steps: drawing the outline of the wafer and the outline of the exposure unit; acquiring attribute information of the exposure unit, and drawing an exposure unit distribution diagram according to the attribute information of the exposure unit; copying the distribution diagram of the exposure unit, and arranging to generate a coarse wafer diagram; and removing the out-of-range chips in the coarse wafer map to generate a final wafer map. The method for generating the wafer map has the characteristics of high efficiency, convenience, intuition, high usability and strong usability, and the method for constructing the computer wafer map with convenience, high efficiency and strong adaptability can greatly improve the efficiency of automatic measurement of the semiconductor wafer, improve the output in unit time, reduce the consumption of human resources and avoid unnecessary human errors.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a method for generating a wafer map.
Background
The wafer map records distribution information of chips on the wafer, and when the wafer map is already available (for example, the wafer map given by a design draft), the wafer map may be directly introduced into the scanner. Without the wafer map, the wafer map needs to be generated later.
For only one chip on the wafer, the wafer can be simply generated according to the actual wafer size, the size of a single chip and the copy arrangement. For the chips with different types distributed on the wafer, the size and layout of each chip are different, and the generation of the wafer graph becomes more complicated.
In actual operation, different types of chips are manually identified and drawn one by one, sometimes test chips in a picture need to be manually removed, and particularly, in the process of carrying out defect scanning by a defect scanning machine, the test chips do not need to be scanned during defect scanning, so that the test chips need to be removed, the efficiency of manually drawing a wafer picture is extremely low, and mistakes are easy to occur.
The semi-automatic method needs a scanning machine to identify different chips after scanning according to the shapes of the chips, the chips with similar shapes cannot be distinguished, and the chips with poor chip boundary shapes are easy to over-kill (for example, functional chips are removed as test chips), so that manual correction is still needed, and the efficiency is low.
Disclosure of Invention
The invention aims to provide a method for generating a wafer map, which can improve the generation efficiency of the wafer map and avoid unnecessary manual errors caused by manual identification.
The invention provides a method for generating a wafer map, wherein a wafer comprises a plurality of repeated exposure units, and the method comprises the following steps:
drawing the outlines of the wafer and the exposure unit;
acquiring attribute information of the exposure unit, and drawing a chip distribution diagram of the exposure unit according to the attribute information of the exposure unit;
copying the distribution diagram of the exposure unit, and arranging to generate a coarse wafer diagram;
and removing the out-of-range chips in the coarse wafer map to generate a final wafer map.
Further, the attribute information of the exposure unit includes: the exposure unit includes the type of chip, the length and width of each of the chips, and the coordinates of each of the chips with respect to the exposure unit.
Further, the step of drawing an exposure unit distribution map according to the attribute information of the exposure unit includes:
drawing the rectangular outline of each chip according to the coordinate of each chip relative to the exposure unit, and simultaneously marking the code of each chip type in the rectangular outline of each chip.
Further, the chips in the exposure unit include a main chip and a test chip.
Further, after the drawing the distribution diagram of the exposure units, before the arranging and generating the coarse wafer diagram, the method further includes:
and rejecting the test chip in the exposure unit.
Further, the exposure unit comprises at least one chip.
Furthermore, the types of the chips included in the exposure unit are more than two, and the wafer is a multi-project wafer.
Further, the attribute information of the wafer, the exposure unit, and the chip is stored by a dedicated configuration file.
Further, the generated wafer map adopts txt text.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a method for generating a wafer map, wherein a wafer comprises a plurality of repeated exposure units, and a chip distribution map of the exposure units is drawn according to attribute information of the exposure units by acquiring the attribute information of the exposure units; copying the distribution diagram of the exposure unit, and arranging to generate a coarse wafer diagram; and removing the out-of-range chips in the coarse wafer map to generate a final wafer map. The method has simple operation and high automation degree, can greatly simplify the step of manually identifying/rejecting the test chip during the generation of the wafer map, and avoids unnecessary human errors.
Drawings
Fig. 1 is a schematic flow chart of a method for generating a wafer map according to an embodiment of the invention.
Fig. 2 to 6 are schematic diagrams illustrating steps of a method for generating a wafer map according to an embodiment of the invention.
Fig. 7 to 9 are schematic diagrams illustrating steps of a method for generating a wafer map according to another embodiment of the present invention.
Wherein the reference numbers are as follows:
1-a wafer; 10-an exposure unit; 2-a wafer; 20-exposure unit.
Detailed Description
The embodiment of the invention provides a method for generating a wafer map. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
A method for generating a wafer map, wherein a wafer comprises a plurality of repeated exposure units, as shown in fig. 1, the method comprises the following steps:
drawing the outline of the wafer and the outline of the exposure unit;
acquiring attribute information of the exposure unit, and drawing a chip distribution diagram of the exposure unit according to the attribute information of the exposure unit;
copying the distribution diagram of the exposure unit, and arranging to generate a coarse wafer diagram;
and removing the out-of-range chips in the coarse wafer map to generate a final wafer map.
Wherein, the out-of-range refers to the edge of the chip crossing (exceeding) the outline of the wafer; the exposure unit (shot) refers to a primary exposure pattern of a photoetching machine.
The method for generating a wafer map according to an embodiment of the invention is described in detail below with reference to fig. 2 to 6.
As shown in fig. 2, the wafer 1 includes a plurality of repeated exposure units 10, and the contour of the wafer 1 and the contour of the exposure units 10 are drawn. In this embodiment, the profile of the wafer 1 may be drawn according to the attribute information parameter of the wafer obtained by the graphical input interface, for example, the diameter of the wafer 1. The outline of one exposure unit 10 is drawn in the outline of the wafer 1. The outline of the exposure unit 10 is, for example, a rectangular frame. Specifically, the outline of the wafer 1 and the outline of the exposure unit 10 may be drawn by using a drawing software installed in a machine (e.g., a scanner), or by using a drawing software such as GDI, GDI +, OPEN GL, etc., where the outline of the exposure unit 10 is, for example, a rectangular frame, and the wafer 1 includes a plurality of repeated exposure units.
As shown in fig. 3, acquiring the attribute information of the exposure unit 10, and drawing a chip distribution diagram of the exposure unit according to the attribute information of the exposure unit 10; specifically, the attribute information of the exposure unit 10 includes: the exposure unit includes a type of chip, a length and a width of the chip, and coordinates of the chip with respect to the exposure unit.
Illustratively, the chips in the exposure unit 10 include a main chip a and test chips including a first test chip B and a second test chip C. The main chip A refers to a functional chip used for formal products, the test chip refers to a chip used for testing after chip production process technology or film production is completed, and the test chip is removed at a later stage. The exposure unit distribution map is drawn according to the types of chips (e.g., A, B and C) included in the exposure unit 10, the lengths and widths of the various chips, and the coordinates of the various chips with respect to the exposure unit 10.
Next, as shown in fig. 3 and 4, the test chips (first test chip B and second test chip C) in the exposure unit 10 are rejected.
Next, as shown in FIG. 5, the exposure unit distribution map is copied and arranged to generate a coarse wafer map. And copying the distribution diagram of the exposure units by a machine (such as a scanning machine) according to the attribute information (such as the width and the length of the exposure units) of the exposure units, the attribute information (such as the diameter) of the wafer and the size information of the scribing grooves, and arranging to generate a coarse wafer diagram. Specifically, a maximum exposure unit matrix is generated within the outline of the wafer, the exposure units are, for example, exposure units, and scribing grooves (not shown) are distributed in rows and columns between the exposure units. The exposure unit profile has been plotted to generate a coarse wafer map based on the wafer diameter, the length of the exposure unit, the width of the exposure unit, and the width of the scribe line. In this embodiment, the wafer includes a plurality of repeated exposure units, the row that generates the maximum exposure unit matrix is the ratio of the diameter of the wafer to the length of the exposure unit (vertical direction in the figure), and the row that generates the maximum exposure unit matrix is the ratio of the diameter of the wafer to the width of the exposure unit (horizontal direction in the figure).
Next, as shown in fig. 6, the out-of-range chips in the coarse wafer map are removed, and a final wafer map is generated. Wherein out-of-range refers to the edge where the chip crosses (exceeds) the outline of the wafer. The wafer map can be scaled to an equal-scale up or down version of the actual semiconductor wafer for easy viewing by the user.
The exposure unit comprises at least one chip. For example, the exposure unit may include one kind of chip, and the chips on the entire wafer are all the same. In the case of a single chip wafer, the wafer can be simply generated only according to the actual wafer size, the size of a single chip and the copy arrangement. The types of the chips in the exposure units can be more than or equal to two, for example, each exposure unit comprises a main chip and a test chip, and the whole wafer is provided with a plurality of repeated exposure units. The types of the chips in the exposure units may be various, that is, each exposure unit includes various chips (multi-project chips), the entire wafer is a plurality of repeated exposure units, and the wafer is a multi-project wafer.
In a multi-project wafer process, each wafer includes a plurality of different chips, and the multi-project wafer is a wafer of products of different processes sharing a set of mask plates for saving development cost. A Multi-Project Wafer (MPW) is a Wafer that a plurality of integrated circuit designs with the same process are placed on the same Mask (also called a Reticle) and then subjected to Wafer flow, and after the Wafer is manufactured, tens of Wafer core samples can be obtained from each design Project, which is enough for experiments and tests in the stage of prototype design. The manufacturing cost is distributed by all projects participating in the multi-project wafer according to the chip area occupied by the projects, the cost is only 5% -10% of the prototype manufacturing cost of each project, the product development risk is greatly reduced, and the threshold for cultivating the talents of integrated circuit designers and the threshold for starting small and medium-sized integrated circuit designers are greatly reduced.
As the technology of integrated circuits is continuously improved, the minimum design size is also continuously reduced, and the number of devices per unit area of a chip is also increasing. Therefore, in the stage of designing and developing the integrated circuit, designers often adopt a plurality of project wafers, a plurality of integrated circuit designs with the same process are placed on the same wafer for wafer flow, and dozens of wafer samples can be obtained for each design variety after wafer flow, and the quantity is enough for experiments and tests in the stage of designing and developing. Meanwhile, the experiment expense is divided by all projects participating in the MPW according to the area, so that the development cost and the new product development risk are reduced, the threshold of medium and small integrated circuit design enterprises in starting is reduced, and the serious waste of resources caused by single experiment flow is reduced. MPW wafers are typically produced as a pattern space (die) by each exposure unit (shot) of the reticle.
A method for generating a wafer map according to another embodiment of the present invention is described in detail below with reference to fig. 7 to 9. As shown in fig. 7 to 9, the wafer 2 is a multi-project wafer, and one multi-project wafer includes a plurality of exposure units 20, and each exposure unit 20 includes a plurality of kinds of chips (multi-project chips) in order to reduce cost and development risk and shorten the development cycle. The exposure unit 20 includes, for example, D, E, F, G four kinds of chips. The outline of the wafer 2 and the outline of the exposure unit 20 are drawn. Specifically, the outline of the exposure unit 20 may be drawn by using a self-contained drawing software in a machine (e.g., a scanner), and the outline of the exposure unit 20 is, for example, a rectangular frame.
The attribute information of each of the chips (e.g., D, E, F and G) in the exposure unit 20, such as the chip length, the chip width, the width of the scribe line between adjacent chips, the blank size, etc., is acquired, and the distribution positions of the various chips in the exposure unit 20 are drawn. The coordinates of each chip with respect to the exposure unit 20 are determined according to the attribute information of each chip and the rectangular frame of the exposure unit 20.
A rectangular outline of each chip is drawn according to coordinates of each chip with respect to the exposure unit 20, while a code number of each chip type, for example, D, E, F and G chips, is labeled within the rectangular outline of each chip. As shown in fig. 8, the exposure unit distribution map is replicated and arranged to generate a coarse wafer map. As shown in fig. 9, the out-of-range chips in the coarse wafer map are removed to generate the final wafer map. The wafer map generated by the embodiment has an intuitive display effect, and the current chip type distribution, relative position and absolute position can be directly seen from the wafer map, so that the actual distribution condition of the wafer is more intuitively reflected. The remaining portion between the various chips is left blank. If the sum of the total widths of the various chips in the exposure unit 20 is greater than the width of the exposure unit 20 (in the horizontal direction in the figure), or the sum of the total lengths of the various chips is greater than the length of the exposure unit 20 (in the vertical direction in the figure), an alarm message indicating that the size is out of range is given.
The method for creating the chip distribution diagram is simple, is close to the habit of using a computer by an operator, draws a rectangular frame by using a mouse or automatically generates the chip distribution diagram by inputting the number of rows, the number of columns, the width of the columns and the height of the rows, and is faster and more efficient.
In this embodiment, the attribute information of the wafer, the exposure unit, and various chips, and the generated wafer map may be stored in a dedicated configuration file, for example, using txt text. And the external program can call the text content of txt and has strong interaction capacity with the external program. Because of the information of various chip types, absolute positions, relative positions and the like, the external program can directly carry out the operation and the attribute retrieval (such as position, size, type and the like) on various chips (such as direct positioning from a diagram to a specified chip).
A wafer map is a circular wafer cut into multiple chiplets of a specified size. The wafer map is an important clue for tracing the cause of the abnormal product, and the chip position with the abnormal product can be found out through the spatial distribution condition and the model analysis of the wafer map. In a CP (circuit probe) test of a Wafer, a Wafer map (Wafer map) is widely used for a Wafer, and according to a CP test result obtained by the Wafer map, the Wafer map can be used for data analysis (data analysis), chip dicing (Die saw), chip picking (Die pick up), and the like, so that the work efficiency can be improved.
In summary, the present invention provides a method for generating a wafer map, in which the present embodiment shows a chip distribution map in the exposure unit, and the chip distribution map covers distribution positions of various chips in the exposure unit (for example, horizontal and vertical coordinates of the chips with respect to the wafer center), chip type codes, chip codes, and the like. The generated wafer map comprises wafer attribute information, and the parameters comprise: wafer number, wafer diameter, chip number, chip width, chip length, chip abscissa, and chip ordinate. The attribute information of the chip includes: the type of the chip, the number of the chip, the relative coordinate position of the chip on the wafer, and the state information of the chip.
The method for constructing the computer wafer map has the advantages of being efficient, convenient, visual, highly available and easy to use, and capable of greatly improving the efficiency of automatic measurement of the semiconductor wafer, improving the output in unit time, reducing the consumption of human resources and avoiding unnecessary human errors.
Those of ordinary skill in the art will understand that: all or a portion of the steps to implement the various method embodiments described above may be accomplished by hardware associated with the program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs the steps comprising the method embodiments described above: the storage medium of the foregoing includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (9)
1. A method for generating a wafer map, wherein the wafer comprises a plurality of repeated exposure units, is characterized by comprising the following steps:
drawing the outline of the wafer and the outline of the exposure unit;
acquiring attribute information of the exposure unit, and drawing a chip distribution diagram of the exposure unit according to the attribute information of the exposure unit;
copying the distribution diagram of the exposure unit, and arranging to generate a coarse wafer diagram;
and removing the out-of-range chips in the coarse wafer map to generate a final wafer map.
2. The method for generating a wafer map according to claim 1, wherein the attribute information of the exposure unit includes: the exposure unit includes the type of chip, the length and width of each of the chips, and the coordinates of each of the chips with respect to the exposure unit.
3. The method for generating a wafer map according to claim 2, wherein the step of drawing a distribution map of exposure units based on the attribute information of the exposure units comprises:
drawing the rectangular outline of each chip according to the coordinate of each chip relative to the exposure unit, and simultaneously marking the code of each chip type in the rectangular outline of each chip.
4. The method for generating the wafer map of claim 1, wherein the chips in the exposure unit include a master chip and a test chip.
5. The method for generating a wafer map as claimed in claim 4, wherein after the drawing the distribution map of the exposure units, before arranging to generate a coarse wafer map further comprises:
and rejecting the test chip in the exposure unit.
6. The method for generating a wafer map of claim 1, wherein the exposure unit comprises at least one chip.
7. The method for generating a wafer map of claim 6, wherein the exposure unit includes more than two types of chips, and the wafer is a multi-project wafer.
8. The method for generating a wafer map according to any one of claims 1 to 7, wherein attribute information of the wafer, the exposure unit, and the chip is stored by a dedicated configuration file.
9. The method for generating a wafer map as claimed in claim 8, wherein the generated wafer map is stored using txt text.
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| CN114548019A (en) * | 2022-04-25 | 2022-05-27 | 成都复锦功率半导体技术发展有限公司 | Cutting layout design method suitable for introducing custom chip and chip prepared by cutting layout design method |
| CN114548020A (en) * | 2022-04-25 | 2022-05-27 | 成都复锦功率半导体技术发展有限公司 | Layout design method of multi-model chip, chip prepared by same and terminal |
| CN114548015A (en) * | 2022-04-21 | 2022-05-27 | 成都复锦功率半导体技术发展有限公司 | Semiconductor laser cutting MPW layout design method and chip and terminal prepared by method |
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