CN111092773B

CN111092773B - PCIE (peripheral component interface express) switching chip port configuration system and method supporting virtual switching

Info

Publication number: CN111092773B
Application number: CN201911354633.1A
Authority: CN
Inventors: 杨珂; 张建波; 赵姣; 崔飞飞
Original assignee: Chengdu Huada Jiutian Technology Co ltd
Current assignee: Chengdu Huada Jiutian Technology Co ltd
Priority date: 2019-12-25
Filing date: 2019-12-25
Publication date: 2022-06-21
Anticipated expiration: 2039-12-25
Also published as: CN111092773A

Abstract

A PCIE switching chip port configuration system and method supporting virtual switching comprises the following steps: the port controller is used for realizing the functions of a medium access control layer, a data link layer and a transaction layer of a physical layer; the physical layer interface realizes the functions of a physical medium adaptation layer and a physical coding sublayer of the PCIE physical layer; the routing module receives routing information from the port controller, searches for a route according to the routing information, and acquires a processing mode of the data packet and a transceiving port number; the EEPROM interface controller is used for reading external EEPROM configuration information and sending the external EEPROM configuration information to the configuration module; the configuration module is used for receiving configuration information, configuring the ports into upstream ports or downstream ports, dividing virtual switching areas in a chip and controlling the enabling of each port; and the crossbar switch is used for forwarding the data packet passing through the PCIE switching chip. The invention can rapidly complete the port configuration and meet the time limit requirement of the initialization of the PCIE switching chip.

Description

PCIE (peripheral component interface express) switching chip port configuration system and method supporting virtual switching

Technical Field

The invention relates to the technical field of Peripheral Component Interconnect Express (PCIE) of a computer, in particular to a PCIE switching chip supporting virtual switching.

Background

With the development of computing technology, in recent years, a number of high-density modular server platforms, or open blades, have appeared, which require that the associated PCIE switch be capable of providing partition functions.

Fig. 1 is a schematic diagram of an existing multi-host system, and as shown in fig. 1, in the existing multi-host system, three servers are connected through the same PCIE switch chip, partition configuration is performed through the PCIE switch chip, and according to a change of a task, an I/O device connected to the switch chip is arbitrarily allocated among a server a, a server B, and a server C without power off. When a Basic Input Output System BIOS (abbreviation of Basic Input Output System) or an operating System of each server enumerates a PCIE bus, only a virtual bridge and I/O devices allocated to the BIOS or the operating System are found, and a plurality of partitions do not interfere with each other.

In the multi-host system, when a plurality of servers are connected and connected through the same PCIE switch chip, if partitioning is not performed, a problem may occur, because a plurality of operating systems enumerate virtual bridges and I/O devices in the same PCIE system respectively and allocate access addresses to the virtual bridges and the I/O devices, a conflict may occur at this time. In order to realize the above functions, PCIE switch chips supporting the partition function are developed accordingly.

Disclosure of Invention

In order to solve the defects of the prior art, the invention aims to provide a system and a method for configuring a port of a PCIE switch chip supporting virtual switching, which can realize multiple virtual switching on one PCIE switch chip, ensure that the port configuration is completed quickly, and meet the time limit requirement of a PCIE protocol for initialization of the PCIE switch chip.

In order to achieve the above object, the present invention provides a PCIE switch chip port configuration system supporting virtual switch, including at least three ports, a routing module, an EEPROM interface controller, a configuration module, and a crossbar switch,

the port comprises a port controller and a physical layer interface;

the port controller is used for realizing the functions of a medium access control layer, a data link layer and a transaction layer of a physical layer;

the physical layer interface realizes the functions of a physical media adaptation layer and a physical coding sublayer of the PCIE physical layer; transmitting a data packet sent by an external device to a PCIE switching chip to a port controller; forwarding the data packet sent by the port controller to an external device;

the routing module is used for receiving routing information from a port controller, searching for a route according to the routing information, and acquiring a processing mode and a receiving or output port number of the data packet;

the EEPROM interface controller is used for reading external EEPROM configuration information and sending the external EEPROM configuration information to the configuration module;

the configuration module is configured to receive configuration information and configure the port, configure the port as an upstream port or a downstream port, divide a virtual switch area inside a chip, and control enabling of each port;

the crossbar is used for forwarding the data packet passing through the PCIE switching chip.

Further, the port comprises a fixed port number and a variable device number, when the port is configured as an upstream port, the upstream port device number is set to be 0, and when the port is configured as a downstream port, the downstream port device number is the fixed port number.

Further, when the port is configured as an upstream port, the upstream port is configured to receive a type 0 configuration request packet, extract configuration information of the upstream port, perform port configuration according to the configuration information, extract a type and routing information of a non-type 0 configuration request packet, and send the non-type 0 configuration request packet to the routing module;

when the port is configured as a downstream port, the downstream port discards the type 0 and type 1 configuration request packets received from the downstream link, receives and extracts the type and routing information of the non-type 0 or non-type 1 configuration request packets and sends the packets to the routing module.

Further, the port controller may be configured to,

when forwarding the data packet, sending the data packet and an output port number of the data packet to the crossbar;

receiving the configuration information of the configuration module, performing read or write operation on a port register according to the configuration information, wherein an upstream port controller can directly generate a configuration completion data packet according to an operation result of a local port register, a downstream port controller cannot directly generate the configuration completion data packet according to the read or write operation result of the local port register by the configuration module, but can feed back the operation result to the configuration module, the configuration module sends the configuration completion data packet to the upstream port controller, and the upstream port controller generates the configuration completion data packet of the downstream port register; the upstream port controller sends the generated configuration completion data packet to the physical layer interface through an output side, and the physical layer interface sends the configuration completion data packet to an output link;

the data packet forwarded by the cross switch is forwarded directly or after being processed;

and processing the power management message packet of which the destination receiver is the port according to the requirement of the PCIE protocol.

Further, a virtual switch configuration register group composed of a port indication register included in the virtual switch, a virtual switch upstream port indication register, and a virtual switch enable register is included, wherein,

a port indication register included in said virtual switch that defines a port included in each of said virtual switch zones;

the virtual switching upstream port indication register is used for indicating an upstream port number corresponding to each virtual switching area;

the virtual swap enable register is used for defining an enable bit of the virtual swap.

Further, the routing information includes a type, a destination ID, and a destination address of the packet header, and for an implicit routing message packet, an eight-bit message encoding of the implicit routing message packet is also included.

Further, the routing module further comprises a reading unit and a generating unit,

the reading unit is used for reading each port pre-readable memory base address register, a pre-readable memory base address high 32-bit register, a memory base address register, an input and output base address high 16-bit register, a pre-readable memory limit high 32-bit register, a memory limit register, an input and output high 16-bit limit register, a command register, a primary bus number register, a secondary bus number register, a subordinate bus number register and the upstream port base address register;

the generation unit is used for generating an IO address routing table, a memory address routing table, an ID routing table and an implicit routing table based on virtual switching.

Further, each entry of the routing table comprises a set of registers, and each entry represents forwarding/receiving/discarding of the data packet meeting the conditions listed by the entry;

and the routing table is used for limiting the data packet to be transmitted between the ports included in the current virtual switching area.

Further, in the IO address routing table, each entry includes a destination IO address range, a processing manner of the data packet, and an output port number of the data packet;

each entry of the memory address routing table comprises a destination memory address range, a processing mode of the data packet and an output/receiving port number;

each entry of the ID routing table comprises a destination bus number range, a processing mode of the data packet and an output/receiving port number;

each entry of the implicit routing table includes a message routing type subfield, a message encoding, a processing mode of the data packet, and an output/receive port number.

Further, the routing module is further configured to feed back a route lookup result to the port controller.

Furthermore, the crossbar is further configured to receive a data packet and an output port number of the data packet, and send the data packet to a corresponding output port controller according to the output port number.

In order to achieve the above object, the present invention further provides a PCIE switch chip port configuration method supporting virtual switch, including the following steps:

1) an external EEPROM chip carries out initialization configuration on all port registers through a configuration module;

2) the configuration module reads the information of the virtual switching configuration register group from the port controller, divides a virtual switching area, enables the link of each enabled port, forbids the link of the disabled port, and enables the link of each enabled port to start to enter link training and initialization;

3) allocating a primary bus number, a secondary bus number and a subordinate bus number for each port, and allocating system addresses;

4) generating an IO address routing table, a memory address routing table, an ID routing table and an implicit routing table based on virtual switching for each port;

5) and the port controller receives and analyzes the data packet, obtains the processing mode of the data packet and the receiving and output port of the data packet according to the type and the routing information of the data packet, and performs read and/or write operation on the port.

Further, the step 3) of performing system address allocation includes,

allocating system addresses for a base address register of an upstream port of each virtual switch area, a pre-readable memory base address register, a pre-readable memory base address high-order 32-bit register, a memory base address register, an input-output base address high-order 16-bit register, a pre-readable memory limit high-order 32-bit register, a memory limit register, an input-output limit register and an input-output high-order 16-bit limit register;

allocating system addresses to a pre-readable memory base register, a pre-readable memory base upper 32-bit register, a memory base register, an input/output base upper 16-bit register, a pre-readable memory limit upper 32-bit register, a memory limit register, an input/output limit register, and an input/output upper 16-bit limit register of a downstream port of each virtual switch region.

Further, each entry of the IO routing table includes: a destination IO address range, a processing mode of the data packet and an output port number of the data packet;

the memory address routing table, each entry of which comprises: destination memory address range, packet processing mode and output/receive port number;

an ID routing table, each entry of which includes: destination bus number range, packet processing mode and output/receive port number;

an implicit routing table, each entry of which includes, a message routing type subfield, a message encoding, a processing mode of a packet, and an output/receive port number.

Further, the step 5) further comprises,

when the upstream port controller receives the transaction layer data packet, extracting the packet header of the data packet and analyzing the packet header;

if the type 0 configuration request packet is received, the upstream port controller receives the configuration request packet, performs read or write operation on a corresponding port register, and returns a completion packet according to the specific situation of the read or write request execution;

if a type 1 configuration request packet is received, the upstream port controller extracts a type field and a destination ID number from a data packet header and sends the type field and the destination ID number to a routing module; the routing module searches for the route, and determines whether to send the data packet to the cross switch or extract a configuration read-write instruction from the data packet and send the configuration read-write instruction to the configuration module according to the searched result; when sending a data packet to the crossbar switch, the output port number of the data packet must also be sent to the crossbar switch, and the crossbar switch sends the data packet to the corresponding output port according to the data packet and the output port number of the data packet.

Further, the step 5) further comprises,

if the upstream port controller receives the memory request packet, the type field and the destination address extracted from the data packet header are sent to a routing module;

the routing module carries out routing search, obtains an output port number or a receiving port number according to a search result, and determines whether a data packet is sent to the cross switch or a read/write instruction for accessing the port or a downstream port is extracted from the data packet;

when the data packet is sent to the cross switch, the output port numbers of the data packet are sent to the cross switch together; the crossbar switch sends the data packet to a corresponding output port according to the data packet and the output port number of the data packet;

if the command is a read/write command for accessing the port, the upstream port controller completes subsequent operations according to the read/write command, generates a corresponding completion packet according to the operation result and the requirement, and sends the completion packet to an upstream port output link; if the read-write instruction is a read-write instruction for accessing the downstream port, the extracted read-write instruction is sent to the configuration module and is transmitted to the downstream port controller by the configuration module, and the downstream port controller carries out read-write operation on the port register according to the read-write instruction; the downstream port controller feeds back the read/write result to the upstream port controller through the configuration module, and the upstream port controller generates a corresponding completion packet according to needs and sends the completion packet to an upstream port output link.

Further, the step 5) further comprises,

if the upstream port controller receives an IO request packet, sending the type field and the destination address extracted from the packet header of the data packet to a routing module; the routing module searches an IO routing table according to the type field and the destination address of the data packet to obtain the processing mode and the output port number of the data packet;

the upstream port controller sends the data packet and the output port number of the data packet to the cross bar switch, and the cross bar switch sends the data packet to the corresponding output port according to the output port number of the data packet and the data packet.

Further, the step 5) further comprises,

if the upstream port controller receives a message request packet, extracting a type field and an eight-bit message code of the message packet from a data packet header, and if the data contains a destination ID and also needs to extract a destination ID number, sending the data to a routing module; the routing module determines which routing table needs to be searched according to the processing mode of the data packet according to the routing type subfield of the data packet, and obtains the processing mode of the data packet, the output port number or the receiving port number according to the searching specified routing table; if the receiving is the upstream port receiving, the upstream port controller processes the receiving; if the output is the output, the output is sent to the corresponding output port controller through the cross bar switch, and the output port controller forwards the output signal after processing or directly forwards the output signal without processing.

Still further, the step 5) further comprises,

when the downstream port controller receives the request packet, the type field of the extracted packet and other routing related information are sent to a routing module; the routing module carries out routing search, forwards, receives or discards the data packet according to the search result, and instructs the downstream port controller to discard the memory request packet from the downstream link for accessing the PCIE chip port register;

after receiving the data packet forwarded from the crossbar switch, the port controller further processes or directly forwards the data packet to the physical layer interface through the output side of the port controller, and then sends the data packet to the output link through the physical layer interface.

The PCIE switching chip port configuration system and the method supporting virtual switching provided by the invention have the following beneficial effects that:

1) the port register of the PCIE switching chip can be configured by correctly processing various types of data packets according to the requirements of the PCIE protocol.

2) A physical PCIE switching chip is divided into a plurality of independent virtual switching areas, data packets can be freely forwarded between ports in the areas, the data packets can not be forwarded between the areas, and various data packets passing through the PCIE can also be forwarded at a line speed.

3) The function of the PCIE switchboard specified by the PCIE protocol is realized, the structure is simple, and the realization is easy.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a diagram of a prior art multi-host system;

fig. 2 is a logic diagram of an eight-port PCIE switch chip;

fig. 3 is a schematic structural diagram of a PCIE switch chip port configuration system supporting virtual switch according to the present invention;

fig. 4 is a schematic diagram of virtual switch partition supported by a PCIE switch chip according to the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

In the embodiment of the present invention, the partition function of the switch chip is also referred to as a virtual switch function, fig. 2 is a logic diagram of an eight-port PCIE switch chip, and as shown in fig. 2, one PCIE switch chip includes one upstream port and two or more downstream ports. Each port is logically a virtual PCI-PCI bridge, and all PCI-PCI bridges in the chip are connected through an internal virtual PCI bus. The Primary Bus (Primary Bus) side of the upstream port is connected to an external link, and the Secondary Bus (Secondary Bus) side is connected to a virtual PCI Bus inside the chip. The primary bus of the downstream port is connected to the virtual PCI bus and the secondary bus is connected to the external link.

The PCIE switch chip supporting virtual switching can be used as the standard PCIE switch chip shown in fig. 2, and can also be divided into several independent virtual switches for use through configuration, although each virtual switch shares the same physical switch, and each virtual switch is isolated from each other and does not communicate data flow.

Example 1

In the embodiment of the present invention, the PCIE switch chip is externally connected to an electrically Erasable Programmable Read-Only Memory (EEPROM for short), and the internal register of the switch chip is initialized and loaded through the externally connected EEPROM. The PCIE switching chip port configuration system supporting virtual switching is provided with n ports, wherein n is a natural number not less than three. The data packets received by the PCIE switch chip are divided into four types according to the difference of routing modes: routing packets based on Identification numbers (Identification, abbreviated as ID), Routing packets based on memory addresses, Routing packets based on Input/Output (IO) addresses, and Implicit Routing (Implicit Routing) packets. In addition, the configuration packet of the PCIE switch chip cannot come from the downstream port.

Each port of the PCIE switch chip has a fixed port number and a variable device number, and when one port is used as an upstream port, its device number is equal to 0, and when one port is used as a downstream port, its device number is equal to its port number. The invention discloses a PCIE switching chip port configuration system supporting virtual switching, which comprises: ports, routing modules, EEPROM interface controllers, Cross Bar switches (Cross bars) and configuration modules, wherein,

the port includes a physical layer interface and a port controller,

a Physical Layer interface, configured to implement functions of a Physical Media adaptation Layer (PMA for short) and a Physical Coding Sublayer (PCS for short) of the PCIE Physical Layer.

The port controller is used for realizing the functions of a Media Access Control (MAC) Layer of a physical Layer, a data link Layer and a transaction Layer, receiving a data packet, extracting a packet type and a routing information related field from the data packet header, and analyzing the data packet.

In the embodiment of the invention, when the port is used as the upstream port, the upstream port directly receives the type 0 configuration request packet, the configuration information of the upstream port register is extracted from the data packet, the port register is read or written for configuration according to the configuration information, and for other types of data packets, the upstream port sends the extracted packet type and the routing related field to the routing module.

When the port is used as a downstream port, the downstream port controller discards the type 0 and type 1 configuration request packets from the downstream link, and for the packets of other data types, the downstream port sends the extracted packet type and the routing information related field to the routing module.

And the routing module is used for receiving the packet type and routing related field information sent by the port controller, searching the route by utilizing the information to obtain the processing mode of the data packet, and simultaneously obtaining the receiving and output port numbers of the data packet.

And the EEPROM interface controller is used for reading the address and the configuration data of the register to be configured from an external EEPROM chip and sending the address and the configuration data to the configuration module.

And the configuration module is used for realizing the configuration of the internal port register of the chip and the division of virtual exchange, and the address and the configuration data of the register to be configured are sourced from a data packet received by the upstream port controller or the EEPROM interface controller.

And the crossbar switch is used for forwarding the data packet passing through the PCIE switching chip.

In the embodiment of the invention, the data packet forwarded by the crossbar comes from the port controller.

In the embodiment of the present invention, the routing related field information includes the type, destination ID, destination address of the packet header, and for the Message packet with implicit routing, the routing related field information further includes an eight-bit Message Code (Message Code) of the Message packet.

In order to divide the inside of a physical entity chip into several independent virtual areas, a virtual switch configuration register set is provided inside the chip, and in general, all the virtual switch configuration registers are located in the configuration space of a certain port, and all the virtual switch configuration registers of a port are located in the port controller.

In the embodiment of the invention, the virtual exchange configuration register group for realizing virtual exchange comprises three types of configuration registers: (1) the virtual switch comprises port indication registers, which ports are defined to be contained in each virtual switch, one virtual switch corresponds to one port indication register contained in each virtual switch, the number of bits of the port indication register contained in each virtual switch is not less than the number of ports of a chip, and each bit of the register corresponds to one port of the chip. When a bit of a port indication register is valid, the port corresponding to the bit belongs to the virtual switch specified by the port indication register contained in the virtual switch. When a bit of a port indication register contained in a virtual switch is invalid, the corresponding port does not belong to the virtual switch specified by the port indication register contained in the virtual switch, and one virtual switch at least contains one port; (2) virtual switch upstream port indication registers indicating the upstream port number of each virtual switch, a virtual switch having an upstream port indication register. (3) A virtual swap enable register defining a chip-enabled virtual swap. A virtual swap corresponds to an enable bit of the virtual swap enable register, which when valid enables the corresponding virtual swap, and which when invalid disables the corresponding virtual swap.

In the embodiment of the present invention, after the chip is powered on and before the PCIE system enumerates, the external EEPROM chip performs initialization configuration loading on all the port registers through the configuration module inside the PCIE switch chip. After loading is completed, the configuration module reads the information of the virtual switch configuration register from the relevant port controller to divide the virtual switch. And simultaneously, enabling the link of each enabled port by the configuration module, forbidding the link of the disabled port, starting the link training and initialization of each enabled port, and after the link of the upstream port is established, independently starting the enumeration of the virtual switch to which the host belongs by each virtual switch upstream host, wherein the enumeration of each virtual switch can be performed in parallel.

In the embodiment of the invention, during system enumeration, a primary Bus Number, a secondary Bus Number and a Subordinate Bus Number (Subordinate Bus Number) are distributed to each port, and after enumeration is completed, an operating system distributes an upstream port Base Address Register (Base Address Register), a pre-readable Memory Base Address Register (pre-readable Memory Base Register), a pre-readable Memory Base Address Register (pre-readable Base Register), a pre-readable Memory Base Address high-order 32-bit Register (pre-readable Base Upper 32bit Register), a Memory Base Address Register (Memory Base Register), an input and output Base Address Register (I/O Base Register), an input and output Base Address high-order 16-bit Register (I/O Base 16bit Register), a pre-readable Memory Limit Register (pre-readable Base Register), a pre-readable Memory Limit high-order 32-bit Register (pre-readable Base Register), and a pre-readable Memory Limit Register (Memory 32bit Register) for each virtual switch, The input/output Limit Register (I/O Limit Register) and the input/output high 16-bit Limit Register (I/O Limit Upper 16bits Register) respectively distribute system addresses, and system addresses are respectively distributed for a downstream port pre-readable memory base address Register, a pre-readable memory base address high 32-bit Register, a memory base address Register, an input/output base address high 16-bit Register, a pre-readable memory Limit high 32-bit Register, a memory Limit Register, an input/output Limit Register and an input/output high 16-bit Limit Register of each virtual switch. The routing module reads the values of the address registers and the values of the primary bus number register, the secondary bus number register, the subordinate bus number register and the command register of each port, and generates an IO address routing table, a memory address routing table, an ID routing table and an implicit routing table based on virtual switching for each port.

In an embodiment of the invention, each entry of the routing table is made up of a set of registers, each entry indicating whether a packet satisfying a certain condition is to be forwarded, received or dropped. The IO routing table is composed of a destination IO address range, a processing mode of the data packet and an output port number of the data packet. Each entry of the memory address routing table consists of a destination memory address range, a data packet processing mode and an output/receiving port number. Each entry of the ID routing table consists of a destination bus number range, a packet processing mode, and an output/receive port number, and the ID routing table indicates that a packet having a destination bus number equal to a primary bus number of each port is received and indicates a corresponding receive port number. The implicit routing table consists of packet type, message encoding, packet processing mode and output/receive port number. The routing table will limit each data packet to be transmitted in the virtual switch where the receiving port is located, and will not be transmitted to the ports outside the virtual switch where the receiving port is located.

In an embodiment of the invention, each port controller's packet has two sources, one from its own input link and one from the crossbar. Besides, the port controller also receives a register read-write operation instruction and write data from the configuration module. The register of each port is managed by the port controller, the port controller can write or read the configuration register, the upstream port can generate a corresponding completion packet according to the operation result and the requirement, and the downstream port controller can not generate the completion packet according to the read or write operation result of the configuration register, but can feed back the read or write operation result to the upstream port controller through the configuration module. The upstream port controller can also generate a completion packet for the read or write operation of the downstream port configuration register according to the downstream port configuration result fed back by the configuration module. The upstream port controller sends the generated completion packet to the physical layer interface through its output side and then to the output link through the physical layer interface.

In the embodiment of the present invention, the crossbar receives the data packet sent by the port controller and the output port number of the data packet, and sends the PCIE request packet to the corresponding output port controller according to the output port number. After receiving the data packet forwarded from the cross bar switch, the port controller either directly forwards the data packet without any processing according to the situation, or forwards the data packet after processing, and the forwarded data packet is forwarded to the physical layer interface through the output side of the port controller and then sent to the output link through the physical layer interface.

Example 2

Fig. 3 is a schematic structural diagram of a port configuration system of a PCIE switch chip supporting virtual switching according to the present invention, and an implementation mechanism of virtual switching is described below by taking an eight-port PCIE switch chip whose interior is configured to be capable of dividing four virtual switches at most as an example, as shown in fig. 3, the PCIE switch chip mainly includes a physical layer interface, a port controller, a routing module, an EEPROM interface controller, a configuration module, a crossbar switch, and the like. The PCIE switching chip is externally connected with an EEPROM chip used for initializing the port register.

The external EEPROM is used for storing the configuration register address and configuration data used for initializing the PCIE switching chip port register.

And the physical layer interface realizes the functions of a physical medium adaptation layer and a physical coding sublayer of the PCIE physical layer.

The port controller receives the data packet, extracts the packet type and the routing information related field from the data packet header, analyzes the data packet, and performs read or write operation on a port register contained in the data packet.

Each port of a PCIE switch chip has a fixed port number and a variable device number, and when a port is used as an upstream port, its device number is equal to 0, and when a port is used as a downstream port, its device number is equal to its port number.

When one port is used as an upstream port, the upstream port controller directly receives a type 0 configuration request packet, extracts configuration information of an upstream port configuration register from a data packet, performs read or write configuration on the configuration register according to the configuration information, and for other types of data packets, the upstream port sends the extracted packet type and relevant fields of routing information to a routing module.

When the port is used as a downstream port, the downstream port controller discards the type 0 and type 1 configuration request packets from the downstream link, and for the packets of other data types, the downstream port controller sends the extracted packet type and the routing information related field to the routing module. The routing module receives the packet type and routing related field information sent by the port controller, and utilizes the information to search the route to obtain the processing mode of the data packet and also obtain the receiving or output port of the data packet.

There are three ways to process the data packet, which are: forwarding, receiving and discarding. The routing module sends the searched result to the port controller which provides the searching request, if the port controller processes the received data packet in a forwarding mode, the data packet and the output port number of the data packet are sent to the cross switch, if the received data packet is the configuration request packet of the access port register, the configuration instruction of the port register is extracted from the data packet and sent to the configuration module, and for the power supply management message packet of which the port is the target receiving party, the port controller processes according to the requirement of the PCIE protocol.

And the EEPROM interface controller reads the address and the configuration data of the register to be configured from an external EEPROM chip and sends the address and the configuration data to the configuration module.

And the cross switch is used for forwarding the data packet passing through the PCIE switching chip, and the data packet forwarded by the cross switch module comes from the port controller.

When the chip is powered on, the address and configuration data of the register to be configured are read from an external EEPROM chip through the EEPROM interface controller module, the address and configuration data are sent to the configuration module, the registers of each port are initialized, loaded and configured, and the registers comprise virtual exchange configuration register groups which are: the virtual switch system comprises an n-bit virtual switch enabling register VSEnable, Port indication register groups VS0 Port-VSnPort contained in n virtual switches, and n virtual switch upstream Port indication register groups VS0 Uport-VSnUport, wherein n can be set to be a positive integer smaller than the actual Port number of a PCIE switch chip, and one PCIE switch chip can be configured into n independent virtual switches at most. Each bit of the virtual exchange enabling register VSEnable defines an enabling bit of virtual exchange, and when the position is 1, the corresponding virtual exchange is enabled and exists; at 0, the corresponding virtual swap is not enabled and does not exist. The bit number of the port indication register included in each virtual switch is the port number of the PCIE switch chip, and one virtual switch corresponds to one port indication register included in the virtual switch. One bit of the port indication register included in the virtual switch corresponds to a port of a PCIE switch chip, and the PCIE switch chip knows which ports each virtual switch is composed of through the port indication register included in each virtual switch. Each virtual switch upstream port indication register indicates an upstream port number for a virtual switch. A PCIE switch chip supporting at most n virtual switches must include an n-bit virtual switch enable register VSEnable, port indication registers included in the n virtual switches, and n upstream port indication registers. It should be noted that, for a chip supporting PCIE virtual switch, n is a positive integer, and once designed, the value of n is a fixed value and cannot be changed. In general, the virtual switch enable register, the virtual switch port indication register, and the virtual switch upstream port indication register are all located on a certain port with the number m, where m is 0 or a positive integer. All virtual swap registers are sticky registers, not affected by hot resets, and can only reset their values if cold reset.

In the embodiment of the present invention, the virtual switch enable register, the virtual switch port indication register, and the virtual switch upstream port indication register are all located at port 0. Port 0 contains a 4-bit valid virtual switch enable register defined as shown in table 1 below.

Table 1:

bit (C)	Name (R)	Read-write Properties
			0	VS0 Enable bit	Readable and writable
1	VS1 Enable bit	Readable and writable
			2	VS2 Enable bit	Readable and writable
3	VS3 Enable bit	Readable and writable
			7～4	Retention	Is not defined

The virtual switch containing 4 valid bits of 8 bits contains a port indication register, which is defined as shown in table 2 below.

Table 2:

there are 4 valid virtual switch upstream port indication registers of 3 bits, whose definition is shown in table 3 below.

Table 3:

bit (C)	Name (R)	Read-write Properties
			2～0	VS0 upstream port numbering	Readable and writable
7～3	Retention	Is not defined

As shown in fig. 4, which is a schematic diagram of virtual switch division supported by a PCIE switch chip, the eight-port switch chip in the diagram is divided into 3 independent virtual switches. In actual use, each virtual switch must have an upstream port, may have multiple downstream ports, or may not have a downstream port, and each virtual switch has its own dedicated reset, interrupt, and error handling mechanism, which do not interfere with each other. The upstream port of each virtual switch has access to each port register defined by the virtual switch to which it belongs.

If the eight-port PCIE switch chip in fig. 1 is divided into 3 virtual switches as shown in fig. 4, the virtual switch enable register of port 0, the 4 virtual switch port indication registers, and the 4 virtual switch upstream port indication registers must be configured with the following binary values respectively:

VSEnable[7:0]＝00000111,

VS0Port[7:0]＝00001001,VS1Port[7:0]＝00110010,

VS2Port[7:0]＝11000100,VS3Port[7:0]＝00000000,

VS0Uport[7:0]＝00000000,VS1Uport[7:0]＝00000001,

VS2Uport[7:0]＝000000010,VS3Uport[7:0]＝000000000。

since there are only 3 virtual switches in fig. 4 and virtual switch VS3 does not exist, VSEnable [7:0] is set to 00000111, leaving VS3 disabled. Since there are only 3 virtual swaps, the values of the VS3Port and VS3Uport registers are meaningless, which we make to all 0's.

After the EEPROM loads the port registers, the configuration module reads the virtual switch configuration registers, divides the chip into 3 virtual switches, and enables the link of each port, so that the link of each port can start to enter link training and initialization. When the upstream port link of a virtual switch is established, the virtual switch can enumerate. Each virtual switch is enumerated by its upstream host, the enumeration process follows the regulation of PCIE protocol, and the enumeration instruction is only transmitted in the port to which each virtual switch belongs. The enumeration of the virtual exchanges may be performed simultaneously, with their enumeration processes not interfering with each other.

In the enumeration process, when an upstream port controller receives a type 0 configuration request packet, if the device number of the configuration request is equal to 0, it indicates that the destination port number of the configuration request is the port, the upstream port controller reads or writes a port configuration register corresponding to the upstream port according to the type 0 configuration request, and if the device number of the type 0 configuration request is not equal to 0, the upstream port controller discards the configuration packet. The upstream port controller also judges whether the addressed port register exists according to the 4-bit extended register number and the 6-bit register number extracted from the data packet, if so, the addressed port register is read or written according to the type of the configuration packet, and if not, the configuration request is discarded. The upstream port controller will feed back a completion packet for each type 0 configuration request and send it to the physical layer interface of the upstream port, through which it is sent to the upstream output link.

As shown in fig. 4, the enumeration instruction received by port 0 from the upstream direction is transmitted only to the PCI-PCI bridge (abbreviated as P2P bridge) of VS0 where the downstream port 3 is located and the downstream devices external to port 3, and is not transmitted to any of VS1 and VS 2. Enumeration instructions received by port 1 from the upstream direction are only transmitted to the P2P bridge of downstream port 4, the P2P bridge of downstream port 5, downstream devices external to downstream port 4 or downstream port 5 of VS1, and not to all ports within VS0 and VS 2. Similarly, enumeration commands received by port 2 from the upstream direction are only transmitted to the P2P bridge of downstream port 6, the P2P bridge of downstream port 7, downstream port 6 or downstream devices external to downstream port 7 of VS2, and not to any of VS0 and VS 1.

When the system is enumerated, a primary bus number, a secondary bus number and a subordinate bus number are distributed to each port, after the enumeration is completed, the operating system distributes system addresses to an upstream port base address register, a pre-readable memory base address high 32-bit register, a memory base address register, an input/output base address high 16-bit register, a pre-readable memory limit high 32-bit register, a memory limit register, an input/output limit register and an input/output high 16-bit limit register of each virtual switch, and distributes system addresses to a downstream port pre-readable memory base address register, a pre-readable memory base address high 32-bit register, a memory base address register, an input/output base address high 16-bit register of each virtual switch, The pre-readable memory limit register, the pre-readable memory limit high 32-bit register, the memory limit register, the input output limit register and the input output high 16-bit limit register are respectively allocated with system addresses. The routing module reads the values of these address registers and the primary, secondary, subordinate and command registers of each port, and generates a virtual switch-based IO address routing table, memory address routing table, ID routing table and implicit routing table for each port, as shown in tables 4, 5, 6 and 7 below.

Table 4:

destination address range	Treatment method	Output port number
			IO Address Range A	Forwarding	Port A
IO Address Range B	Forwarding	Port B
			IO Address Range C	Forwarding	Port C
Others	Discard the

Table 5:

destination address range	Treatment method	Output/receive port number
			Memory address range A1	Forwarding	Port A
Memory address range A2	Receiving	Port A
			Memory address range B1	Forwarding	Port B
Memory address range B2	Receiving	Port B
			Memory address range C1	Forwarding	Port C
Memory address range C2	Receiving	Port C
			Others	Discard of

Table 6:

destination bus number range	Treatment method	Output/receive port number
			Bus range A1	Forwarding	Port A
Bus number equal to A	Receiving	Port A
			Bus range B1	Forwarding	Port B
Total number equal to B	Receiving	Port B
			Bus range C1	Forwarding	Port C
Bus number equal to C	Receiving	Port C
			Others	Discard the	Output/receive port number

Table 7:

there are three ways for each input port to process packets, which are: forwarding, receiving and discarding. Each entry of the routing table is made up of a set of registers, each entry indicating whether to forward, receive, or discard a packet that satisfies a condition. Each entry of the IO routing table is composed of a destination IO address range, a packet processing mode, and an output port number of the packet. Each entry of the memory address routing table consists of a destination address range, a data packet processing mode and an output/receiving port number. In addition, the ID routing table can indicate that the processing mode of the data packet with the target bus number equal to the primary bus number of each port is receiving and indicate the corresponding receiving port number. The implicit Routing table is composed of a message Routing type Subfield (Routing Subfield), message encoding, a packet processing method, and an output/reception port number.

As shown in fig. 4, when the upstream port 1 controller of VS1 receives a transaction layer packet, it will extract the packet header of the packet and analyze the packet header, and if the received type 0 configuration request is received, the upstream port 1 controller receives the configuration request, performs a read or write operation on the corresponding port register, and returns a completion packet according to the specific situation of the read or write request.

If the upstream port 1 controller of VS1 receives the type 1 configuration request, extract the type field and the destination ID number from the packet header, and send them to the routing module, which performs routing lookup and determines, according to the result of the lookup, whether to send the packet to the crossbar switch or send the configuration read-write command extracted from the packet to the configuration module. When sending a data packet to the crossbar switch, the output port number of the data packet must also be sent to the crossbar switch, and the crossbar switch sends the data packet to the corresponding output port according to the data packet and the output port number of the data packet.

If the upstream port 1 of the VS1 receives a memory request packet, the type field and the destination address extracted from the packet header of the data packet are sent to the routing module, the routing module performs routing lookup, and obtains an output port number or a receiving port number according to the lookup result, and determines whether the data packet is sent to the crossbar switch or a read/write instruction for accessing the port or the downstream port is extracted from the data packet. When sending a data packet to the crossbar switch, the output port number of the data packet must also be sent to the crossbar switch, and the crossbar switch sends the data packet to the corresponding output port according to the data packet and the output port number of the data packet. If the command is a read/write command for accessing the port, the upstream port controller completes the subsequent operation according to the read/write command, generates a corresponding completion packet according to the operation result, and sends the completion packet to the upstream port link. If the read-write instruction is a read-write instruction for accessing a downstream port, the extracted read-write instruction is sent to a configuration module and is transmitted to a downstream port controller by the configuration module, the downstream port controller performs read-write operation on a port register according to the instruction, the downstream port controller feeds back a read/write result to the upstream port through the configuration module, and the upstream port controller generates a corresponding completion packet and sends the completion packet to an upstream port link.

If an upstream port 1 of VS1 receives an IO request packet, the type field and the destination address extracted from the packet header of the data packet are sent to the routing module, the routing module knows that an IO routing table should be searched according to the type field of the data packet, and obtains the processing mode and the output port number of the data packet according to the routing search, the upstream port 1 controller sends the data packet and the output port number of the data packet to the crossbar switch, and the crossbar switch sends the data packet to the corresponding output port according to the output port number of the data packet and the data packet.

If the upstream port 1 of VS1 receives the message request packet, the type field extracted from the packet header of the data packet, the eight-bit message of the message packet are coded and sent to the routing module, the routing module knows that an implicit routing table should be searched according to the type field of the data packet, the processing mode, the output port number or the receiving port number of the data packet is obtained according to the routing table search, if the data packet is received by the upstream port of VS1, the data packet is processed by the upstream port 1 controller, if the data packet is output, the data packet is sent to the corresponding output port controller through the cross switch, and the data packet is forwarded after being processed by the output port controller or is directly forwarded without being processed.

The downstream port 4 or 5 of VS1 receives packets in the same manner as the upstream packet, except that the downstream port does not receive a type 0 or type 1 configuration request packet, and if so, should discard it. In addition, when the downstream port 4 or 5 receives the memory request packet, the type field and the destination address of the extracted packet are sent to the routing module, and the routing module performs routing lookup to obtain a processing mode of the data packet, wherein the processing mode is to forward the data packet through a certain port or discard the data packet, and the data packet cannot be received.

After receiving the data packet forwarded from the cross bar switch, the port controller either directly forwards the data packet without any processing according to the situation, or forwards the data packet after processing, and the forwarded data packet is forwarded to the physical layer interface through the output side of the port controller and then sent to the output link through the physical layer interface. For example, the upstream port controller may receive four types of virtual INT interrupt message packets INTA, INTB, INTC, and INTD from each downstream port forwarded by the crossbar, aggregate the same type of virtual INT interrupt message packets, generate one message packet, and forward the message packet.

It should be noted that, the PCIE switch chip of this patent is implemented, and the same can be used for a scene that does not need to support virtual switching, at this time, only the port of the entire PCIE switch chip needs to be configured in one virtual switching, and during operation, the user cannot feel the existence of virtual switching.

The invention provides a PCIE (peripheral component interface express) exchange chip port configuration system and a method supporting virtual exchange, which support the initialization loading of a port register through an external EEPROM (electrically erasable programmable read-only memory) memory chip, divide a physical entity PCIE exchange chip into a plurality of virtual exchange areas according to loaded configuration data after the loading is finished, and freely forward data packets between ports in the virtual exchange areas but not communicate data streams between the virtual exchange areas. The configuration mechanism can rapidly realize the port configuration of the PCIE switching chip and meet the time limit requirement of the PCIE protocol on the initialization of the PCIE switching chip.

Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A PCIE switching chip port configuration system supporting virtual switching comprises at least three ports, a routing module, an EEPROM interface controller, a configuration module and a cross switch,

the port comprises a port controller and a physical layer interface;

the physical layer interface realizes the functions of a physical media adaptation layer and a physical coding sublayer of the PCIE physical layer; transmitting a data packet which is transmitted by an external device to a PCIE switching chip to a port controller; forwarding the data packet sent by the port controller to an external device;

the crossbar is used for forwarding the data packet passing through the PCIE switching chip;

when the port is configured as an upstream port, the upstream port is configured to receive a type 0 configuration request packet, extract configuration information of the upstream port, perform port configuration according to the configuration information, extract a type and routing information of a non-type 0 configuration request packet, and send the type and routing information to the routing module;

2. The PCIE switch chip port configuration system supporting virtual switching according to claim 1, wherein the port includes a fixed port number and a variable device number, when the port is configured as an upstream port, the upstream port device number is set to 0, and when the port is configured as a downstream port, the downstream port device number is the fixed port number.

3. The PCIE switching chip port configuration system supporting virtual switching of claim 1 wherein the port controller,

receiving the configuration information of the configuration module, performing read or write operation on a port register according to the configuration information, wherein an upstream port controller can directly generate a configuration completion data packet according to an operation result of a local port register, a downstream port controller cannot directly generate the configuration completion data packet according to the read or write operation result of the local port register by the configuration module, but can feed back the operation result to the configuration module, the configuration module sends the configuration completion data packet to the upstream port controller, and the upstream port controller generates the configuration completion data packet of the downstream port register; the upstream port controller sends the generated configuration completion data packet to the physical layer interface through an output side, and the configuration completion data packet is sent to an output link through the physical layer interface;

4. The PCIE switching chip port configuration system supporting virtual switching of claim 1, further comprising a virtual switching configuration register set composed of a port indication register included in the virtual switching, a virtual switching upstream port indication register, and a virtual switching enable register, wherein,

5. The PCIE switching chip port configuration system supporting virtual switching of claim 1, wherein the routing information includes a type, a destination ID, a destination address of the data packet header, and for an implicit routing message packet, an octet message encoding of the implicit routing message packet.

6. The PCIE switching chip port configuration system supporting virtual switching of claim 1, wherein the routing module further comprises a reading unit and a generating unit,

7. The PCIE switching chip port configuration system supporting virtual switching of claim 6,

each entry of the routing table comprises a set of registers, and each entry represents forwarding/receiving/discarding of the data packet meeting the conditions listed by the entry;

8. The PCIE switching chip port configuration system supporting virtual switching of claim 6,

each entry of the IO address routing table comprises a destination IO address range, a processing mode of the data packet and an output port number of the data packet;

9. The system according to claim 1, wherein the routing module is further configured to feed back a route search result to the port controller.

10. The system according to claim 1, wherein the crossbar switch is further configured to receive a packet and an output port number of the packet, and send the packet to a corresponding output port controller according to the output port number.

11. A PCIE switching chip port configuration method supporting virtual switching is characterized by comprising the following steps:

1) the external EEPROM chip performs initialization configuration on all port registers through a configuration module;

5) the port controller receives and analyzes a data packet, obtains a processing mode of the data packet and a receiving and output port of the data packet according to the type and the routing information of the data packet, and performs read and/or write operation on a port;

said step 5) further comprises the step of,

when the upstream port controller receives a transaction layer data packet, extracting a packet header of the data packet and analyzing the packet header;

if the type 0 configuration request packet is received, the upstream port controller receives the configuration request packet, performs read or write operation on a corresponding port register, and returns a completion packet according to the specific situation of the read or write request;

if a type 1 configuration request packet is received, the upstream port controller extracts a type field and a destination ID number from a data packet header and sends the type field and the destination ID number to a routing module; the routing module searches for a route, and determines whether to send a data packet to the cross switch or extract a configuration read-write instruction from the data packet and send the configuration read-write instruction to the configuration module according to a searching result; when sending a data packet to the crossbar switch, the output port number of the data packet must also be sent to the crossbar switch, and the crossbar switch sends the data packet to the corresponding output port according to the data packet and the output port number of the data packet.

12. The method of claim 11, wherein the step 3) of performing system address allocation comprises,

allocating system addresses for a base address register, a pre-readable memory base address high 32-bit register, a memory base address register, an input and output base address high 16-bit register, a pre-readable memory limit high 32-bit register, a memory limit register, an input and output limit register and an input and output high 16-bit limit register of an upstream port of each virtual switching region;

allocating system addresses to a pre-readable memory base register, a pre-readable memory base upper 32-bit register, a memory base register, an input output base upper 16-bit register, a pre-readable memory limit upper 32-bit register, a memory limit register, an input output limit register, and an input output upper 16-bit limit register of a downstream port of each virtual switch area.

13. The method of claim 11, wherein the port configuration of the PCIE switching chip supporting virtual switching,

each entry of the IO routing table includes: a destination IO address range, a processing mode of the data packet and an output port number of the data packet;

14. The method of claim 11, wherein the step 5) further comprises,

if the command is a read/write command for accessing the port, the upstream port controller completes subsequent operations according to the read/write command, generates a corresponding completion packet according to the operation result and the requirement, and sends the completion packet to an upstream port output link; if the read-write command is a read-write command for accessing the downstream port, the extracted read-write command is sent to the configuration module and is transmitted to the downstream port controller by the configuration module, and the downstream port controller performs read-write operation on the port register according to the read-write command; the downstream port controller feeds back the read/write result to the upstream port controller through the configuration module, and the upstream port controller generates a corresponding completion packet according to needs and sends the completion packet to an upstream port output link.

15. The method of claim 11, wherein the step 5) further comprises,

16. The method of claim 11, wherein the step 5) further comprises,

if the upstream port controller receives a message request packet, extracting a type field and an eight-bit message code of the message packet from a data packet header, and if the data contains a destination ID and also needs to extract a destination ID number, sending the data to a routing module; the routing module knows that an implicit routing table needs to be searched according to the type field of the data packet, and searches a processing mode, an output port number or a receiving port number of the data packet according to the routing table; if the receiving is the upstream port receiving, the upstream port controller processes the receiving; if the output is the output, the output is sent to the corresponding output port controller through the cross bar switch, and the output port controller forwards the output signal after processing or directly forwards the output signal without processing.

17. The method of claim 11, wherein the step 5) further comprises,

when the downstream port controller receives the request packet, extracting the type field and the destination address of the packet and sending the type field and the destination address to the routing module; the routing module carries out routing search, forwards or discards the data packet according to the search result, and instructs the downstream port controller to discard the memory request packet from the downstream link for accessing the port register of the PCIE chip;