CN114265805A - PCIe switching chip upstream and downstream port routing table construction method and system - Google Patents
PCIe switching chip upstream and downstream port routing table construction method and system Download PDFInfo
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Abstract
The invention provides a PCIe switching chip upstream and downstream port routing table constructing method, which is used for constructing upstream and downstream port routing tables, and comprises the following steps: the following steps are repeatedly executed at the upstream port until the construction of the routing table entry from the upstream port to all the downstream ports is completed: s1, the upstream port captures the configuration packet related to the downstream port route issued by the operating system connected with the upstream port; s2, analyzing the information related to the route in the configuration packet and constructing an upstream port routing table item according to the analyzed route related information; the following steps are repeatedly executed on the downstream port until the construction of the routing table entry from the downstream port to other downstream ports is completed: p1, the downstream port receives the configuration packet which is captured by the upstream port and is sent by the operating system connected with the upstream port and related to the downstream port route; and P2, analyzing the information related to the route in the configuration packet and constructing a downstream port routing table entry according to the analyzed route related information.
Description
Technical Field
The invention relates to the technical field of communication, in particular to data communication supporting a PCIe protocol, and more particularly to a method and a system for constructing routing tables of upstream and downstream ports of a PCIe switching chip supporting the PCIe protocol.
Background
With the development and progress of science and technology, internet services become more abundant and diversified, and the service requirements are continuously increasing, for example, applications such as big data, artificial intelligence, image calculation and the like, and the requirements of the applications on I/O devices such as storage devices and intelligent accelerator cards are continuously increasing, wherein the demand on the storage devices is increased at a very high speed due to the explosive increase of data, and more special accelerator cards are required for accelerating model training in the fields such as artificial intelligence. Storage devices (NVMe SSD and the like), acceleration cards (NVIDIA GPU, Membrian smart acceleration cards and the like) all support a universal I/O interconnection protocol, namely a PCIe protocol, but PCIe expansion slots of a host mainboard are limited, so that the expandability of the devices is limited, and the performance of applications is influenced. Therefore, there is a need for expansion through PCIe switch chips.
PCIe switch chips typically have an upstream port that is a port pointing in the direction of the root complex and a plurality of downstream ports that are ports away from the root complex. The PCIe switch chip has a main function of correctly sending a packet from a source port to a destination port, and when the function is completed, a routing table needs to be searched according to a destination address in the packet, so as to obtain the destination port. When the host system is reset or powered on, enumeration operation is carried out, system software firstly scans the PCIe bus to enumerate and discover all devices connected under the bus, then sends a read configuration packet, judges the type of the PCIe device according to the returned content and then sends a write configuration packet and initializes a register in the device. In the enumeration process, system software traverses all combinations of Bus number Bus (0-255), Device number Device (0-31) and Function number Function (0-7), tries to read a Vendor ID register of each Bus, Device and Function combination, indicates that the Device does not exist when the read Vendor ID is 0xFFFF, initializes the Device register when the Device exists, however, after the Device is powered on and started, the initial state of a routing table of the switching chip is empty, and if the Device is not configured with the correct routing table, the switching chip cannot correctly search a destination port after receiving a data packet. In the traditional method, a routing table is not constructed, after a CPU sends out a data packet in data transmission from an upstream port to a target downstream port, the upstream port broadcasts the data packet to all the downstream ports, after the data packet reaches the downstream ports, each downstream port independently judges whether the destination address of the data packet belongs to the address space range of the subordinate device of the port, if not, the data packet is discarded, and if so, the data packet is sent to the connected subordinate devices; in addition, when a data packet which is received by the downstream port and sent by the device connected with the downstream port and accesses the devices under other downstream ports is received, the downstream port is required to broadcast the data packet to all other downstream ports, and after the data packet reaches the downstream port, each downstream port independently judges whether the packet is a data packet sent to the downstream port, so that each downstream port also needs to judge and process the data packet, the time delay of the whole process is greatly increased, the bandwidth of a switching network is wasted, and the throughput of the whole PCIe switching chip is influenced.
Overall, the main drawbacks of the conventional methods are:
1. the upstream port broadcasts the data packet to all the downstream ports, which increases the data flow of the interconnection network among the ports, wastes the bandwidth of the switching network and affects the throughput of the whole PCIe switching chip.
2. The number of data packets to be processed by the downstream port is increased, and when the data volume is large, the data packets need to be queued and wait for sequential processing at the port, so that the delay of the data packets which should be forwarded by the port is caused.
Disclosure of Invention
Therefore, an object of the present invention is to overcome the drawbacks of the conventional methods and provide a method and a system for constructing routing tables of upstream and downstream ports of a PCIe switch chip.
According to a first aspect of the present invention, there is provided a PCIe switch chip upstream port routing table building method, including: s1, the upstream port captures the configuration packet related to the downstream port route issued by the operating system connected with the upstream port; s2, analyzing the information related to the route in the configuration packet and constructing an upstream port routing table entry according to the analyzed information related to the route, wherein the upstream port routing table entry at least comprises downstream port equipment number information and routing information corresponding to each downstream port equipment number.
In some embodiments of the present invention, the upstream port routing table entry is: an address routing entry, and/or an ID routing entry, and/or an implicit routing entry, and/or a multicast entry.
Preferably, the address routing table entry is: IO address space routing table entries, and/or prefetcheable memory address space routing table entries, and/or non-prefetched memory address space routing table entries;
wherein, the IO address space routing table entry at least includes: a downstream port device number and an IO address space range corresponding to the downstream port device number;
the prefetch memory address space routing table entry at least comprises: a downstream port device number and a prefetcheable memory address space range corresponding to the downstream port device number;
the non-prefetch memory address space routing table entry at least comprises: a downstream port device number and a non-prefetched memory address space range corresponding to the downstream port device number;
the ID routing table entry includes at least: a downstream port device number and a BUS number range corresponding to the downstream port device number.
According to a second aspect of the present invention, there is provided a PCIe switch chip based data forwarding method, where an upstream port includes an upstream port routing table configured according to the method of the first aspect of the present invention, the method includes: t1, the upstream port receives the data packet from the operating system connected with it; t2, based on the destination information in the data packet received in step T1, looking up the destination downstream port corresponding to the destination information of the data packet in the upstream port routing table; t3, forwarding the data packet to the destination downstream port obtained in the step T2.
According to a third aspect of the present invention, there is provided a PCIe switch chip upstream port routing table system, the system comprising: the upstream port configuration packet analysis module is used for capturing a configuration packet related to the configuration of the downstream port route, analyzing the configuration packet to extract information related to the configuration of the downstream port route and sending the information to the upstream port route table construction module; an upstream port routing table constructing module, configured to receive the information extracted by the upstream port configuration packet parsing module and construct an upstream port routing table entry, where the upstream port routing table entry at least includes downstream port device number information and routing information corresponding to each downstream port device number; the upstream port routing table storage module is used for storing the upstream port routing table constructed by the upstream port routing table construction module; and the upstream port route searching module is used for searching a destination downstream port corresponding to the destination information of the data packet in the upstream port route table according to the route information in the data packet received by the upstream port and sent by the operating system and routing the data packet.
According to a fourth aspect of the present invention, there is provided a PCIe switch chip downstream port routing table building method, including: p1, the downstream port receives the configuration packet which is captured by the upstream port and is sent by the operating system connected with the upstream port and related to the downstream port route; and P2, analyzing the information related to the route in the configuration packet and constructing a downstream port routing table entry according to the analyzed route related information, wherein the downstream port routing table entry at least includes downstream port device number information and routing information corresponding to each downstream port device number.
In some embodiments of the present invention, the downstream port routing table entry is: an address routing entry, and/or an ID routing entry, and/or an implicit routing entry, and/or a multicast entry.
Preferably, the address routing table entry is: IO address space routing table entries, and/or prefetcheable memory address space routing table entries, and/or non-prefetched memory address space routing table entries; wherein, the IO address space routing table entry at least includes: a downstream port device number and an IO address space range corresponding to the downstream port device number; the prefetch memory address space routing table entry at least comprises: a downstream port device number and a prefetcheable memory address space range corresponding to the downstream port device number; the non-prefetch memory address space routing table entry at least comprises: a downstream port device number and a non-prefetched memory address space range corresponding to the downstream port device number; the ID routing table entry includes at least: a downstream port device number and a BUS number range corresponding to the downstream port device number.
According to a fifth aspect of the present invention, there is provided a PCIe switch chip based data forwarding method, where a downstream port includes a downstream port routing table configured according to the method according to the fourth aspect of the present invention, the method includes: r1, the downstream port receives the data packet sent by the device connected with the downstream port; r2, based on the destination information in the data packet received in the step R1, searching a destination downstream port corresponding to the destination information of the data packet in a downstream port routing table; and R3, forwarding the data packet to the destination downstream port obtained in the step R2.
According to a sixth aspect of the present invention, there is provided a PCIe switch chip downstream port routing table system, the system comprising: the downstream port configuration packet analysis module is used for receiving and analyzing the configuration packet forwarded by the upstream port, extracting information related to the configuration of the downstream port route in the configuration packet, and sending the information to the downstream port route table construction module; a downstream port routing table constructing module, configured to receive the information extracted by the downstream port configuration packet parsing module and construct a downstream port routing table entry, where the downstream port routing table entry at least includes information of a downstream port device number and routing information corresponding to each downstream port device number; the downstream port routing table storage module is used for storing the downstream port routing table constructed by the downstream port routing table construction module; and the downstream port route searching module is used for searching a destination downstream port corresponding to the destination information of the data packet in a downstream port route table according to the route information in the data packet received by the downstream port and sent by the equipment connected with the downstream port and routing the destination downstream port.
According to a seventh aspect of the present invention, there is provided a PCIe switch chip, where the chip includes an upstream port and a plurality of downstream ports, and the upstream port stores an upstream port routing table constructed by the method according to the first aspect of the present invention; the downstream port stores a downstream port routing table constructed by the method according to the fourth aspect of the present invention.
According to an eighth aspect of the present invention, there is provided a PCIe switching system, the system including an upstream port and a plurality of downstream ports, the upstream port being configured with the upstream port routing table system according to the third aspect of the present invention; each downstream port is configured with a downstream port routing table system according to the sixth aspect of the invention.
In some embodiments of the invention, the upstream port routing table system further comprises: the upstream port configuration packet broadcasting module is used for broadcasting the configuration packet which is captured by the upstream port and is related to the configuration of the downstream port route to all the downstream ports.
Compared with the prior art, the invention has the advantages that:
1. the method for constructing the routing table by the PCIe exchange chip can actively analyze data packets passing through the exchange chip and construct the routing table in real time, and can realize point-to-point direct communication from an operating system connected with a PCIe upstream port to equipment connected with a downstream destination port and end-to-end communication between different equipment connected with the PCIe downstream port by constructing the routing table.
2. And a special processor (such as ARM, MCU, DSP and the like) is not needed to configure the routing table, so that resources are saved.
3. The method for constructing the routing table simultaneously comprising the upstream port and the downstream port can construct the routing table in real time without transmitting the data packet to all the downstream ports in a broadcasting mode, is more direct and efficient, fully utilizes the performance of a switching network in a switch, improves the throughout of the whole PCIe switching chip, reduces the processing of port data packets and reduces the processing delay of the data packets.
Drawings
Embodiments of the invention are further described below with reference to the accompanying drawings, in which:
fig. 1 is a schematic flowchart of a PCIe switch chip upstream port routing table constructing method according to an embodiment of the present invention;
FIG. 2 is a flow chart illustrating a method for transmitting data of an upstream port of a PCIe switch chip according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a PCIe switching chip upstream port routing table system according to an embodiment of the present invention;
FIG. 4 is a flow chart of a method for constructing a routing table of a downstream port of a PCIe switch chip according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating a method for transmitting data of a downstream port of a PCIe switch chip according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a downstream port routing table system of a PCIe switch chip according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a PCIe switching system architecture in accordance with an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail by the following specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
For a better understanding of the present invention, reference is made to the following detailed description taken in conjunction with the accompanying drawings. Since the PCIe protocol is a known technology, the present invention does not repeat the specific english representation, protocol itself and communication process related to the PCIe protocol itself, and only explains the method for constructing the routing table.
As mentioned in the background art, in the conventional PCIe-based data transmission method, a routing table is not constructed for data forwarding from an upstream port to a downstream port, so that the upstream port needs to broadcast a data packet to all downstream ports after receiving the data packet, each downstream port separately determines whether the packet is a data packet addressed to itself after the data packet arrives at the downstream port, similarly, when a data packet which is sent by a device connected to the downstream port and accesses devices under other downstream ports and is received by the downstream port, the downstream port needs to broadcast the data packet to all other downstream ports, and when the data packet arrives at the downstream port, each downstream port separately determines whether the packet is a data packet addressed to itself, so that each downstream port needs to determine and process the data packet, thereby greatly increasing the delay of the whole process and wasting the bandwidth of a switching network, affecting the throughput of the entire PCIe switch chip.
As described above, because the packet forwarding from the upstream port to the downstream port in the conventional method adopts a broadcast manner, which increases the time consumption of the whole data transmission process and wastes the bandwidth of the switching network, the inventor designs a method for constructing a routing table of the upstream port of the PCIe switching chip, constructs a routing table entry from the upstream port to each downstream port, and can implement point-to-point communication from the operating system connected to the PCIe upstream port to the device connected to the PCIe downstream port based on the constructed routing table entry of the upstream port.
According to an embodiment of the present invention, the present invention provides a PCIe switch chip upstream port routing table building method, configured to build a routing table from an upstream port to a downstream port, as shown in fig. 1, the method includes repeatedly performing steps S1 and S2 until the building of routing table entries from the upstream port to all downstream ports is completed, where each step is described in detail below.
In step S1, the upstream port captures a configuration packet associated with the downstream port route issued by the operating system connected to the upstream port. The routing related information refers to routing information that can indicate a path from an upstream port to a downstream port directly, where the routing information may be routing information such as an address routing table, an ID routing table, an implicit routing table, a multicast table, and the like.
Each port in the PCIe switch chip has a configuration space based on the characteristics of the PCIe protocol itself, where the protocol specifies that the configuration space fields associated with ID routing and address routing have a number range in registers of 18h-30 h. Table 1 shows the address routing related register specific contents and the ID routing related register specific contents based on the PCIe protocol.
TABLE 1
The configuration space is configured when the host operating system is powered on for enumeration, table 2 shows a read-write configuration packet format based on the PCIe protocol, and since the read-write configuration format is specified by the PCIe protocol, the present invention does not describe the meaning of each field, but only describes the fields related to the route, where the specific content of the configuration packet captured by the upstream port is: the Fmt field is 0b010, the Type field is 0b00100 or 0b00101, and the packet Type is a configuration write packet; the EP field is 0, which represents Payload of the configuration packet as valid data; the Bus Number field is the Bus Number of the upstream port plus one, wherein the Bus Number of the downstream port is the Bus Number of the upstream port plus 1, and the Bus Number of the upstream port can be obtained from the configuration space of the upstream port; the Device Number field does not exceed the Number of downstream ports of the PCIe switching chip; the Function Number field does not exceed the Number of functions realized by the downstream port of the switch chip (generally, only physical functions are realized, and the Function Number is 0); the value of the Rgist Number field is in the range of 18h-30 h; the extracted routing information includes: register Number, Payload, First DW BE (each bit of the First DW BE field corresponds to a byte enable bit of the First doubleword of the data Payload), Device Number.
TABLE 2
As can be seen from table 1, the register configuration space of each port includes ID routing information (indicated by a BUS number) and address routing information, and as can be seen from table 2, each port, particularly a downstream port, is configured with a port device number, and then the port device number corresponds to the downstream port, and as can be seen from the combination of table 1 and table 2, the downstream port device number corresponding to the corresponding downstream port can be directly obtained by obtaining the ID number or address space range of the downstream port, so that an ID routing table entry can be constructed according to the ID number information in the configuration packet or an address routing table entry can be constructed according to the address space range, and point-to-point communication from the upstream port to the downstream port can be realized through the routing table entry.
In step S2, the information related to the route in the configuration packet is parsed, and an upstream port routing table entry is constructed according to the parsed information related to the route, where the upstream port routing table entry at least includes information of a downstream port device number and routing information corresponding to each downstream port device number.
According to an embodiment of the present invention, the upstream port routing table entry is: address routing table entries, and/or ID routing table entries, and/or implicit routing table entries, and/or multicast table entries, which are set up in the upstream port routing table as an example, are described below.
As can be seen from Table 1 above, the address space ranges may include IO address space ranges, prefetcheable memory address space ranges, and non-prefetched memory address space ranges.
Thus, the address routing table entry may be constructed as: IO address space routing table entries, and/or prefetcheable memory address space routing table entries, and/or non-prefetched memory address space routing table entries; wherein, the IO address space routing table entry at least includes: a downstream port device number and an IO address space range corresponding to the downstream port device number; the prefetch memory address space routing table entry at least comprises: a downstream port device number and a prefetcheable memory address space range corresponding to the downstream port device number; the non-prefetch memory address space routing table entry at least comprises: a downstream port device number and a non-prefetched memory address space range corresponding to the downstream port device number.
Specifically, the index of the IO address space routing table entry is a downstream port device number, and an IO address space range corresponding to each downstream port device number, where the IO address space range: the length of the I/O Limit/Base is 8bits, wherein when the I/O Limit/Base [3:0] is 1, the I/O Limit Upper16bits and the I/O Base Upper16bits are supported, the length of an IO address is 32bits, and the address space is as follows: { I/O Base Upper16bits, I/O Base [7:4],000H } - { I/O Limit Upper16bits, I/O Limit [7:4], FFFH }; if the I/O Limit/Base [3:0] is 0, the I/O Limit Upper16bits and the I/O Base Upper16bits are not supported, the address length is 16bits, and the IO address space is as follows: { I/O Base [7:4],000H } - { I/O Limit [7:4], FFFH }; the rest values of I/O Limit/Base [3:0] are reserved, and a routing table composed of constructed IO address space routing table entries is shown in table 3, so that it can be seen that in each table entry, one downstream port device number corresponds to one IO address space range, and the corresponding destination port device number can be found by matching the IO address space range in the data packet.
TABLE 3
The index of the prefetcheable address space routing table entry is a downstream port device number, and a prefetcheable address space range corresponding to each downstream port device number, wherein the prefetcheable memory address space range is as follows: the length of the prettchable Memory Limit/Base is 16bits, wherein the length of the prettchable Memory Limit/Base [3:0] represents 64bits when the prettchable Memory Limit/Base [1 ], the length of the prettchable Memory Base [31:0], the prettchable Memory Base [15:4], the 00000H ], the Upper prettchable Memory Base [31:0] prettchable Memory Base [15:4], the FFFFFH }; when the address space is 0, the length of the address capable of being prefetched is 32bits, and the address space is as follows: { prefectchable Memory Base [15:4], 00000H-prefectchable Memory Base [15:4], FFFFFH }, where a routing table composed of constructed routing table entries of the prefetcheable address space is shown in Table 4, and it can be seen that in each table entry, a downstream port device number corresponds to a range of the prefetcheable address space, and the corresponding destination port device number can be found by matching the range of the prefetcheable address space in the data packet.
TABLE 4
The index of the non-prefetch address routing table entry is the downstream port device number, the non-prefetch address space range corresponding to each downstream port device number, wherein the non-prefetch memory address space range: the length of Memory Base/Limit is 16bits, wherein Memory Base/Limit [3:0] must be 0, the length of non-prefetch Memory address is always 32bits, and does not exceed 4GB host Memory { Memory Base [15:4],00000H } - { Memory Limit [15:4], FFFH }, and the routing table composed of the constructed non-prefetch address space routing table entries is shown in Table 5.
TABLE 5
The ID routing table entry includes: a downstream port device number and a BUS number range corresponding to the downstream port device number. The index of the ID routing table entry is each downstream port device number and the BUS number range (composed of upstream and downstream) corresponding to each downstream port device number, and the routing table composed of the constructed ID routing table entries is shown in table 6. According to one embodiment of the invention, in order to flexibly support an address in any space, each type of address register or RAM bit width takes the maximum value during chip design.
TABLE 6
It can be seen from the above embodiments that the method of the present invention can construct the upstream port routing table, and the constructed upstream port routing table can implement peer-to-peer communication from the operating system connected to the PCIe upstream port to the device connected to the PCIe downstream destination port.
According to an embodiment of the present invention, the present invention further provides a data forwarding method based on an upstream port routing table of a PCIe switch chip, as shown in fig. 2, where the upstream port stores a routing table configured by using the upstream port routing table constructing method of the present invention, the method includes steps T1, T2, and T3, and each step is described in detail below.
In step T1, the upstream port receives a data packet from the operating system connected to the upstream port.
In step T2, the destination downstream port corresponding to the destination information of the packet is looked up in the upstream port routing table based on the destination information in the packet received in step T1.
In step T3, the data packet is forwarded to the destination downstream port obtained in step T2.
According to an embodiment of the present invention, the present invention further provides a PCIe switch chip upstream port routing table system, as shown in fig. 3, the system includes: the upstream port configuration packet analysis module is used for capturing a configuration packet related to the configuration of the downstream port route, analyzing the configuration packet to extract information related to the configuration of the downstream port route and sending the information to the upstream port route table construction module; an upstream port routing table constructing module, configured to receive the information extracted by the upstream port configuration packet parsing module and construct an upstream port routing table entry, where the upstream port routing table entry at least includes downstream port device number information and routing information corresponding to each downstream port device number; the upstream port routing table storage module is used for storing the upstream port routing table constructed by the upstream port routing table construction module; and the upstream port route searching module is used for searching a corresponding routing table item in the routing table according to the routing information in the data packet sent by the operating system and received by the upstream port and carrying out routing according to the destination downstream port in the routing table item.
The operation of the upstream port routing table system is described in detail below: 1. the upstream port configuration packet analysis module captures a configuration packet which is issued by an operating system connected with the upstream port, is used for configuring the downstream port and is related to the routing, and because the routing range represented by a register in the configuration space of the upstream port is the set of all the routing ranges of the downstream port, the routing of the upstream port only needs to construct a routing table entry of each single downstream port; 2. the upstream port configuration packet analysis module analyzes the configuration packet, extracts and configures the routing related information of the downstream port and sends the routing related information to the upstream port routing table construction module; 3. the upstream port routing table constructing module constructs an upstream port routing table according to the extracted information and writes the upstream port routing table into the upstream port routing table storage module, and the upstream port routing table storage module contains routing table entries. According to an embodiment of the present invention, the storage medium is not limited, and may be a RAM, a register, or the like.
The following describes a specific implementation process of forwarding a data packet through a constructed upstream port routing table, by taking an example of initiating an IO write request from a CPU to a device connected to a specified destination downstream port, and a routing process of other types of requests (such as an IO read request, a memory read/write, and a completion packet) and a process of forwarding a data packet between downstream ports through a downstream port routing table are similar to the above.
Firstly, when an upstream port configuration packet analysis module receives a data packet, judging, if the data packet is not a configuration packet for configuring a downstream port, forwarding the data packet to a route searching module for routing; then, the upstream port route searching module firstly judges the packet type, and if the packet type is IO read-write, the packet type is matched with an IO space route table; if the packet is a memory read-write packet, matching a non-prefetch memory address space routing table with a prefetch memory address space routing table; if the configuration packet is a completion packet or a non-downstream port, the ID routing table entry is matched.
In this embodiment, taking an IO write packet as an example, the Fmt field is 0b010, and the Type field is 0b00010, which represents that the Type of the packet is an IO write request packet. The route searching module searches an IO Address space routing table (table 7) according to an Address field carried in the packet header, and matches the Address [31:0] in the Address range of which table entry, in this example, corresponding to table entry 2 in table 7, so that the destination downstream output port corresponding to the packet is the port with the downstream port device number of 1, thereby obtaining a correct destination downstream port, and the CPU sends the IO write packet to the device connected to the port with the downstream port device number of 1 through the constructed upstream port routing table.
TABLE 7
As can be seen from the description of the above embodiments, the method of the present invention can construct a routing table at the upstream port of the PCIe chip, and by looking up the routing table, it can implement point-to-point communication between the operating system connected to the PCIe upstream port and the device connected to the PCIe downstream port, without broadcasting the packet to all downstream ports, which saves the time for forwarding data, is more direct and efficient, makes full use of the performance of the switching network in the switch, improves the throughput of the entire PCIe switch chip, and reduces the processing of the port packet and the processing delay of the packet.
Further, the inventor also designs a PCIe switch chip downstream port routing table constructing method, as shown in fig. 4, a routing table entry from a downstream port to other downstream ports is constructed, and based on the constructed downstream port routing table entry, end-to-end communication between a device connected to a PCIe downstream port and devices connected to other downstream ports can be implemented. According to an embodiment of the invention, the PCIe switch chip downstream port routing table construction method includes performing steps P1 and P2 on each downstream port until the routing table entry construction from the downstream port to other downstream ports is completed, and each step is described in detail below.
In step P1, the downstream port receives the configuration packet related to the downstream port route, which is captured by the upstream port and sent by the operating system connected to the downstream port. The routing related information refers to routing information that can indicate a path from an upstream port to a downstream port directly, where the routing information may be routing information such as an address routing table, an ID routing table, an implicit routing table, a multicast table, and the like.
Each port in the PCIe switch chip has a configuration space based on the characteristics of the PCIe protocol itself, where the protocol specifies that the configuration space fields associated with ID routing and address routing have a number range in registers of 18h-30 h. Table 1 as in the previous embodiment shows the address routing related register specific content and the ID routing related register specific content based on the PCIe protocol.
The configuration space is configured when the host operating system is powered on and enumerated, as table 2 in the previous embodiment shows a read-write configuration packet format based on the PCIe protocol, because the read-write configuration format is specified by the PCIe protocol, the present invention does not describe the meaning of each field, but only describes the fields related to the route, wherein the specific content of the configuration packet captured by the upstream port is: the Fmt field is 0b010, the Type field is 0b00100 or 0b00101, and the packet Type is a configuration write packet; the EP field is 0, which represents Payload of the configuration packet as valid data; the Bus Number field is the Bus Number of the upstream port plus one, wherein the Bus Number of the downstream port is the Bus Number of the upstream port plus 1, and the Bus Number of the upstream port can be obtained from the configuration space of the upstream port; the Device Number field does not exceed the Number of downstream ports of the PCIe switching chip; the Function Number field does not exceed the Number of functions realized by the downstream port of the switch chip (generally, only physical functions are realized, and the Function Number is 0); the value of the Rgist Number field is in the range of 18h-30 h; the extracted routing information includes: register Number, Payload, First DW BE (each bit of the First DW BE field corresponds to a byte enable bit of the First doubleword of the data Payload), Device Number
As can be seen from table 1, the register configuration space of each port includes ID routing information (represented by a BUS number) and address routing information, and as can be seen from table 2, each port, particularly a downstream port, is configured with a port device number, and then the port device number corresponds to the downstream port, and as can be seen from the combination of table 1 and table 2, the downstream port device number corresponding to the corresponding downstream port can be directly obtained by obtaining the ID number or address space range of the downstream port, so that an ID routing table entry can be constructed according to the ID number information in the configuration packet or an address routing table entry can be constructed according to the address space range, and end-to-end communication from the downstream port to other downstream ports can be realized through the routing table entry.
In step P2, the information related to the route in the configuration packet is parsed, and a downstream port routing table entry is constructed according to the parsed information related to the route, where the downstream port routing table entry at least includes information of a downstream port device number and routing information corresponding to each downstream port device number.
According to an embodiment of the present invention, the downstream port routing table entry of the present invention is: according to an embodiment of the present invention, the following takes the establishment of an address routing table entry and an ID routing table entry in a downstream port routing table as an example.
As can be seen from Table 1 above, the address space ranges may include IO address space ranges, prefetcheable memory address space ranges, and non-prefetched memory address space ranges.
Thus, the address routing table entry may be constructed as: IO address space routing table entries, and/or prefetcheable memory address space routing table entries, and/or non-prefetched memory address space routing table entries; wherein, the IO address space routing table entry at least includes: a downstream port device number and an IO address space range corresponding to the downstream port device number; the prefetch memory address space routing table entry at least comprises: a downstream port device number and a prefetcheable memory address space range corresponding to the downstream port device number; the non-prefetch memory address space routing table entry at least comprises: a downstream port device number and a non-prefetched memory address space range corresponding to the downstream port device number.
Specifically, similar to the routing table entry of the upstream port, the index of the IO address routing table entry of the downstream port is the downstream port device number, and the IO address space range corresponding to each downstream port device number, where the IO address space range: the length of the I/O Limit/Base is 8bits, wherein when the I/O Limit/Base [3:0] is 1, the I/O Limit Upper16bits and the I/O Base Upper16bits are supported, the length of an IO address is 32bits, and the address space is as follows: { I/O Base Upper16bits, I/O Base [7:4],000H } - { I/O Limit Upper16bits, I/O Limit [7:4], FFFH }; if the I/O Limit/Base [3:0] is 0, the I/O Limit Upper16bits and the I/O Base Upper16bits are not supported, the address length is 16bits, and the IO address space is as follows: { I/O Base [7:4],000H } - { I/O Limit [7:4], FFFH }; the rest values of I/O Limit/Base [3:0] are reserved, the routing table formed by the constructed IO address space routing table items is consistent with the IO address space routing table of the upstream port (as shown in table 3), and it can be seen that in each table item, one downstream port device number corresponds to one IO address space range, and the corresponding destination port device number can be found by matching the IO address space range in the data packet.
The index of the prefetcheable address routing table entry of the downstream port is the downstream port device number, and the prefetcheable address space range corresponding to each downstream port device number, wherein the prefetcheable memory address space range is as follows: the length of the prettchable Memory Limit/Base is 16bits, wherein the length of the prettchable Memory Limit/Base [3:0] represents 64bits when the prettchable Memory Limit/Base [1 ], the length of the prettchable Memory Base [31:0], the prettchable Memory Base [15:4], the 00000H ], the Upper prettchable Memory Base [31:0] prettchable Memory Base [15:4], the FFFFFH }; when the address space is 0, the length of the address capable of being prefetched is 32bits, and the address space is as follows: { prefectchable Memory Base [15:4], 00000H-prefectchable Memory Base [15:4], FFFFFH }, where a routing table formed by constructed routing table entries of the prefetcheable address space is consistent with a routing table of the prefetcheable address space of the upstream port (as shown in table 4), and it can be seen that in each table entry, a device number of a downstream port corresponds to a range of the prefetcheable address space, and a device number of a corresponding destination port can be found by matching the range of the prefetcheable address space in the data packet.
The index of the non-prefetch address routing table entry of the downstream port is the downstream port device number, the non-prefetch address space range corresponding to each downstream port device number, wherein the non-prefetch memory address space range: the length of Memory Base/Limit is 16bits, wherein Memory Base/Limit [3:0] must be 0, the length of non-prefetch Memory address is always 32bits, and does not exceed 4GB host Memory { Memory Base [15:4],00000H } - { Memory Limit [15:4], FFFFFH }, and the routing table composed of the constructed non-prefetch address space routing table entries is consistent with the non-prefetch address space routing table of the upstream port (as shown in table 5).
The ID routing table entry of the downstream port includes: a downstream port device number and a BUS number range corresponding to the downstream port device number. The index of the ID routing table entry is each downstream port device number and the BUS number range (composed of upstream and downstream) corresponding to each downstream port device number, and the routing table composed of the constructed ID routing table entries is consistent with the ID routing table of the upstream port (as shown in table 6). According to one embodiment of the invention, in order to flexibly support an address in any space, each type of address register or RAM bit width takes the maximum value during chip design.
It can be seen from the above embodiments that the method of the present invention can construct the downstream port routing table, and the constructed downstream port routing table can implement end-to-end communication from a device connected to any downstream port of PCIe to a device connected to other downstream destination ports of PCIe.
According to an embodiment of the present invention, the present invention further provides a data forwarding method based on a PCIe switch chip downstream port routing table, as shown in fig. 5, where the downstream port stores a routing table configured by using the downstream port routing table constructing method of the present invention, the method includes steps R1, R2, and R3, and each step is described in detail below.
In step R1, the downstream port receives a packet from the device to which it is connected.
In step R2, the destination downstream port corresponding to the packet destination information is looked up in the downstream port routing table based on the destination information in the packet received in step R1.
In step R3, the packet is forwarded to the destination downstream port obtained in step R2.
It should be noted that some fixed type packets or packets with failed routing will be forwarded to the upstream port, so the destination port in the "forward packet to the destination downstream port obtained in step R2" in step R3 only refers to the destination downstream port that needs to receive the packet and successfully get the routing.
According to an embodiment of the present invention, the present invention further provides a PCIe switch chip downstream port routing table system, as shown in fig. 6, the system includes: a downstream port configuration packet parsing module, configured to receive and parse a configuration packet forwarded by an upstream port, extract information related to configuring a downstream port route in the configuration packet, and send the information to a downstream port route table construction module, where it needs to be noted that the configuration packet received by the downstream port is a configuration packet that includes information related to configuring a downstream port route and is captured by the upstream port configuration packet parsing module in the upstream port route table system; a downstream port routing table constructing module, configured to receive the information extracted by the downstream port configuration packet parsing module and construct a downstream port routing table entry, where the downstream port routing table entry at least includes information of a downstream port device number and routing information corresponding to each downstream port device number; the downstream port routing table storage module is used for storing the downstream port routing table constructed by the downstream port routing table construction module; and the downstream port route searching module is used for searching a corresponding routing table entry in the routing table according to the routing information received by the downstream port from the data packet sent by the equipment connected with the downstream port and carrying out routing according to the destination downstream port in the routing table entry.
It should be noted that some fixed type packets or packets with failed routing will be forwarded to the upstream port, and therefore, the destination port in "find the corresponding routing table entry and route according to the destination downstream port in the routing table entry" in the downstream port route lookup module here is the same as the step R3 described above, and also refers to only the destination downstream port that needs to receive the packet and successfully obtains the routing.
In addition, since the process of constructing the routing table by each downstream port is the same, which is equivalent to that the upstream port needs to send the configuration packet related to the routing to each downstream port, based on this, the inventor configures an upstream port configuration packet broadcasting module in the upstream port routing table system, so as to broadcast the configuration packet captured by the upstream port configuration packet parsing module to all downstream ports, and avoid the upstream port sending the configuration packet to each downstream port individually, so as to save the working time and bandwidth and improve the efficiency.
The operation of the downstream port routing table system is described in detail below: 1. an upstream port configuration packet analysis module captures a configuration packet which is used for configuring a downstream port and is related to a route; 2. the upstream port configuration packet analysis module continuously sends the captured configuration packet to an upstream port configuration packet broadcasting module, and the upstream port configuration packet broadcasting module broadcasts the configuration packet to all downstream port configuration packet analysis modules so that the downstream ports construct a routing table; 3. the downstream port configuration packet analysis module analyzes the configuration packet forwarded by the upstream port, extracts information related to the configuration of the downstream port route and sends the information to the downstream port route table construction module; 4. the downstream port routing table constructing module constructs a downstream port routing table and writes the downstream port routing table into a downstream port routing table storage module, and the downstream port routing table storage module contains routing table entries. According to an embodiment of the present invention, the storage medium is not limited, and may be a RAM, a register, or the like.
As can be seen from the description of the above embodiment, the method of the present invention can construct a routing table at the downstream port of the PCIe chip, and by looking up the routing table, end-to-end communication from a device connected to the PCIe downstream port to a device connected to another destination downstream port obtained by looking up the routing table can be achieved, and it is also not necessary to broadcast a packet to all downstream ports, so that time for forwarding data is saved, and the method is more direct and efficient, and makes full use of the performance of a switching network in a switch, improves throughput of the entire PCIe switch chip, and reduces processing of port packets, and reduces processing delay of packets.
According to an embodiment of the present invention, the present invention further provides a PCIe switch chip, where the chip includes an upstream port and a plurality of downstream ports, and the upstream port stores an upstream port routing table constructed by using an upstream port routing table construction method; the downstream port stores a downstream port routing table constructed by adopting a downstream port routing table construction method.
According to an embodiment of the present invention, the present invention further provides a PCIe switching system, the overall system structure of which is shown in fig. 7, the system includes an upstream port and a plurality of downstream ports, the upstream port is configured with an upstream port routing table system, and the system includes: the upstream port configuration packet analysis module is used for capturing a configuration packet related to the configuration of the downstream port route, analyzing the configuration packet to extract information related to the configuration of the downstream port route and sending the information to the upstream port route table construction module; an upstream port routing table constructing module, configured to receive the information extracted by the upstream port configuration packet parsing module and construct an upstream port routing table entry, where the upstream port routing table entry at least includes downstream port device number information and routing information corresponding to each downstream port device number; the upstream port routing table storage module is used for storing the upstream port routing table constructed by the upstream port routing table construction module; and the upstream port route searching module is used for searching a destination downstream port corresponding to the destination information of the data packet in the upstream port route table according to the route information in the data packet received by the upstream port and sent by the operating system and routing the data packet. According to an embodiment of the present invention, the upstream port routing table system further includes an upstream port configuration packet broadcasting module, configured to broadcast the configuration packet captured by the upstream port and related to configuring the downstream port route to all the downstream ports, so as to avoid the upstream port from separately sending the configuration packet to each downstream port, thereby saving working time and bandwidth and improving efficiency. Each downstream port is configured with a downstream port routing table system comprising: the downstream port configuration packet analysis module is used for receiving and analyzing the configuration packet forwarded by the upstream port, extracting information related to the configuration of the downstream port route in the configuration packet, and sending the information to the downstream port route table construction module; a downstream port routing table constructing module, configured to receive the information extracted by the downstream port configuration packet parsing module and construct a downstream port routing table entry, where the downstream port routing table entry at least includes information of a downstream port device number and routing information corresponding to each downstream port device number; the downstream port routing table storage module is used for storing the downstream port routing table constructed by the downstream port routing table construction module; and the downstream port route searching module is used for searching a destination downstream port corresponding to the destination information of the data packet in a downstream port route table according to the route information in the data packet received by the downstream port and sent by the equipment connected with the downstream port and routing the destination downstream port.
In summary, the present invention implements peer-to-peer direct communication from an operating system connected to a PCIe upstream port to a device connected to a downstream destination port and peer-to-peer communication between devices connected to different PCIe downstream ports by constructing a PCIe chip upstream port and downstream port routing table and sending packets using the routing table.
Compared with the prior art, the invention has the advantages that:
1. the method for constructing the routing table by the PCIe exchange chip can actively analyze data packets passing through the exchange chip and construct the routing table in real time, and can realize point-to-point direct communication from an operating system connected with a PCIe upstream port to equipment connected with a downstream destination port and end-to-end communication between different equipment connected with the PCIe downstream port by constructing the routing table.
2. And a special processor (such as ARM, MCU, DSP and the like) is not needed to configure the routing table, so that resources are saved.
3. The method for constructing the routing table simultaneously comprising the upstream port and the downstream port can construct the routing table in real time without transmitting the data packet to all the downstream ports in a broadcasting mode, is more direct and efficient, fully utilizes the performance of a switching network in a switch, improves the throughout of the whole PCIe switching chip, reduces the processing of port data packets and reduces the processing delay of the data packets.
It should be noted that, although the steps are described in a specific order, the steps are not necessarily performed in the specific order, and in fact, some of the steps may be performed concurrently or even in a changed order as long as the required functions are achieved.
The present invention may be a system, method and/or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied therewith for causing a processor to implement various aspects of the present invention.
The computer readable storage medium may be a tangible device that retains and stores instructions for use by an instruction execution device. The computer readable storage medium may include, for example, but is not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing.
Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (18)
1. A PCIe switching chip upstream port routing table building method, the method comprising:
s1, the upstream port captures the configuration packet related to the downstream port route issued by the operating system connected with the upstream port;
s2, analyzing the information related to the route in the configuration packet and constructing an upstream port routing table entry according to the analyzed information related to the route, wherein the upstream port routing table entry at least comprises downstream port equipment number information and routing information corresponding to each downstream port equipment number.
2. The method of claim 1, wherein the upstream port routing table entry is: an address routing entry, and/or an ID routing entry, and/or an implicit routing entry, and/or a multicast entry.
3. The method of claim 2, wherein the address routing table entry is: IO address space routing table entries, and/or prefetcheable memory address space routing table entries, and/or non-prefetched memory address space routing table entries;
wherein, the IO address space routing table entry at least includes: a downstream port device number and an IO address space range corresponding to the downstream port device number;
the prefetch memory address space routing table entry at least comprises: a downstream port device number and a prefetcheable memory address space range corresponding to the downstream port device number;
the non-prefetch memory address space routing table entry at least comprises: a downstream port device number and a non-prefetched memory address space range corresponding to the downstream port device number.
4. The method of claim 2, wherein the ID routing table entry comprises: a downstream port device number and a BUS number range corresponding to the downstream port device number.
5. A PCIe switch chip based data forwarding method, wherein an upstream port includes an upstream port routing table configured according to the method of any one of claims 1 to 4, the method comprising:
t1, the upstream port receives the data packet from the operating system connected with it;
t2, based on the destination information in the data packet received in step T1, looking up the destination downstream port corresponding to the destination information of the data packet in the upstream port routing table;
t3, forwarding the data packet to the destination downstream port obtained in the step T2.
6. A PCIe switch chip upstream port routing table system, the system comprising:
the upstream port configuration packet analysis module is used for capturing a configuration packet related to the configuration of the downstream port route, analyzing the configuration packet to extract information related to the configuration of the downstream port route and sending the information to the upstream port route table construction module;
an upstream port routing table constructing module, configured to receive the information extracted by the upstream port configuration packet parsing module and construct an upstream port routing table entry, where the upstream port routing table entry at least includes downstream port device number information and routing information corresponding to each downstream port device number;
and the upstream port routing table storage module is used for storing the upstream port routing table constructed by the upstream port routing table construction module.
7. The upstream port routing table system of claim 6, further comprising:
and the upstream port route searching module is used for searching a destination downstream port corresponding to the destination information of the data packet in the upstream port route table according to the route information in the data packet received by the upstream port and sent by the operating system and routing the data packet.
8. A PCIe switching chip downstream port routing table building method comprises the following steps:
p1, the downstream port receives the configuration packet which is captured by the upstream port and is sent by the operating system connected with the upstream port and related to the downstream port route;
and P2, analyzing the information related to the route in the configuration packet and constructing a downstream port routing table entry according to the analyzed route related information, wherein the downstream port routing table entry at least includes downstream port device number information and routing information corresponding to each downstream port device number.
9. The method of claim 8, wherein the downstream port routing table entry is: an address routing entry, and/or an ID routing entry, and/or an implicit routing entry, and/or a multicast entry.
10. The method of claim 9, wherein the address routing table entry is: IO address space routing table entries, and/or prefetcheable memory address space routing table entries, and/or non-prefetched memory address space routing table entries;
wherein, the IO address space routing table entry at least includes: a downstream port device number and an IO address space range corresponding to the downstream port device number;
the prefetch memory address space routing table entry at least comprises: a downstream port device number and a prefetcheable memory address space range corresponding to the downstream port device number;
the non-prefetch memory address space routing table entry at least comprises: a downstream port device number and a non-prefetched memory address space range corresponding to the downstream port device number.
11. The method of claim 9, wherein the ID routing table entry comprises: a downstream port device number and a BUS number range corresponding to the downstream port device number.
12. A PCIe switch chip based data forwarding method, wherein a downstream port includes a downstream port routing table configured according to the method of any one of claims 8 to 11, the method comprising:
r1, the downstream port receives the data packet sent by the device connected with the downstream port;
r2, based on the destination information in the data packet received in the step R1, searching a destination downstream port corresponding to the destination information of the data packet in a downstream port routing table;
and R3, forwarding the data packet to the destination downstream port obtained in the step R2.
13. A PCIe switch chip downstream port routing table system, the system comprising:
the downstream port configuration packet analysis module is used for receiving and analyzing the configuration packet forwarded by the upstream port, extracting information related to the configuration of the downstream port route in the configuration packet, and sending the information to the downstream port route table construction module;
a downstream port routing table constructing module, configured to receive the information extracted by the downstream port configuration packet parsing module and construct a downstream port routing table entry, where the downstream port routing table entry at least includes information of a downstream port device number and routing information corresponding to each downstream port device number;
and the downstream port routing table storage module is used for storing the downstream port routing table constructed by the downstream port routing table construction module.
14. The downstream port routing table system of claim 13, further comprising:
and the downstream port route searching module is used for searching a destination downstream port corresponding to the destination information of the data packet in a downstream port route table according to the route information in the data packet received by the downstream port and sent by the equipment connected with the downstream port and routing the destination downstream port.
15. A PCIe switch chip, said chip comprising an upstream port and a plurality of downstream ports, characterized in that:
the upstream port stores an upstream port routing table constructed by the method according to any one of claims 1 to 4;
the downstream port stores a downstream port routing table constructed by the method of any one of claims 8 to 11.
16. A PCIe switching system, said system comprising an upstream port and a plurality of downstream ports, characterized in that:
the upstream port is configured with an upstream port routing table system according to any of claims 6-7;
each downstream port is configured with a downstream port routing table system according to any of claims 13-14;
wherein the upstream port routing table system further comprises:
the upstream port configuration packet broadcasting module is used for broadcasting the configuration packet which is captured by the upstream port and is related to the configuration of the downstream port route to all the downstream ports.
17. A computer-readable storage medium, on which a computer program is stored which is executable by a processor for carrying out the steps of the method according to any one of claims 1-4 or 5 or 8-11 or 12.
18. An electronic device, comprising:
one or more processors;
storage means for storing one or more programs which, when executed by the one or more processors, cause the electronic device to carry out the steps of the method of any of claims 1-4 or 5 or 8-11 or 12.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118069571A (en) * | 2024-04-24 | 2024-05-24 | 北京数渡信息科技有限公司 | PCIe (peripheral component interconnect express) switching chip with aggregate communication on-line computing function and PCIe switch |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117929A (en) * | 2013-01-31 | 2013-05-22 | 中国科学院计算技术研究所 | Communication method and system based on PCIe (peripheral component interconnect express) data exchange |
| CN103209134A (en) * | 2013-04-22 | 2013-07-17 | 杭州华三通信技术有限公司 | Method and equipment for multicast forwarding |
| CN104883631A (en) * | 2015-05-13 | 2015-09-02 | 烽火通信科技股份有限公司 | Network data packet obtaining system and method |
| CN105515991A (en) * | 2014-09-23 | 2016-04-20 | 中兴通讯股份有限公司 | Method for extending the routing table capacity of three-layer forwarding equipment, and forwarding equipment |
| CN111092773A (en) * | 2019-12-25 | 2020-05-01 | 成都九芯微科技有限公司 | PCIE (peripheral component interface express) switching chip port configuration system and method supporting virtual switching |
-
2021
- 2021-12-23 CN CN202111587285.XA patent/CN114265805A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117929A (en) * | 2013-01-31 | 2013-05-22 | 中国科学院计算技术研究所 | Communication method and system based on PCIe (peripheral component interconnect express) data exchange |
| CN103209134A (en) * | 2013-04-22 | 2013-07-17 | 杭州华三通信技术有限公司 | Method and equipment for multicast forwarding |
| CN105515991A (en) * | 2014-09-23 | 2016-04-20 | 中兴通讯股份有限公司 | Method for extending the routing table capacity of three-layer forwarding equipment, and forwarding equipment |
| CN104883631A (en) * | 2015-05-13 | 2015-09-02 | 烽火通信科技股份有限公司 | Network data packet obtaining system and method |
| CN111092773A (en) * | 2019-12-25 | 2020-05-01 | 成都九芯微科技有限公司 | PCIE (peripheral component interface express) switching chip port configuration system and method supporting virtual switching |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118069571A (en) * | 2024-04-24 | 2024-05-24 | 北京数渡信息科技有限公司 | PCIe (peripheral component interconnect express) switching chip with aggregate communication on-line computing function and PCIe switch |
| CN118069571B (en) * | 2024-04-24 | 2024-06-18 | 北京数渡信息科技有限公司 | PCIe (peripheral component interconnect express) switching chip with aggregate communication on-line computing function and PCIe switch |
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