CN112799991B - PCIE switching chip - Google Patents

PCIE switching chip Download PDF

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CN112799991B
CN112799991B CN202110028138.2A CN202110028138A CN112799991B CN 112799991 B CN112799991 B CN 112799991B CN 202110028138 A CN202110028138 A CN 202110028138A CN 112799991 B CN112799991 B CN 112799991B
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register
virtual
area
switching
pcie
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CN112799991A (en
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杨珂
唐重林
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Niuxin Semiconductor Shenzhen Co ltd
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Niuxin Semiconductor Shenzhen Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Abstract

The application relates to the technical field of PCIE, and provides a PCIE switching chip, which comprises a protection switching module and at least two divided virtual switching areas, wherein the protection switching module is configured as follows: determining a first virtual switching area with abnormal occurrence of a connected host and a second virtual switching area serving as a spare by reading first indication information in an upstream heartbeat register corresponding to each virtual switching area; writing a first register corresponding to the first virtual exchange area; and writing a first register corresponding to the second virtual exchange area; after the write operation is completed, triggering a doorbell register corresponding to the second virtual switching area to send interrupt information to a corresponding host, thereby realizing protection switching in the PCIE switching chip.

Description

PCIE switching chip
Technical Field
The present application relates to the technical field of Peripheral Component Interconnect Express (PCIE) of a computer, and in particular, to a PCIE switch chip.
Background
In the existing multi-host system, a PCIE switch chip is configured in a partitioned manner, that is, two or more virtual switch areas are divided at the PCIE switch chip, so that a plurality of hosts can be connected to the same PCIE switch chip. An upstream port in a virtual switch area is connected with a host, a downstream port is connected with PCIE equipment, and in the working process, the host provides service for the PCIE equipment connected with the downstream port in the virtual switch area. The PCIE device refers to an I/O device that receives services of a host connected to the local virtual switch area.
In a PCIE switch chip, there is a situation that a host connected to a virtual switch area cannot provide a service for PCIE devices connected to the virtual switch area, for example, when the host is abnormal, a link where the host is located fails. Because at least two virtual switching areas are divided in the PCIE switching chip, and each virtual switching area is connected to a host, when a situation occurs in which the host connected to one virtual switching area cannot provide service for the PCIE device connected to the virtual switching area, how to provide service for the PCIE device connected to the downstream port of the virtual switching area in which the abnormality occurs by using the host connected to the other virtual switching area in the PCIE switching chip in the normal operating state, so as to implement protection switching.
Disclosure of Invention
Embodiments of the present application provide a PCIE switch chip, and thus protection switching can be implemented in the PCIE switch chip.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.
According to an aspect of the embodiments of the present application, a PCIE switch chip is provided, including a protection switching module and at least two divided virtual switch areas, where ports in the PCIE switch chip are divided into each virtual switch area;
the PCIE switching chip can divide the PCIE switching chip into a plurality of virtual switching areas through a first register, a third register and a second enabling register in the PCIE switching chip, and one virtual switching area is specified through the first register, the third register and the second enabling register;
the first register is used for storing first indication information, the first indication information is used for indicating ports included in a virtual switching area, the ports include an upstream port and a downstream port, the upstream port is used for being connected with a host, and the downstream port is used for being connected with PCIE equipment;
a virtual switch area includes one or more ports, and the third register designates a port of the associated virtual switch area as an upstream port of the virtual switch area;
the second enabling register enables the virtual exchange work specified by the first register and the third register;
in addition, each port of the PCIE switch chip includes a heartbeat register and a doorbell register, the heartbeat register corresponding to the upstream port is referred to as an upstream heartbeat register, and the doorbell register corresponding to the upstream port is referred to as an upstream doorbell register;
the upstream heartbeat register is connected with the upstream port and is used for storing second indication information, and the second indication information is used for indicating whether the host corresponding to the virtual switching area in which the host is located has an abnormal condition or not;
the doorbell register is used for sending interrupt information to the host connected with the upstream port, and the interrupt information is used for indicating the connected host to enumerate the ports in the virtual switching area according to the first indication information stored in the corresponding first register;
the protection switching module can perform read-write operation on the first register, the third register, the second enabling register, the heartbeat register and the doorbell register;
the protection switching module is configured to:
determining a first virtual switching area and a second virtual switching area which is used as a spare area when the connected host is in an abnormal condition by reading second indication information in an upstream heartbeat register corresponding to each virtual switching area;
writing a first register corresponding to the first virtual switching area to delete information indicating a downstream port in the first virtual switching area, which is stored in the first register corresponding to the first virtual switching area; performing write operation on a first register corresponding to the second virtual switching area to add and store information indicating a downstream port in the first virtual switching area into the first register corresponding to the second virtual switching area;
and after the write operation is finished, triggering a doorbell register corresponding to the second virtual exchange area to send interrupt information to a corresponding host.
In one implementation of the present application, the protection switching module includes a second register, where the second register is used to store first indication information stored in a first register before a write operation is performed;
the protection switching module is further configured to:
reading second indication information in the upstream heartbeat register corresponding to the first virtual switching area again, resetting the second indication information in the upstream heartbeat register corresponding to the virtual switching area to first state information according to a first set period by a host connected to the virtual switching area, wherein the first state information is used for indicating that the host corresponding to the virtual switching area is in a normal working state;
if the second indication information read again is first state information, reading first information and second information from the second register, wherein the first information is first indication information stored in a first register corresponding to the first virtual switching area before write operation is carried out, and the second information is first indication information stored in a first register corresponding to the second virtual switching area before write operation is carried out;
resetting the first indication information stored in the first register corresponding to the first virtual switching area as the first information and resetting the first indication information stored in the first register corresponding to the second virtual switching area as the second information.
Triggering the doorbell register corresponding to the first virtual switching area to send interrupt information to the corresponding host and triggering the doorbell register corresponding to the second virtual switching area to send interrupt information to the corresponding host.
In an implementation of the present application, after reading the second indication information stored in the upstream heartbeat register corresponding to each virtual switching area, if the read second indication information is the first state information, the protection switching module resets the second indication information stored in the upstream heartbeat register corresponding to the virtual switching area to the second state information, and reads the second indication information stored in the upstream heartbeat register again according to a second setting period, where the second state information is used to indicate that an abnormal condition occurs in a host corresponding to the virtual switching area, and a duration of the first setting period does not exceed a duration of the second setting period.
In an implementation of the present application, the virtual switch area further includes a third register, where the third register is configured to store fourth indication information, and the fourth indication information is used to indicate an upstream port in the virtual switch area where the virtual switch area is located.
In one implementation of the present application, the PCIE switch chip further includes a first enable register, where the first enable register is connected to the protection switching module, the first enable register is configured to store a first enable signal, and the first enable signal is configured to enable the protection switching module.
In one implementation of the present application, when it is determined that a host corresponding to the first virtual switching area is abnormal, the PCIE switching chip includes at least one virtual switching area where the connected host is in a normal operating state, and when only one connected host is in the virtual switching area in the normal operating state, the virtual switching area is determined as the second virtual switching area;
when there are two or more connected hosts in a virtual switching area in a normal operating state, the protection switching module is further configured to:
reading priority information configured for a virtual switching area in the PCIE switching chip;
and determining the virtual switching area with the highest priority in the virtual switching areas of the two or more connected hosts in the normal working state according to the priority information, and determining the virtual switching area with the highest priority as the second virtual switching area.
In an implementation of the present application, the PCIE switch chip further includes a crossbar module, where the crossbar module is configured to control and connect ports in the same virtual switch area in the PCIE switch chip, so that the ports in the same virtual switch area can communicate data streams with each other.
In one implementation of the present application, the PCIE switch chip further includes a port reset register, and before the protection switching module performs a write operation on the first register, the protection switching module performs a write operation on a reset register corresponding to an upstream port in a virtual switch area where the first register to be subjected to the write operation is located, so as to generate a reset signal.
In one implementation of the present application, a first interface is disposed on the PCIE switch chip, the first interface may be used for externally connecting a programmable read only memory, and a register inside the PCIE switch chip performs initialization loading through the programmable read only memory externally connected to the first interface.
In an implementation of the present application, the PCIE switch chip further includes a fourth register, before an upstream port in the virtual switch area is reset, the fourth register sends a load prohibition signal to the first interface, where the load prohibition signal is used to instruct the first interface to prohibit information loading through the external programmable read only memory. After the protection switching is completed, the fourth register is further configured to send a load start signal to the first interface, so as to allow information loading through an external programmable read-only memory.
In the scheme of the application, whether the host corresponding to the virtual switching area is abnormal is determined based on an upstream heartbeat register set for an upstream port of each virtual switching area in the PCIE switching chip, and when the host corresponding to one virtual switching area is abnormal, the protection switching module performs a write operation on a first register corresponding to a first virtual switching area where the host is abnormal and a first register corresponding to a second virtual switching area serving as a standby, so that a downstream port of the first virtual switching area is transferred to the second virtual switching area before the write operation is performed. Correspondingly, after the host in the second virtual switching area enumerates according to the first indication information in the first register corresponding to the second virtual switching area after the write operation, the host in the second virtual switching area correspondingly learns the port belonging to the second virtual switching area, and the host in the second virtual switching area provides service for the PCIE device originally hung in the first virtual switching area, so that the protection switching is realized.
Moreover, in the scheme of the application, since the information is transmitted by setting the hardware physically connected with the first register, the upstream heartbeat register and the doorbell register in the PCIE switch chip, rather than by using a software manner, there are no processes of encoding and decoding the transmitted information, and the response speed block can ensure that the PCIE switch chip can process efficiently in time when an abnormal condition occurs in the virtual switch area, thereby ensuring timeliness and rapidity of implementing protection switching.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram illustrating a division of a virtual switch area in a PCIE switch chip according to an embodiment;
fig. 2 is a flowchart illustrating a protection switching module implementing protection switching according to an embodiment;
fig. 3 is a flowchart illustrating protection switching recovery after the first virtual switch area is recovered to normal according to an embodiment;
fig. 4 is a block diagram of a PCIE switch chip shown in accordance with a particular embodiment;
fig. 5 is a schematic diagram illustrating a division of a virtual switch area in the PCIE switch chip shown in fig. 4;
fig. 6 is a schematic diagram of ports actually included in each virtual switching area of the PCIE switching chip shown in fig. 5 after protection switching.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.
The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. I.e. these functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.
The flowcharts shown in the figures are illustrative only and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
The application provides a PCIE switching chip, under the default state, all ports of the switching chip are located in the same switching area, and can intercommunicate data with each other, but through register configuration, the switching chip can be divided into at least more than two virtual switching areas, the ports in the PCIE switching chip are divided into each virtual switching area, any port on the PCIE switching chip can only belong to one virtual switching area, and each virtual switching area at least comprises one port. According to the difference of the port functions, each port is set as an upstream port or a downstream port, the upstream port is connected with a host, the upstream port can be connected with the host through a Root Complex (Root Complex), the upstream port can also be connected with the Root Complex through other PCIE switching chips, then the Root Complex is connected with the host, and the downstream port is used for connecting PCIE equipment. In the working process, a host connected to an upstream port in a virtual switch area provides service for a PCIE device connected to a downstream port in the virtual switch area. Further, the number of downstream ports in each virtual switch area may be set according to actual needs, and is not specifically limited herein.
In the PCIE switch chip divided into virtual switch areas, although each virtual switch area is located in the same physical chip, the virtual switch areas are isolated from each other and do not communicate data streams.
Fig. 1 is a schematic diagram illustrating a division of a virtual switch area in a PCIE switch chip according to a specific embodiment, and as shown in fig. 1, three virtual switch areas, that is, a virtual switch area I, a virtual switch area II, and a virtual switch area III, are divided in the PCIE switch chip. The PCIE switching chip is provided with 12 ports, namely T0, T1, T2, 8230, 8230and T11. The ports belonging to the virtual switching area I in the PCIE switching chip include T0, T3, and T4, the ports belonging to the virtual switching area II include T1, T5, T6, and T7, and the ports belonging to the virtual switching area III include T2, T8, T9, T10, and T11. In the virtual switching area I, a port T0 is an upstream port and is connected with a host A; the ports T3 and T4 are downstream ports, and are respectively connected to a PCIE device. In the virtual switching area II, the port T1 is an upstream port and is communicated with the host B; the ports T5, T6, and T7 are downstream ports, and are respectively communicated with a PCIE device. In the virtual switching area III, the port T2 is an upstream port and is communicated with the host C; the ports T8, T9, T10, and T11 are downstream ports, and are respectively communicated with a PCIE device.
As described above, in a virtual switch area, a host connected to an upstream port of the virtual switch area provides services for PCIE devices connected to a downstream port of the virtual switch area, and in practice, there are inevitably situations where the host connected to the virtual switch area cannot provide services for PCIE devices connected to the virtual switch area, such as host exception and link failure where the host is located. Because at least two virtual switching areas are divided in the PCIE switching chip, and each virtual switching area is connected to a host, when a situation occurs in which the host connected to one virtual switching area cannot provide service for the PCIE device connected to the virtual switching area, how to provide service for the PCIE device connected to the downstream port of the virtual switching area in which the abnormality occurs by using the host connected to the other virtual switching area in the PCIE switching chip in the normal operating state, so as to implement protection switching. Based on this, the PCIE switch chip capable of implementing protection switching is provided.
In the embodiment of the application, a PCIE switch chip can divide itself into a plurality of virtual switch areas through a first register, a third register, and a second enable register inside the PCIE switch chip; each virtual switching area in the PCIE switching chip is specified by a first register, a third register and a second enabling register, and the third register is used for specifying one port of the virtual switching area as an upstream port of the virtual switching area;
the second enabling register enables the virtual exchange area designated by the first register and the third register to work;
in addition, each port of the PCIE switch chip includes a heartbeat register and a doorbell register, the heartbeat register corresponding to the upstream port is referred to as an upstream heartbeat register, and the doorbell register corresponding to the upstream port is referred to as an upstream doorbell register;
the first register is configured to store first indication information, where the first indication information is used to indicate a port included in the associated virtual switch area, the port includes an upstream port and a downstream port, the upstream port is used to connect to a host, and the downstream port is used to connect to a PCIE device.
And the upstream heartbeat register is connected with the upstream port and is used for storing second indication information, and the second indication information is used for indicating whether the host corresponding to the associated virtual switching area has an abnormal condition or not.
And the doorbell register is used for sending interrupt information to a host connected with the upstream port, reading the interrupt information by the host, and enumerating the ports in the associated virtual switching area according to the first indication information stored in the corresponding first register.
The protection switching module can perform read-write operation on the first register, the third register, the second enabling register, the heartbeat register and the doorbell register; it should be noted that, registers inside the PCIE switch chip (for example, the upstream heartbeat register, the first register, the doorbell register, and hereinafter, the second register, the third register, the first enable register, the port reset register, the fourth register, and the like) store information in binary codes. The register is composed of D flip-flops, each of which is capable of registering a one-bit binary code under the action of a clock pulse CP, for example, the register stores 0 when D =0 and 1 when D = 1. Therefore, because the number of the D flip-flops in the register is different, the information stored in the register inside the PCIE switch chip may be a binary code with one bit or a binary code with two or more bits.
The protection switching module is configured to implement protection switching according to steps 210-250 shown in fig. 2, which is specifically described as follows:
step 210, by reading the second indication information in the upstream heartbeat register corresponding to each virtual switching area, a first virtual switching area where an abnormal condition occurs in the connected host and a second virtual switching area serving as a spare are determined.
In the PCIE switch chip of the present application, the protection switching module is connected to each upstream heartbeat register, and the protection switching module may read the second indication information stored in the upstream heartbeat register.
It should be noted that each port in the PCIE switch chip is undifferentiated, because the configuration settings are different, one port in the virtual switch area is used as an upstream port and connected to the host, and the other ports are used as downstream ports and connected to the PCIE device.
In this context, each port in the PCIE switch chip is connected to a heartbeat register, so that a user performs upstream port designation according to actual needs to determine a corresponding upstream heartbeat register according to the designated upstream port. After the user sets the upstream port and the downstream port in the virtual switching area, the setting of the upstream heartbeat register for the upstream port is not required to be carried out again.
In the solution of the present application, the upstream heartbeat register refers to a heartbeat register connected to an upstream port of the virtual switch area. Each port of the PCIE switch chip is connected to one heartbeat register, and the upstream port specifies a heartbeat register corresponding to the port and is an upstream heartbeat register. In an embodiment, the virtual switch area further includes a third register, where the third register is used to store fourth indication information, and the fourth indication information is used to indicate an upstream port in the virtual switch area where the virtual switch area is located.
The first virtual switch area does not refer to a certain virtual switch area, but refers to a virtual switch area where an abnormal condition occurs in a host connected to the PCIE switch chip. In the first virtual switching area, the host connected to the first virtual switching area cannot provide a service for the PCIE device or the downstream switching chip connected to the downstream port in the first virtual switching area due to the occurrence of the abnormal condition, and the cause of the abnormal condition of the host connected to the first virtual switching area may be at least one of an abnormality of the host connected to the first virtual switching area and an abnormality of a link where the host connected to the first virtual switching area is located.
Similarly, the second virtual switch area does not refer to a certain virtual switch area, but refers to a standby virtual switch area determined to be used as a virtual switch area where an abnormal condition occurs in the connected host. It can be understood that the standby virtual switch is a virtual switch area in which the hosts connected to the PCIE switch chip are in a normal operating state.
As described above, since the information stored in the upstream heartbeat register is used to indicate whether the host corresponding to the corresponding virtual switching area is abnormal, the protection switching module may determine, by obtaining the second indication information stored in the upstream heartbeat register corresponding to each virtual switching area, the virtual switching area where the host connected to the PCIE switching chip is in a normal working state (that is, the connected host is not abnormal), and the virtual switching area where the connected host is abnormal.
In a virtual switch area, because the suspended PCIE device is serviced by the host connected to the upstream port, if an abnormality occurs in the host connected to the virtual switch area (for example, a host failure) and/or an abnormality occurs in a link where the host is located (for example, a link where the host is located is interrupted), the host may not provide service for the suspended PCIE device in the virtual switch area, and thus the virtual switch area is subjected to an abnormal condition.
For a PCIE switch chip divided into at least two virtual switch areas, a host in the virtual switch area in the PCIE switch chip in a normal operating state and a link where the host is located are both normal. In other words, the standby virtual switching area provides service for the PCIE devices that are originally suspended in the standby virtual switching area, and also provides service for the PCIE devices that are suspended in the first virtual switching area while providing service for the PCIE devices that are originally suspended in the standby virtual switching area.
It can be understood that, since there may be more than two virtual switch areas in the same PCIE switch chip, there may be one or more virtual switch areas with an exception at the same time. The second virtual switch area serving as the standby virtual switch area may take over only one first virtual switch area, or may take over a plurality of first virtual switch areas at the same time, which is not particularly limited herein.
In an embodiment, if it is determined that the hosts connected to the first virtual switching area are in an abnormal condition, the PCIE switching chip includes a virtual switching area where at least two connected hosts are in a normal working state, and the protection switching module is further configured to: reading priority information configured for a virtual switching area in a PCIE switching chip; and determining the virtual switching area with the highest priority from the virtual switching areas of the at least two connected hosts in the normal working state according to the priority information, and determining the virtual switching area with the highest priority as a second virtual switching area.
Wherein the priority information is used to indicate the priority of the virtual switch area as the standby virtual switch area. By determining the virtual switch area with the highest priority among the at least two virtual switch areas in the normal operating state based on the priority information as described above, it is possible to uniquely determine a second virtual switch area as a spare virtual switch area for a first virtual switch area.
In an embodiment of the present application, the PCIE switch chip further includes a first enable register, where the first enable register is connected to the protection switching module, and the first enable register is used to store a first enable signal, and the first enable signal is used to enable the protection switching module. After the protection switching module is enabled by the first enable signal, the protection switching module is turned on, and the first indication information in the first register can be read, so that the protection switching process is realized.
In a specific embodiment, the information stored in the first enable register is a one-bit binary code, and when the first enable register is set to 1, the information currently stored in the first enable register is a first enable signal, so that the protection switching module is enabled by the first enable signal, and the protection switching module is turned on; on the contrary, if the first enable register is set to 0, the protection switching module cannot be enabled.
Step 230, performing a write operation on the first register corresponding to the first virtual switch area, so as to delete the information indicating the downstream port in the first virtual switch area, which is stored in the first register corresponding to the first virtual switch area; and writing the first register corresponding to the second virtual switch area to add and store the information indicating the downstream port in the first virtual switch area into the first register corresponding to the second virtual switch area.
In the solution of the present application, the protection switching module is connected to the first register, and the protection switching module can perform read-write operation on the first register, so as to modify the first indication information stored in the first register.
As described above, the first indication information stored in the first register corresponding to the virtual switch area is used to indicate the port belonging to the located virtual switch area. If the information indicating the downstream port in the first virtual switch area is added to and stored in the first register corresponding to the second virtual switch area, it is equivalent to binding the downstream port originally belonging to the first virtual switch area with the second virtual switch area, so as to indicate the host in the second virtual switch area to provide service for the PCIE device suspended by the downstream port originally belonging to the first virtual switch area.
Similarly, if the information indicating the downstream port in the first virtual switch area, which is stored in the first register corresponding to the first virtual switch area, is deleted, it is equivalent to unbind the PCIE device originally hung on the downstream port of the first virtual switch area from the first virtual switch area after the write operation is performed on the first register corresponding to the first virtual switch area.
And step 250, after the write operation is completed, triggering a doorbell register corresponding to the second virtual exchange area to send interrupt information to a corresponding host.
And after the virtual switching area is triggered, the doorbell register sends interrupt information to the connected host, and the host connected with the doorbell register responds to the received interrupt information and enumerates the ports in the virtual switching area according to the first indication information in the first register of the virtual switching area.
It can be understood that, after the write operation is completed, the first indication information stored in the first register in the second virtual switch area is changed, so that, in the process of enumeration by a host connected to the second virtual switch area according to the first indication information stored in the first register, the port assigned to the second virtual switch area and indicated by the first indication information may be re-determined correspondingly.
And in the process of port enumeration by the host, correspondingly acquiring first indication information according to the first indication information in the first register in the second virtual exchange area to re-determine the downstream port belonging to the second virtual exchange area. Furthermore, after the enumeration is finished, the host in the second virtual switch area provides a service for the PCIE device that is suspended by the downstream port in the second virtual switch area, where the downstream port in the second virtual switch area includes the downstream port in the second virtual switch area before the write operation and the downstream port in the first virtual switch area before the write operation.
In the solution of the present application, whether a host connected to a virtual switch area is abnormal is determined based on an upstream heartbeat register set for an upstream port of each virtual switch area in a PCIE switch chip, and when the host connected to a virtual switch area is abnormal, a protection switching module performs a write operation on a first register corresponding to a first virtual switch area where the host connected to the virtual switch area is abnormal and a first register corresponding to a second virtual switch area serving as a standby host, so that a downstream port of the first virtual switch area before the write operation is transferred to the second virtual switch area. Correspondingly, after the host in the second virtual switching area enumerates according to the first indication information in the first register corresponding to the second virtual switching area after the write operation, the host in the second virtual switching area correspondingly learns the port belonging to the second virtual switching area, and the host in the second virtual switching area provides service for the PCIE device originally hung in the first virtual switching area, so that the protection switching is realized.
Moreover, in the scheme of the application, since the information is transmitted by setting the hardware physically connected with the first register, the upstream heartbeat register and the doorbell register in the PCIE switch chip, rather than by using a software mode, the transmitted information is not encoded or decoded, and the response speed block are high, so that the PCIE switch chip can be ensured to process efficiently in time when an abnormal condition occurs in the virtual switch area, and the timeliness and the rapidity of implementing the protection switching are ensured.
In an embodiment of the present application, the protection switching module includes a second register, and the second register is configured to store first indication information stored in the first register before the write operation is performed. Based on the second register, the protection switching module may also implement, through the flowchart shown in fig. 3, that when the virtual switching area returns to normal, the transferred downstream port originally belonging to the first virtual switching area is transferred to the first virtual switching area again. Specifically, as shown in fig. 3, the protection switching module is further configured to execute the following steps 310 to 340, which are specifically described as follows:
step 310, reading the second indication information in the upstream heartbeat register corresponding to the first virtual switching area again, and resetting the second indication information in the upstream heartbeat register corresponding to the virtual switching area to be the first state information according to the first setting period, where the first state information is used to indicate that the host connected to the corresponding virtual switching area is in a normal working state.
Because the host connected to the first virtual switching area resets the information of the upstream heartbeat register in the first virtual switching area according to the first set period, if the host connected to the first virtual switching area is still in an abnormal condition, that is, the host in the first virtual switching area or the link where the host is located is still abnormal, the host in the first virtual switching area cannot perform read-write operation on the corresponding upstream heartbeat register, that is, cannot reset the second indication information stored in the upstream heartbeat register corresponding to the first virtual switching area to the first state information; on the contrary, if the first virtual switching area recovers to the normal working state, the host connected to the first virtual switching area may perform read-write operation on the corresponding upstream heartbeat register, and reset the second indication information stored in the upstream heartbeat register to the first state information.
In an embodiment, in order to facilitate timely learning of the condition of each virtual switching area, the protection switching module reads second indication information stored in an upstream heartbeat register corresponding to each virtual switching area according to a second set period, and if the read second indication information is first state information, the protection switching module performs a write operation on the second indication information stored in the upstream heartbeat register corresponding to the virtual switching area, resets the second indication information to the second state information, and reads the second indication information stored in the upstream heartbeat register again according to the second set period, where the second state information is used to indicate that an abnormal condition occurs in a host connected to the corresponding virtual switching area, and a duration of the first set period does not exceed a duration of the second set period. Otherwise, if the second indication information read from the upstream heartbeat register is the second state information, the protection switching module does not perform write operation on the upstream heartbeat register.
The method is applied to a first virtual switching area, after a protection switching module resets second indication information in an upstream heartbeat register in the first virtual switching area to second state information, if a host connected to the first virtual switching area and/or a link where the host connected to the first virtual switching area is still abnormal, the host connected to the first virtual switching area cannot reset the second indication information in the corresponding upstream heartbeat register to the first state information according to a first set period, and the second indication information in the upstream heartbeat register in the first virtual switching area is still the second state information. Correspondingly, when the protection switching module reads the second state information stored in the upstream heartbeat register in the first virtual switching area next time, it may be correspondingly determined that the host connected to the first virtual switching area is still in an abnormal condition.
On the contrary, if the first virtual switching area is recovered to be normal after the protection switching module resets the second indication information in the upstream heartbeat register in the first virtual switching area to the second state information, the host in the first virtual switching area may reset the second indication information in the corresponding upstream heartbeat register to the first state information according to the first set period. Therefore, when the protection switching module reads the first state information stored in the upstream heartbeat register in the first virtual switching area next time, it can be correspondingly determined that the first virtual switching area recovers to a normal working state.
In a specific embodiment, in order to enable the protection switching module to trigger protection switching on a virtual switching area in time when determining that the virtual switching area is abnormal, the protection switching module includes a timer configured for each upstream heartbeat register, and the timer is used for counting down.
For convenience of description, it is assumed that the second indication information stored in the upstream heartbeat register is a one-bit binary code, and the first state information is set to be 1, and the second state information is set to be 0. And further setting, after the protection switching module reads the second indication information stored in the upstream heartbeat register corresponding to the virtual switching area each time, if the read second indication information is 1, while clearing the value of the upstream heartbeat register to 0, setting the timer corresponding to the upstream heartbeat register to the maximum value, and starting countdown.
The protection switching module is applied to a first virtual switching area, if a host connected with the first virtual switching area is in an abnormal state in a countdown period, the protection switching module always reads that the value of an upstream heartbeat register corresponding to the first virtual switching area is 0 in a certain time period, and if the value of the upstream heartbeat register corresponding to the first virtual switching area is still 0 when a timer counts down to 0, the protection switching module starts protection switching on the first virtual switching area, namely, a downstream port of the first virtual switching area is moved to a second virtual switching area and subsequent steps.
Step 320, if the second indication information read again is the first status information, reading the first information and the second information from the second register, where the first information is the first indication information stored in the first register corresponding to the first virtual switch area before the write operation, and the second information is the first indication information stored in the first register corresponding to the second virtual switch area before the write operation.
As described above, if the second indication information read again from the upstream heartbeat register corresponding to the first virtual switch area is the first state information, it indicates that the first virtual switch area is recovered to be normal.
Step 330, resetting the first indication information stored in the first register corresponding to the first virtual switch area to the first information and resetting the first indication information stored in the first register corresponding to the second virtual switch area to the second information.
After the first virtual switch area is recovered to be normal, the PCIE device originally suspended in the first virtual switch area may not be served by the host in the second virtual switch area, but may be served by the host in the first virtual switch area again.
Therefore, in order to realize the purpose of transferring the PCIE device originally hung in the first virtual switch area to the first virtual switch area again, the first indication information in the first register corresponding to the first virtual switch area is reset to the first information, and the first indication information in the first register corresponding to the second virtual switch area is reset to the second information, so that the downstream port originally belonging to the first virtual switch area is bound with the first virtual switch again, and the downstream port originally belonging to the first virtual switch area is unbound with the second virtual switch area. The re-transfer of the downstream port originally attributed to the first virtual switch zone, which was transferred to the second virtual switch zone, to the first virtual switch zone in step 230 is achieved.
Step 340, triggering the doorbell register corresponding to the first virtual switching area to send the interrupt information to the corresponding host, and triggering the doorbell register corresponding to the second virtual switching area to send the interrupt information to the corresponding host.
After the trigger is triggered, the doorbell register corresponding to the first virtual switching area sends interrupt information to the connected host, and the doorbell register corresponding to the second virtual switching area sends interrupt information to the connected host, so that the host connected to the first virtual switching area enumerates the port belonging to the first virtual switching area according to the received interrupt information, the host connected to the second virtual switching area enumerates the port belonging to the second virtual switching area according to the received interrupt information, and after the enumeration is completed, each host in the first virtual switching area and the second virtual switching area provides service for the PCIE equipment hung up by itself.
In some embodiments of the present application, the PCIE switch chip further includes a port reset register, before the protection switching module performs a write operation on the first register, the protection switching module performs a write operation on the port reset register of the upstream port in the virtual switch area where the first register to be subjected to the write operation is located, generates a reset signal, and sends the generated reset signal to the upstream port of the corresponding virtual switch area, after the upstream port in the virtual switch area receives the reset signal, the virtual switch area where the upstream port is located is reset, and the traffic in the virtual switch area is cleared.
In some embodiments of the present application, a first interface is disposed on the PCIE switch chip, the first interface may be used to externally connect an electrical programmable read-only memory, and a register inside the PCIE switch chip may be initialized and loaded through the programmable read-only memory externally connected to the first interface. The registers inside the PCIE switch chip include, but are not limited to, the first register, the upstream heartbeat register, the doorbell register, the second register, the third register, and the like listed above.
In some embodiments of the present application, the PCIE switch chip further includes a fourth register, where before resetting the upstream port in the virtual switch area, the fourth register sends a load prohibition signal to the first interface, and the load prohibition signal is used to instruct the first interface to prohibit information loading through the external programmable read only memory. Correspondingly, when the information stored in the fourth register is a signal allowing loading, the first interface is allowed to load the information from the external programmable read-only memory. The first interface may include an EEPROM (Electrically Erasable Programmable read only memory) interface, a pin interface, and an I2C/SMBus slave interface, which is not limited herein. Further, after the protection switching is completed, the fourth register sends a load start signal to the first interface, so as to allow information loading through an external programmable read only memory.
In some embodiments of the present application, the PCIE switch chip further includes a crossbar module, and the crossbar module is configured to control and connect ports in the same virtual switch area in the PCIE switch chip, so that the ports in the same virtual switch area may communicate data flows with each other, and the ports belonging to different virtual switch areas do not communicate data flows with each other.
The first register, the second register, the third register, the first enabling register, the second enabling register, and the port reset register may all be set to a certain port of the PCIE switch chip, and be located in the configuration space of the port, or may be designed to several ports, and be located in the configuration spaces of the corresponding ports, respectively. These registers are sticky registers and are not affected by a hot reset, and their values can only be reset by a cold reset.
The following description is directed to a PCIE switch core of the present application in combination with a specific embodimentImplementation process of slice and protection switching Detailed description of the invention。
Fig. 4 is a block diagram of a PCIE switch chip according to an embodiment, and fig. 4 shows modules shared by each virtual switch area.
As shown in fig. 4, the module shared by each virtual switch area of the PCIE switch chip includes: the protection switching module, the first enabling register, the port reset register, the fourth register, the second enabling register, the interface module and the cross switch module. The first enabling register, the port reset register, the fourth register and the second enabling register are all connected with the protection switching module. The protection switching module comprises a timer and a second register.
And the second enable register is used for defining virtual switch areas in the PCIE switch chip, wherein each virtual switch area corresponds to one enable bit of the second enable register. When an enable bit is valid, enabling the virtual switching area corresponding to the enable bit; otherwise, when an enable bit is invalid, the virtual switch area corresponding to the enable bit is not enabled. In one embodiment, it may be set that: when an enable bit is 1, enabling the virtual switch area corresponding to the enable bit, namely the virtual switch area exists; when an enable bit is 0, the virtual swap area corresponding to the enable bit is not enabled, i.e., the virtual swap area does not exist.
The number of bits of the port reset register is the same as the number of ports in the PCIE switch chip, one bit in the port reset register corresponds to one port in the PCIE switch chip, and one bit in the port reset register is used to generate a reset signal of one port.
The bit width of the fourth register is 1, and when the fourth register is 1, initializing operation of an EEPROM (electrically erasable programmable read-only memory) externally connected with the PCIE switching chip on the PCIE switching chip is forbidden; when the fourth register is set to 0, the PCIE switch chip can perform a loading operation on the fourth register through the EEPROM after being reset.
The first register, the heartbeat register, the doorbell register and the third register are all connected with the protection switching module. Each port is provided with a heartbeat register, and the heartbeat register corresponding to the upstream port is called an upstream heartbeat register.
It is understood that the heartbeat register set for a port is connected to the corresponding port, and in fig. 4, because there are many ports, the connection relationship between each module/register (e.g., doorbell register, etc.) and the port is not shown.
The heartbeat register is located in the register space configured by each port and receives the read-write operation of the protection switching module and the host in the virtual switching area to which the port belongs.
The operation of the protection switching module is controlled by a first enable register, which is a single bit and can set: when the first enable register is set to 1, the protection switching module enters an enable state.
In a specific embodiment, for convenience, the first register, the second enable register, the port reset register, the fourth register, and the first enable register are arranged at a certain port, and except that the protection switching module can perform read/write operations on these registers, the host corresponding to the port where these registers are located can also perform read/write operations on these registers. In this embodiment, these registers are sticky registers, not affected by a hot reset, and only a cold reset can reset their values.
In this embodiment, as shown in fig. 4, the interface module includes an EEPROM interface sub-module, a pin interface sub-module, and an I2C/SMBus slave interface sub-module. The EEPROM interface submodule is used for connecting with an external EEPROM chip, and when the EEPROM interface submodule is powered on, the EEPROM interface submodule reads data stored by the EEPROM chip and initializes the first register, the third register, the first enabling register, the second enabling register and some port registers. The pin interface sub-module is connected with all configuration binding pins of the chip, so that the PCIE switching chip can set the working state of the PCIE switching chip by configuring the input state of the binding pins. When the PCIE switch chip is powered on, the registers (e.g., the first register, the third register, the first enable register, the second enable register, and the like) inside the PCIE switch chip are configured by collecting the input state of the configuration binding pin of the PCIE switch chip, so that the protection switching module is enabled, and the operation of the protection switching module is started. The input state of the configuration binding pin can be a high level, a low level or a high resistance state, and different pin state combinations correspond to different configuration results, namely, different virtual switch partitions.
The I2C/SMBus slave interface sub-module is used for connecting external I2C/SMBus master control equipment, and the registers in the PCIE switching chip can be initialized and configured through the I2C/SMBus master control equipment.
For a PCIE switch chip supporting virtual switch, if there are M ports in the port configuration system, where M is a natural number not less than 3. The number of virtual switching areas supported by most of one PCIE switching chip is less than the number of actual ports of the PCIE switching chip, and one PCIE switching chip supporting n virtual switching areas must have an n-bit second enabling register VSEnable, n first registers VS0 Port-VSnPort and n third registers VS0 Uport-VSnPort. It should be noted that, for a PCIE switch chip supporting virtual switch, n is a positive integer, and once designed, the value of n is a fixed value and cannot be changed.
The PCIE switch chip shown in fig. 4 includes 12 PCIE ports, which are ports P0 to P11, and can be divided into 6 virtual switch areas at most. Therefore, in the PCIE switch chip, the configured second enable register VSEnable has 6 bits, and one enable bit corresponds to one virtual switch area; because the virtual switching chip can be divided into 6 virtual switching areas at most, 6 first registers VS0 Port-VS 5Uport are correspondingly arranged in the PCIE switching chip, the first registers are 12 bits, and one bit corresponds to one Port. The PCIE switch chip is provided with 6 third registers, which are VS0 uplink to VS5 uplink, and each third register has 4 bits.
Fig. 5 is a schematic diagram illustrating a division of a virtual switch area in the PCIE switch chip shown in fig. 4. Assume that the first register, the third register, the second enable register, the port reset register, the fourth register, and the first enable register are all routed to port P0.
After the power is on, the first register, the third register, the first enabling register and the second enabling register are configured through configuring the input state of the binding pin, an EEPROM chip externally connected with the PCIE switching chip or I2C/SMBus main control equipment, and the obtained configuration values are as follows:
a second enable register: VSEnable [5 ] =000111;
6 first registers:
VS0Port[11:0]＝0000 0001 1001；
VS1Port[11:0]＝0000 1110 0010；
VS2Port[11:0]＝1111 0000 0100；
VS3Port[11:0]＝0000 0000 0000；
VS4Port[11:0]＝0000 0000 0000；
VS5Port[11:0]＝0000 0000 0000；
6 third registers:
VS0Uport[3:0]＝0000；
VS1Uport[3:0]＝0001；
VS2Uport[3:0]＝0010；
VS3Uport[3:0]＝0000；
VS4Uport[3:0]＝0000；
VS5Uport[3:0]＝0000。
through the above configuration, the PCIE switch chip shown in fig. 4 is divided into 3 virtual switch areas VS0, VS1, and VS2, where VS0 includes ports: p0, P3 and P4, VS1 comprises P1, P5, P6, P7, VS2 comprises P2, P8, P9, P10, P11, as shown in fig. 5.
The following describes the implementation process of protection switching by taking fig. 5 as an example. As shown in fig. 5, the upstream ports corresponding to the virtual switch areas VS0, VS1 and VS2 are P0, P1 and P2, respectively, and the port Heartbeat registers corresponding to these upstream ports are Heartbeat registers, respectively, heartbeat0, heartbeat1 and Heartbeat2. After the PCIE switching chip is powered on, the values of the PCIE switching chip are set to 1 by an external EEPROM chip, a configuration binding pin or an I2C/SMBus main control device or a host 0 of VS0, and the first enabling register is also set to 1 by the external EEPROM chip or the I2C/SMBus main control device, the configuration binding pin or the host 0 of VS0. The hosts corresponding to VS0, VS1 and VS2 are host 0, host 1 and host 2, respectively.
The first enable register is set to be 1, the protection switching module is started, the first enable register reads the values of the first register, the third register and the second enable register from a port 0, and then timeout timers VS0-timer-out, VS1-timer-out and VS2-timer-out of VS0, VS1 and VS2 are preset to be the maximum value 8000 respectively, and the first enable register, the third register and the second enable register are started to time. The countdown timer decrements 1 every microsecond.
The protection switching enable module reads the values of Heartbeat registers Heartbeat0, heartbeat1, heartbeat2 every 4 ms, and clears them to 0 after reading. And if the value of any read heartbeat register is 1, presetting the timer corresponding to the heartbeat register as a maximum value, otherwise, if the value of any read heartbeat register is 0, not presetting the timer corresponding to the heartbeat register.
Under normal conditions, if the host 0, the host 1 or the host 2 operates normally, the values of Heartbeat0, heartbeat1 and Heartbeat2 are set to 1 every 4 milliseconds. If the host 0 fails or the upstream port link of the port P0 fails for some reason, if the failure is not repaired in time, the value of the Heartbeat register Heartbeat0 read by the protection switching module and clearing 0 is not reset to 1 by the host 0, after at most 8 milliseconds, the timer vs0-timer-out will count down from 8000 to 0, and when the timer vs0-timer-out jumps from 1 to 0, protection switching is triggered.
The implementation of protection switching includes the following procedures:
firstly, when protection switching occurs, the protection switching module queries the virtual switching which is still in normal work at present, and determines a second virtual switching area serving as a standby for the abnormal virtual switching area VS0 according to the priority of VS0> VS1> VS2> VS3> VS4> VS 5. Since the priority of VS1 is higher than that of VS2, the protection switching module determines the virtual switching area VS1 as the second virtual switching area.
Secondly, if the PCIE switching chip has a plug-in EEPROM chip, the fourth register at the port P0 is set to be 1, so that the EEPROM loading caused by all the hot resets is forbidden.
Then, the protection switching module resets the upstream Port of the virtual switching area VS0 by setting the Port Reset register Reset-Port [0] to 1 and then clearing 0, resets the abnormal virtual switching area VS0, and clears all the traffic of the virtual switching area VS0.
Next, the protection switching module reads the value 0000 0001 of the first register VS0Port corresponding to the abnormal virtual switching area (VS 0) and the value of the first register VS1Port corresponding to the second virtual switching area (VS 1), stores the value of the first register VS0Port of the virtual switching area VS0 in the second register VS0Port _ former corresponding to the protection switching module, and stores the value of the first register VS1Port corresponding to the second virtual switching area in the second register VS1Port _ former corresponding to the protection switching module. The protection switching module performs write operation on the values of the first register VS0Port and the first register VS1Port, and sets the value of the first register VS0Port to 0000 0000 0001, so that downstream ports P3 and P4 needing to be moved are deleted from the virtual switching area VS 0; the addition of new ports P3 and P4 in the virtual switch area VS1 is realized by setting the value of the first register VS1Port to 0000 1111 1010.
Finally, the protection switching module controls to set a doorbell register of an upstream port of the first virtual switching area VS1 to 1, trigger the upstream port to send an interrupt message to a connected host, the host responds to the interrupt message, clears the value of the doorbell register to 0, and at the same time, re-enumerates the first virtual switching area VS1 according to a first register corresponding to the first virtual register after the write operation. After the enumeration is completed, the host 1 starts to work normally, and the PCIE endpoints suspended on the ports P3 and P4 receive the service of the host 1.
After the protection switching is implemented, the downstream ports in each virtual switching area of the PCIE switching chip take over as shown in fig. 6, and after the protection switching is implemented, the downstream ports P3 and P4 originally belonging to the virtual switching area VS0 are transferred to the virtual switching area VS1. After the protection-to-replacement is completed, the protection-to-replacement module sets the fourth register at the port P0 to be 0, and starts all the EEPROM loads caused by the hot reset.
If a period of time elapses, the host 0 fails or the link failure of the upstream port P0 of the virtual switch area VS0 is repaired, the host 0 can perform read/write operations on the configuration register of the upstream port P0, and the host 0 sets the Heartbeat register Heartbeat0 to 1.
Because the protection switching module reads the three Heartbeat registers according to the set period, after finding that the Heartbeat register Heartbeat0 is set to be 1, presetting the timer vs0-timer-out to be the maximum value 8000, and simultaneously starting the protection switching to realize the following recovery process:
setting the fourth register at port P0 to 1 inhibits all EEPROM loads from a warm reset.
The protection switching module resets the upstream Port of the virtual switching area VS1 by setting the Reset-Port [1] of the Port Reset register to 1 and then clearing 0, the virtual switching VS1 is Reset, and all the flow of the virtual switching VS1 is cleared.
Then, the protection switching module prohibits the EEPROM of the upstream port where the port 0 is located from loading the control register clear 0.
Then, the protection switching module reads the value of a VS1Port _ provider of a second register corresponding to the virtual switching area VS1, and writes the value into a VS1Port of a first register corresponding to the virtual switching area VS1, so as to delete the ports P3 and P4 from the virtual switching area VS 1; and reading a value of a second register VS0Port _ former corresponding to the virtual switch area VS0, and writing the value into a first register VS0Port corresponding to the virtual switch area VS0, so as to restore the ports P3 and P4 originally belonging to the virtual switch area VS0.
Secondly, the protection switching module sets the doorbell registers of the upstream ports of the virtual switching areas VS0 and VS1 to 1, triggers the virtual switching area VS0 to send interrupt information to the connected host 0, and triggers the virtual switching area VS1 to send interrupt information to the connected host 1. And responding to the interrupt information by the host 0 and the host 1, clearing 0 of the value of the corresponding doorbell register, and then respectively enumerating the virtual switch areas VS0 and VS1 again.
After enumeration is completed, the PCIE endpoints hanging down on ports P3 and P4 resume receiving the service of host 0. Host 1 continues to serve the PCIE endpoints hanging down on ports P5, P6, and P7, and the PCIE switch chip resumes the state shown in fig. 5.
After the operation is completed, the protection-to-replacement module sets the fourth register at the port P0 to be 0, and starts all the EEPROM loads caused by the hot reset.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the application. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains.
It will be understood that the present application is not limited to the precise arrangements that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (9)

1. A PCIE switching chip is characterized in that the PCIE switching chip comprises a protection switching module and at least two divided virtual switching areas, and ports in the PCIE switching chip are divided into each virtual switching area;
the PCIE switching chip divides the PCIE switching chip into at least two virtual switching areas through a first register, a third register and a second enabling register in the PCIE switching chip, and one virtual switching area is specified through the first register, the third register and the second enabling register; wherein the third register is used for indicating a port of the associated virtual switch area as an upstream port of the virtual switch area; the second enabling register is used for enabling the virtual switching area associated with the first register and the third register to work; each port of the PCIE switching chip comprises a heartbeat register and a doorbell register, the heartbeat register corresponding to the upstream port is called an upstream heartbeat register, and the doorbell register corresponding to the upstream port is called an upstream doorbell register; a first register, configured to store first indication information, where the first indication information is used to indicate ports included in an associated virtual switch area, where the ports include an upstream port and a downstream port, the upstream port is used to connect to a host, and the downstream port is used to connect to a PCIE device;
the upstream heartbeat register is connected with the upstream port and used for storing second indication information, and the second indication information is used for indicating whether the host corresponding to the associated virtual switching area has abnormal conditions or not;
the doorbell register is used for sending interrupt information to the host connected with the upstream port, and the interrupt information is used for indicating the connected host to enumerate the ports in the associated virtual switching area according to the first indication information stored in the corresponding first register;
the protection switching module can perform read-write operation on the first register, the third register, the second enabling register, the heartbeat register and the doorbell register;
the protection switching module is configured to:
determining a first virtual exchange area and a second virtual exchange area serving as a spare area of the connected host in case of abnormal conditions by reading second indication information in an upstream heartbeat register corresponding to each virtual exchange area;
writing a first register associated with the first virtual switch area to delete the information which is stored in the first register corresponding to the first virtual switch area and indicates the downstream port in the first virtual switch area; performing write operation on a first register corresponding to the second virtual switching area to add and store information indicating a downstream port in the first virtual switching area into the first register corresponding to the second virtual switching area;
after the write operation is finished, triggering a doorbell register corresponding to the second virtual exchange area to send interrupt information to a corresponding host;
the protection switching module comprises a second register, and the second register is used for storing first indication information stored in the first register before write operation;
the protection switching module is further configured to:
reading second indication information in the upstream heartbeat register corresponding to the first virtual switching area again, resetting the second indication information in the upstream heartbeat register corresponding to the virtual switching area to first state information according to a first set period by a host connected to the virtual switching area, wherein the first state information is used for indicating that the host corresponding to the corresponding virtual switching area is in a normal working state;
if the second indication information read again is first state information, reading first information and second information from the second register, wherein the first information is first indication information stored in a first register corresponding to the first virtual switching area before write operation is performed, and the second information is first indication information stored in a first register corresponding to the second virtual switching area before write operation is performed;
resetting first indication information stored in a first register corresponding to the first virtual switching area to the first information and resetting first indication information stored in a first register corresponding to the second virtual switching area to the second information;
triggering the doorbell register corresponding to the first virtual switching area to send interrupt information to the corresponding host, and triggering the doorbell register corresponding to the second virtual switching area to send interrupt information to the corresponding host.
2. The PCIE switch chip of claim 1, wherein after reading the second indication information stored in the upstream heartbeat register corresponding to each virtual switch area, if the read second indication information is the first state information, the protection switching module resets the second indication information stored in the upstream heartbeat register corresponding to the virtual switch area to the second state information, and reads the second indication information stored in the upstream heartbeat register again according to a second set period, where the second state information is used to indicate that the host corresponding to the corresponding virtual switch area is abnormal, and the duration of the first set period does not exceed the duration of the second set period.
3. The PCIE switch chip of claim 1, wherein the virtual switch area further comprises a third register, the third register is configured to store fourth indication information, and the fourth indication information is configured to indicate an upstream port in the virtual switch area where the virtual switch area is located.
4. The PCIE switch chip of claim 1, wherein the PCIE switch chip further comprises a first enable register, the first enable register is connected to the protection switching module, the first enable register is used to store a first enable signal, and the first enable signal is used to enable the protection switching module.
5. The PCIE switch chip of claim 1, wherein when it is determined that the host corresponding to the first virtual switch area is in an abnormal condition, the PCIE switch chip includes at least one virtual switch area where the connected host is in a normal operating state, and when only one connected host is in a virtual switch area in a normal operating state, the virtual switch area is determined as the second virtual switch area;
when there are two or more connected hosts in a virtual switching area in a normal operating state, the protection switching module is further configured to: reading priority information configured for a virtual switching area in the PCIE switching chip;
and determining the virtual switching area with the highest priority in the virtual switching areas of the two or more connected hosts in the normal working state according to the priority information, and determining the virtual switching area with the highest priority as the second virtual switching area.
6. The PCIE switch chip of claim 1, wherein the PCIE switch chip further comprises a crossbar module, and the crossbar module is configured to control and connect ports in the same virtual switch area in the PCIE switch chip, so that the ports in the same virtual switch area are interconnected by a data stream.
7. The PCIE switch chip of claim 1, wherein the PCIE switch chip further comprises a port reset register, and before the protection switching module performs write operation on the first register, the protection switching module performs write operation on a port reset register corresponding to an upstream port in a virtual switch area where the first register to be subjected to write operation is located, so as to generate a reset signal.
8. The PCIE switch chip of claim 1, wherein a first interface is disposed on the PCIE switch chip, the first interface is used for externally connecting an electrically programmable read only memory, and a register inside the PCIE switch chip performs initialization loading through the programmable read only memory externally connected to the first interface.
9. The PCIE switch chip of claim 8, wherein the PCIE switch chip further comprises a fourth register, before an upstream port in the virtual switch area is reset, the fourth register sends a load prohibition signal to the first interface, and the load prohibition signal is used to instruct the first interface to prohibit information loading through an external programmable read only memory.
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