CN111092013B - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN111092013B CN111092013B CN201811237104.9A CN201811237104A CN111092013B CN 111092013 B CN111092013 B CN 111092013B CN 201811237104 A CN201811237104 A CN 201811237104A CN 111092013 B CN111092013 B CN 111092013B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Abstract
The invention discloses a method for forming a semiconductor device, which comprises the following steps: providing a substrate and a discrete first sacrificial structure formed over the substrate; forming a side wall covering the side wall of the first sacrificial structure; forming a transition material layer between the side walls; removing the side wall to form a first groove; etching part of the transition material layer to form a second groove and a second sacrificial structure separated by the second groove; forming a dielectric layer in the first groove and the second groove; and etching the first sacrificial structure and the second sacrificial structure by taking the dielectric layer as a mask to form a groove pattern. The process can better control the accuracy of pattern formation, and further forms patterns with smaller size and more dense and regular structure.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for forming a semiconductor device.
Background
In a semiconductor manufacturing process, a mask pattern is typically transferred onto a substrate using a photolithography process. As semiconductor device dimensions continue to decrease, lithographic critical dimensions are approaching or even exceeding the physical limits of lithography, thereby presenting more serious challenges to lithography.
At present, in a process of forming a small line segment or a small-size pattern, a mask layer is formed, then etching is performed, and the steps are sequentially performed. However, the size of the formed pattern may vary and the shape of the pattern may be irregular, affecting the performance of the semiconductor device.
Therefore, a method for forming a semiconductor device with a smaller size and a regular pattern structure is needed.
Disclosure of Invention
The embodiment of the invention discloses a method for forming a semiconductor device, which adopts a two-step process, firstly, a raised pattern is formed step by step, and then the raised pattern is transferred into a groove to form a final groove pattern.
The invention discloses a method for forming a semiconductor device, which comprises the following steps: providing a substrate and a discrete first sacrificial structure formed over the substrate; forming a side wall covering the side wall of the first sacrificial structure; forming a transition material layer between the side walls; removing the side wall to form a first groove; etching part of the transition material layer to form a second groove and a second sacrificial structure separated by the second groove; forming a dielectric layer in the first groove and the second groove; and etching the first sacrificial structure and the second sacrificial structure by taking the dielectric layer as a mask to form a groove pattern.
According to one aspect of the invention, after the first recess is formed, the transition material layer and the first sacrificial structure are separated by the first recess.
According to one aspect of the invention, each second sacrificial structure is formed between adjacent first sacrificial structures.
According to one aspect of the invention, there is also provided an etch stop layer between the substrate and the first sacrificial structure.
According to one aspect of the invention, after the groove pattern is formed by etching, the etching process is continuously executed to etch the etching stop layer and the substrate so as to form a target pattern in the substrate.
According to an aspect of the present invention, in the etching process for forming the groove pattern, the etching process has an etching rate ratio γ of 10. ltoreq. γ.ltoreq.15 to the first sacrificial structure and the second sacrificial structure and to the etch stop layer.
According to one aspect of the invention, the process steps of forming the side wall include: forming a side wall material layer covering the side wall and the top of the first sacrificial structure and covering the top surface of the etching stop layer between the adjacent first sacrificial structures; and etching back the side wall material layer, and only reserving the side wall material layer formed on the side wall of the first sacrificial structure, namely the side wall.
According to one aspect of the invention, the process for forming the side wall material layer comprises an atomic layer deposition process.
According to one aspect of the invention, the process steps for forming the transition material layer include: forming a transition material which is filled between the side walls and covers the tops of the side walls and the top of the first sacrificial structure; and removing the transition materials on the tops of the side walls and the top of the first sacrificial structure, and only keeping the transition materials formed between the side walls, namely the transition material layers.
According to one aspect of the invention, the process of forming the transition material comprises a fluid chemical vapor deposition process.
According to one aspect of the invention, after forming the transition material, before removing a portion of the transition material, the method further comprises subjecting the transition material to an annealing process.
According to one aspect of the invention, the conditions of the annealing process include: the annealing temperature range is 400-500 ℃, and the annealing time range is 2-4 h.
According to one aspect of the invention, the process for removing the transition material on top of the sidewall and on top of the first sacrificial structure comprises a dry etching process, a wet etching process or a chemical mechanical planarization process.
According to one aspect of the invention, the process steps of forming the second sacrificial structure and the second recess comprise: forming an intermediate material layer filling the first groove; forming a mask layer on the tops of the intermediate material layer, the first sacrificial structure and the transition material layer; and etching part of the transition material layer by taking the mask layer as a mask so as to form a second sacrificial structure and a second groove.
According to one aspect of the invention, after forming the second sacrificial structure, further comprising removing the intermediate material layer, after removing the intermediate material layer, the first sacrificial structure and the second sacrificial structure being separated by the first recess.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the invention, side walls covering the side walls of the first sacrificial structures are formed; forming a transition material layer between the side walls; and removing the side wall to form a first groove. And removing the side wall positioned on the side wall of the first sacrificial structure to form a first groove, and reserving a part of the target groove pattern in the raised first sacrificial structure pattern. Next, portions of the transition material layer are etched to form a second recess and a second sacrificial structure separated by the second recess. And forming the second sacrificial structures, wherein the raised pattern structures with smaller sizes can be formed between the adjacent first sacrificial structures again, and the first sacrificial structures and the second sacrificial structures are closer to each other, so that a more regular dense pattern is formed. At the same time, the target groove pattern is entirely present in the raised pattern. In addition, a dielectric layer is formed in the first groove and the second groove, and the first sacrificial structure and the second sacrificial structure are etched by taking the dielectric layer as a mask to form a groove pattern. This one step process can transfer the raised pattern into the grooves to form the final target groove pattern. The two-step process for forming the convex pattern can gradually replace a target groove pattern which needs to be formed originally by the convex sacrificial structure pattern, replace a convex area originally by the groove, and finally realize accurate transfer of the pattern after conversion.
Further, the process of forming the transition material includes a fluid chemical vapor deposition process. By utilizing the fluid chemical vapor deposition process, the transition material can be guaranteed to be compact in structure, no gap is formed inside the transition material, and the formed structure can be guaranteed to be regular.
Drawings
Fig. 1 a-6 b are schematic structural views of a method for forming a semiconductor device according to an embodiment of the invention.
Detailed Description
As described above, the prior art has problems of irregular pattern structure, inaccurate size, easy change of pattern shape, etc. when forming patterns having a small size.
The research finds that the reasons causing the problems are as follows: in the process of forming a mask and etching for many times, the mask layer patterns are prone to being misaligned, and finally the pattern structure is changed.
In order to solve the problem, the invention provides a method for forming a semiconductor device, which utilizes a two-step process to replace the pattern which needs to form a groove originally by a raised pattern so as to ensure the accurate transfer of a pattern structure.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in these embodiments should not be construed as limiting the scope of the present invention unless it is specifically stated otherwise.
Further, it will be appreciated that the dimensions of the various elements shown in the figures are not necessarily drawn to scale relative to actual dimensions, for example, the thickness or width of some layers may be exaggerated relative to other layers for ease of illustration.
The following description of the exemplary embodiment(s) is merely illustrative and is not intended to limit the invention, its application, or uses in any way.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification as applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the following description of the figures.
In each figure of the embodiment of the invention, a diagram b is a top view of a structure in the process of forming a semiconductor device, and a diagram a is a schematic diagram of a longitudinal section structure of the diagram b taken along a section line of the A-A' direction. And will not be described in detail hereinafter.
Referring to fig. 1a and 1b, an etch stop layer 110 and a discrete first sacrificial structure 121 are formed on a substrate 100.
The substrate 100 serves as a base on which a semiconductor device is formed.
In the embodiment of the present invention, the base 100 may be a semiconductor substrate. The material of the substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like. In the embodiment of the present invention, the material of the substrate 100 is polysilicon. Other structures may be included in the substrate 100, such as: the structures of metal plugs, metal connection layers, dielectric layers, etc., or other semiconductor devices including these structures, are not limited in this respect.
In another embodiment of the present invention, the substrate 100 may also be a metal material layer, such as a copper layer, an aluminum layer, a tungsten layer, etc., and is not particularly limited herein.
Embodiments of the present invention also include forming an etch stop layer 110. The etch stop layer 110 serves to stop the subsequent etching there to avoid over-etching and damaging the structure of the substrate 100. Accordingly, the etch stop layer 110 is formed on the top surface of the substrate 100.
The material forming the etch stop layer 110 includes one or a combination of TiN and TaN. Specifically, in the embodiment of the present invention, the material of the etch stop layer 110 is TiN. In another embodiment of the present invention, the material of the etch stop layer 110 is a combination of TiN and TaN.
The discrete first sacrificial structures 121 are structures having a specific pattern of protrusions (here, protrusions are in contrast to recesses) that subsequently need to be accurately transferred into the substrate 100. In an embodiment of the present invention, a discrete first sacrificial structure 121 is formed over the etch stop layer 110. Obviously, the process of forming the first sacrificial structure 121 is a conventional etching process, that is, a mask layer is formed on a material layer on which the first sacrificial structure 121 is to be formed, and then the mask layer is patterned and then etched.
In fact, the target groove pattern will be more dense. Therefore, the position of the target pattern relatively far away can be selected as the region for forming the first sacrificial structures 121, and then the second sacrificial structures located between the first sacrificial structures 121 can be formed through the second step process (hereinafter, for convenience of description, the first sacrificial structures and the second sacrificial structures are collectively referred to as sacrificial structures), so that the overall pattern is more dense and regular.
The material of the first sacrificial structure 121 comprises conventional poly-Si or SiO2And the like. Specifically, in the embodiment of the present invention, the material of the first sacrificial structure 121 is SiO2。
Referring to fig. 2a and 2b, sidewalls 130 are formed on sidewalls of the first sacrificial structure 121, and a transition material layer 122 is formed between the sidewalls 130.
The formation of the sidewalls 130 provides for the subsequent transfer of the pattern. In the embodiment of the present invention, the sidewall spacers 130 are formed on the sidewalls of the first sacrificial structure 121.
In the embodiment of the present invention, the process for forming the sidewall spacers 130 includes: first, a sidewall material layer (not shown) covering the sidewalls and the tops of the first sacrificial structures 121 and the top surfaces of the etch stop layers 110 between adjacent first sacrificial structures 121 is formed, and then the sidewall material layer (not shown) located at the tops of the first sacrificial structures 121 and the top surfaces of the etch stop layers 110 between adjacent first sacrificial structures 121 is etched back to remove, and only the sidewall material layer (i.e., the sidewall 130) formed on the sidewalls of the first sacrificial structures 121 is remained.
In the embodiment of the invention, the process for forming the side wall material layer comprises an atomic layer deposition process (ALD). The side wall 130 formed by the ALD process has a compact structure and accurate size, and can realize accurate transfer of subsequent patterns.
In other embodiments of the present invention, the sidewall spacer 130 may also be directly formed on the sidewall of the first sacrificial structure 121, which is not limited herein.
The material for forming the side wall material layer comprises SiNxAnd SiON, or a combination of one or more of them. Specifically, in the embodiment of the present invention, the material of the sidewall material layer is SiN. In another embodiment of the present invention, the material of the sidewall spacer material layer is a combination of SiN and SiON. Obviously, the material of the side wall 130 and the material of the side wall material layer are the same.
Please refer to fig. 2b, in an embodiment of the invention, sidewalls 130 are formed on upper and lower sidewalls of the first sacrificial structure 121 in fig. 2 b. In other embodiments of the invention, the sidewalls 130 may also be formed on left and right sidewalls of the first sacrificial structure 121, or on sidewalls around the first sacrificial structure 121, which is not limited herein.
The formation of the transition material layer 122 provides for the subsequent formation of a more finely dimensioned pattern.
The transition material layer 122 is formed between the side walls 130. The process steps for forming the transition material layer 122 include: first, a transition material (not shown) is formed to fill between the sidewall spacers 130 and cover the top of the sidewall spacers 130 and the top of the first sacrificial structure 121, and then the transition material on the top of the sidewall spacers 130 and the top of the first sacrificial structure 121 is removed, and only the transition material formed between the sidewall spacers 130, i.e., the transition material layer 122, remains.
Specifically, in the embodiment of the present invention, the process of forming the transition material is a Flow Chemical Vapor Deposition (FCVD) process. The FCVD process can better fill the transition material between the sidewalls 130, reduce the generation of internal voids, improve the strength of the finally formed transition material layer 122, and ensure the accuracy of the dimensions.
It should be noted that, in other embodiments of the present invention, the transition material may also be formed by other processes, such as a spin-on process, other deposition processes, or a growth process, and the like, which are not limited in this respect.
In the embodiment of the invention, because the transition material is formed by the FCVD process, before the subsequent removal of part of the transition material, the annealing process is further performed on the formed transition material. The conditions of the annealing process include: the annealing temperature ranges from 400 ℃ to 500 ℃ (temperature is greater than or equal to 400 ℃ and less than or equal to 500 ℃, i.e. the range includes the end values, the following range is expressed as the same meaning here), and the annealing time ranges from 2h to 4 h. Specifically, in the embodiment of the invention, the annealing temperature is 400 ℃, and the annealing time is 4 h. In another embodiment of the present invention, the annealing temperature is 500 ℃ and the annealing time is 2 hours. In yet another embodiment of the present invention, the annealing temperature is 440 ℃ and the annealing time is 3 hours.
After the annealing process, the process of removing the transition material on the top of the sidewall 130 and the top of the first sacrificial structure 121 includes a dry etching process, a wet etching process, or a chemical mechanical planarization process (CMP). Specifically, in the embodiment of the present invention, the transition material on the top of the sidewall 130 and the top of the first sacrificial structure 121 is removed by polishing using a CMP process. The CMP process allows for better control of the endpoint of the polishing.
In an embodiment of the invention, the material of the transition material comprises polysilicon or SiO2. Specifically, in the embodiment of the present invention, the material of the transition material is SiO2. Notably, in embodiments of the present invention, the material of the transition material and the material of the first sacrificial structure 121The same material facilitates simultaneous subsequent etching processes. In other embodiments of the present invention, the material of the transition material and the material of the first sacrificial structure 121 may also be different, and are not limited herein.
Referring to fig. 3a and 3b, the sidewall spacers 130 are removed to form a first groove 141.
The sidewall spacers 130 are removed to form a specific pattern structure. In the embodiment of the present invention, after the first groove 141 is formed, the shape of the pattern protruded by the first sacrificial structure 121 actually represents a partial pattern shape of the target groove pattern.
After forming the first recess 141, the first sacrificial structure 121 and the transition material layer 122 are separated by the first recess 141.
Referring to fig. 4 a-4 c, second sacrificial structure 122a and second recess 142 are formed.
As described above, the second sacrificial structure 122a is formed to form a smaller-sized, more dense bump pattern structure. In the embodiment of the present invention, the second sacrificial structures 122a are formed between the adjacent first sacrificial structures 121, and obviously, the distances between the second sacrificial structures 122a and the first sacrificial structures 121 are relatively close, and the overall pattern is more dense. Meanwhile, the first sacrificial structure 121 and the second sacrificial structure 122a are separated by the first groove 141 or the second groove 142. Specifically, in the embodiment of the present invention, after the second sacrificial structure 122a is formed, the first sacrificial structure 121 and the second sacrificial structure 122a are separated by the first groove 141.
As shown in fig. 4c, in other embodiments of the present invention, a first groove 141 and a second groove 142 may be further included between the first sacrificial structure 121 and the second sacrificial structure 122a, i.e., the first sacrificial structure 121 and the second sacrificial structure 122a are separated by the first groove 141 and the second groove 142, which is not limited herein. Up to this point, the shape of the patterns projected by the first sacrificial structure 121 and the second sacrificial structure 122a represents the shape of the target groove pattern that is finally formed.
In an embodiment of the present invention, the process steps for forming second sacrificial structure 122a and second recess 142 include: an intermediate material layer (not shown) is formed to fill the first recess 141, a mask layer (not shown) is formed on top of the intermediate material layer and the transition material layer, and a portion of the transition material layer is etched using the mask layer as a mask to form a second sacrificial structure 122a and a second recess 142, wherein the second sacrificial structure 122a is separated by the second recess 142.
And further comprising removing the intermediate material layer after forming the second sacrificial structure 122a, after removing the intermediate material layer, the first sacrificial structure 121 and the second sacrificial structure 122a being separated by said first recess 141. That is, in the embodiment of the present invention, after the second sacrificial structure 122a is formed, the protruding pattern shape of the sacrificial structure represents the structure of the target groove pattern that is finally formed, and this step removes all the regions that do not need to form the target groove pattern, and replaces the regions with the grooves.
As described above, when the second sacrificial structure 122a is formed by etching, the region where the first sacrificial structure 121 is removed in the target groove pattern is selected as the region where the second sacrificial structure 122a is formed. The distance between adjacent pattern lines formed by each step of the two-step process is relatively large, the patterns are sparse, but after the two-step process is carried out, the integrally formed raised pattern structure is more dense.
Obviously, the materials of the second sacrificial structure 122a and the transition material layer are the same, that is, in the embodiment of the present invention, the materials of the second sacrificial structure 122a, the transition material layer and the first sacrificial structure 121 are all SiO2。
Referring to fig. 4b, in the embodiment of the invention, only a portion of the transition material layer is etched to form the second sacrificial structure 122 a. In other embodiments of the present invention, a portion of the first sacrificial structure 121 or a portion of the intermediate material layer may be etched at the same time to form the second sacrificial structure 122a, which is not limited herein.
In the method for forming the semiconductor device, a mask layer is directly formed, then different groove patterns are formed through etching, then the mask is formed again, the groove patterns with different small sizes are formed through etching, and the like, so that a precise pattern is formed. However, in the process of forming the groove pattern for many times, the position of the mask layer is not easy to control, and the pattern is easy to be misplaced, so that the problems of shape deformation or size deviation are caused, and the accuracy of forming the groove pattern is finally influenced.
By utilizing the process of the embodiment of the invention, the raised pattern of the sacrificial structure is formed in two steps: in the first step, the formation of the pattern is assisted in a manner of forming a side wall. And a second step of retaining the required first sacrificial structure pattern, removing most of the unnecessary regions, gradually replacing the regions which finally need to form the target groove pattern with the raised patterns of the sacrificial structure, and replacing the regions which originally need to keep the raised patterns with the grooves. The two-step pattern transfer process can change the pattern to be fine, the size is smaller, and the structure is more dense and regular.
Referring to fig. 5 a-6 b, a dielectric layer 150 is formed in the first recess and the second recess.
In the embodiment of the present invention, after the dielectric layer 150 is formed, etching the first sacrificial structure 121 and the second sacrificial structure 122a by using the dielectric layer 150 as a mask to form the groove 140, so that the raised pattern of the first sacrificial structure 121 and the second sacrificial structure 122a is transferred into the groove 140 to form a final target groove pattern.
During the formation of the recess 140, the etching process needs to be stopped on the etch stop layer 110. Therefore, in the embodiment of the present invention, in the etching process for forming the groove 140, the etching process has a certain etching rate ratio γ to the first and second sacrificial structures 121 and 122a and to the etch stop layer 110. Here, 10. ltoreq. gamma. ltoreq.15. Specifically, in the embodiment of the present invention, γ is 12, i.e., the etching rate of the transition material layer is 12 times higher than the etching rate of the etching stop layer 110. In another embodiment of the present invention, γ is 14.
In summary, in the method for forming a semiconductor device disclosed in the embodiment of the present invention, the two-step process is adopted to gradually form the raised pattern, and then the raised pattern is etched to form the groove, so that the precise transfer of the dense pattern is realized, and the size of the formed pattern is more regular and accurate.
Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. Those skilled in the art can now fully appreciate how to implement the teachings disclosed herein, in view of the foregoing description.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (15)
1. A method of forming a semiconductor device, comprising:
providing a substrate and a discrete first sacrificial structure formed over the substrate;
forming a side wall covering the side wall of the discrete first sacrificial structure;
forming a transition material layer between the side walls;
removing the side wall to form a first groove;
etching part of the transition material layer to form a second groove and a second sacrificial structure separated by the second groove;
forming dielectric layers in the first groove and the second groove; and
and etching the first sacrificial structure and the second sacrificial structure by taking the dielectric layer as a mask to form a groove pattern.
2. The method of claim 1, wherein after forming the first recess, the transition material layer and the first sacrificial structure are separated by the first recess.
3. The method of claim 1, wherein each of the second sacrificial structures is formed between adjacent first sacrificial structures.
4. The method of claim 1, further comprising providing an etch stop layer between the substrate and the first sacrificial structure.
5. The method as claimed in claim 4, further comprising, after the etching to form the recess pattern, continuing to perform an etching process to etch the etch stop layer and the substrate to form a target pattern in the substrate.
6. The method as claimed in claim 4, wherein in the etching process for forming the groove pattern, the etching process has a certain etching rate ratio γ to the first sacrificial structure and the second sacrificial structure and to the etch stop layer, γ is 10 ≤ and 15.
7. The method for forming the semiconductor device according to claim 4, wherein the step of forming the side wall includes:
forming a side wall material layer which covers the side wall and the top of the first sacrificial structure and covers the top surface of the etching stop layer between the adjacent first sacrificial structures; and
and etching back the side wall material layer, and only reserving the side wall material layer formed on the side wall of the first sacrificial structure, namely the side wall.
8. The method as claimed in claim 7, wherein the step of forming the spacer material layer comprises an atomic layer deposition step.
9. The method of claim 1, wherein the step of forming the transition material layer comprises:
forming a transition material which is filled between the side walls and covers the tops of the side walls and the top of the first sacrificial structure; and
and removing the transition materials positioned at the tops of the side walls and the top of the first sacrificial structure, and only keeping the transition materials formed between the side walls, namely the transition material layers.
10. The method of claim 9, wherein the process of forming the transition material comprises a fluid chemical vapor deposition process.
11. The method of claim 10, further comprising annealing the transition material after forming the transition material and before removing a portion of the transition material.
12. The method of claim 11, wherein the conditions of the annealing process comprise: the annealing temperature range is 400-500 ℃, and the annealing time range is 2-4 h.
13. The method as claimed in claim 12, wherein the step of removing the transition material on top of the sidewall and on top of the first sacrificial structure comprises a dry etching step, a wet etching step or a chemical mechanical planarization step.
14. The method of claim 1, wherein the process steps of forming the second sacrificial structure and the second recess comprise:
forming an intermediate material layer filling the first groove;
forming a mask layer on the tops of the intermediate material layer, the first sacrificial structure and the transition material layer; and
and etching part of the transition material layer by taking the mask layer as a mask to form the second sacrificial structure and the second groove.
15. The method of claim 14, further comprising removing the intermediate material layer after forming the second sacrificial structure, wherein the first sacrificial structure and the second sacrificial structure are separated by the first recess after removing the intermediate material layer.
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| US6548385B1 (en) * | 2002-06-12 | 2003-04-15 | Jiun-Ren Lai | Method for reducing pitch between conductive features, and structure formed using the method |
| US7935477B2 (en) * | 2007-11-30 | 2011-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double patterning strategy for contact hole and trench |
| US9564361B2 (en) * | 2013-09-13 | 2017-02-07 | Qualcomm Incorporated | Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device |
| CN106910677B (en) * | 2015-12-23 | 2020-12-18 | 中芯国际集成电路制造(上海)有限公司 | Patterning method for manufacturing semiconductor device, and semiconductor device manufacturing method |
| US10381235B2 (en) * | 2016-05-29 | 2019-08-13 | Tokyo Electron Limited | Method of selective silicon nitride etching |
| CN107579001B (en) * | 2016-07-04 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| US10049918B2 (en) * | 2016-09-29 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Directional patterning methods |
| CN107887273A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
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