CN111180507A

CN111180507A - Embedded grid structure and manufacturing method thereof

Info

Publication number: CN111180507A
Application number: CN201811336185.8A
Authority: CN
Inventors: 冯大伟
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-11-09
Filing date: 2018-11-09
Publication date: 2020-05-19

Abstract

The invention discloses an embedded grid structure and a manufacturing method thereof, and the embedded grid structure comprises a semiconductor substrate, grid grooves are formed on a semiconductor substrate, and a dielectric layer is arranged on the semiconductor substrate, wherein in each grid groove, a first conductive metal layer is distributed along two side walls of the grid groove, the first conductive metal layer is in a clamping shape, and a second conductive metal layer is clamped between the first conductive metal layers at two sides.

Description

Embedded grid structure and manufacturing method thereof

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a buried gate structure and a method for fabricating the same.

Background

As technology advances, the size of semiconductor integrated circuits is becoming smaller, and the density of functional devices (i.e., interconnect devices per unit area of a chip) is increasing as the size of semiconductor integrated circuits is being reduced. Therefore, while the size of the semiconductor integrated circuit is reduced, the short channel effect is more and more obvious, and the threshold voltage of the gate is reduced, and the increase of the density of the functional elements is easy to cause the drain leakage current in the overlapping region of the drain and the gate, which affects the normal use of the semiconductor integrated circuit.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a buried gate structure and a method for fabricating the same, which can reduce drain leakage caused by a gate, increase the stability of a semiconductor device, and improve the performance of the semiconductor device.

To achieve the above and other related objects, the present invention provides a buried gate structure, including:

a semiconductor substrate comprising a gate trench having a gate oxide layer covering sidewalls and a bottom;

the first conductive metal layer is partially covered on the side wall of the gate oxide layer;

the second conductive metal layer is filled in the grid groove between the first conductive metal layers, and the height of the filled second conductive metal layer is less than or equal to that of the first conductive metal layers;

and the dielectric layer is filled in the grid groove except the first conductive metal layer and the second conductive metal layer.

Optionally, the thickness of the first conductive metal layer is 4-20 nm.

Optionally, the work function of the first conductive metal layer is greater than that of the second conductive metal layer, and the work function range of the first conductive metal layer is 4.1-4.9; the work function range of the second conductive metal layer is 4.7-5.0.

Optionally, the metal of the first conductive metal layer is one or a mixture of scandium, zirconium, hafnium, aluminum, titanium and tantalum; the metal of the second conductive metal layer is one or a mixture of tungsten, platinum, ruthenium and molybdenum.

Optionally, the second conductive metal layer and the first conductive metal layer form a metal gate having a continuous planar upper surface.

Optionally, there is a height difference of 40-60nm between the metal gate and the top of the gate trench.

Optionally, the buried gate structure further includes:

the metal blocking layer is formed between the gate oxide layer and the first conductive metal layer, and the metal blocking layer partially covers the gate oxide layer.

Optionally, a height difference exists between the metal barrier layer and the first conductive metal layer.

Optionally, there is a height difference of 5-10nm between the first conductive metal layer and the barrier layer. .

The invention also provides a manufacturing method of the embedded grid structure, which comprises the following steps:

providing a semiconductor substrate;

etching a grid groove on the semiconductor substrate, and covering a grid oxide layer on the bottom and the side wall of the grid groove;

sequentially filling a first conductive metal layer and a second conductive metal layer in the grid groove, wherein the first conductive metal layer partially covers the side wall of the grid oxide layer, the second conductive metal layer is filled in the grid groove between the first conductive metal layers, and the height of the filled second conductive metal layer is less than or equal to that of the first conductive metal layer;

optionally, a dielectric layer is filled on the semiconductor substrate, wherein the dielectric layer is filled in the gate trench except for the first conductive metal layer and the second conductive metal layer.

Optionally, when the first conductive metal layer is filled, the thickness of the filled first conductive metal layer is 4-20 nm.

Optionally, when the second conductive metal layer is filled, the second conductive metal layer and the first conductive metal layer form a metal gate having a continuous planar upper surface.

Optionally, when the metal gate is formed, a height difference of 40-60nm is formed between the metal gate and the top end of the gate trench.

Optionally, before the first conductive metal layer is filled in the gate trench, a metal blocking layer is filled on the side wall of the gate oxide layer.

Optionally, when the first conductive metal layer is filled, a height difference is formed between the metal barrier layer and the first conductive metal layer.

By adopting the technical scheme, when the embedded gate structure is formed, the double-layer metal gate is formed through the first conductive metal layer and the second conductive metal layer, the threshold voltage of the gate is increased, and further, the stability of the semiconductor device is increased.

Drawings

FIG. 1 is a schematic diagram of the structure of a semiconductor device of the present invention;

3 FIG. 3 2 3 is 3a 3 cross 3- 3 sectional 3 view 3A 3- 3A 3 of 3 FIG. 31 3 of 3 the 3 present 3 invention 3; 3

FIG. 3 is a schematic diagram of the deposition of a barrier layer, a first mask layer, a second mask layer, a third mask layer, an anti-reflection layer, and a photoresist layer according to the present invention;

FIG. 4 is a schematic view of the photoresist layer being processed to form a pattern I according to the present invention;

FIG. 5 is a schematic view of a fourth mask layer deposited over the antireflective layer of the present invention;

FIG. 6 is a schematic diagram of the present invention during etching of a fourth mask layer over the antireflective layer;

FIG. 7 is a schematic view of the present invention in etching the spacer forming pattern II;

FIG. 8 is a schematic view of the present invention when transferring pattern II;

FIG. 9 is a schematic view of the present invention with a fifth mask layer deposited over the second mask layer;

FIG. 10 is a schematic view of the present invention during polishing of a fifth mask layer;

FIG. 11 is a schematic view of the present invention in forming a gate trench;

FIG. 12 is a schematic structural diagram of the present invention during etching of the first mask layer and the barrier layer;

FIG. 13 is a schematic diagram of the present invention during deposition of a gate oxide layer;

FIG. 14 is a schematic illustration of the present invention in depositing a metallic barrier layer;

FIG. 15 is a schematic illustration of the invention when depositing a first conductive metal layer;

FIG. 16 is a schematic representation of the invention as it etches the first conductive metal layer;

FIG. 17 is a schematic illustration of the invention when depositing a second conductive metal layer;

FIG. 18 is a schematic diagram of the present invention during the process of alternately etching the first conductive metal layer, the second conductive metal layer, and the metal barrier layer;

FIG. 19 is an enlarged view of portion A of FIG. 2;

FIG. 20 is an enlarged view of portion B of FIG. 15;

FIG. 21 is an enlarged view of section C of FIG. 16;

fig. 22 is an enlarged view of a portion D of fig. 18.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1-22. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

It should be noted that, with the advance of technology, the volume of the semiconductor integrated circuit is smaller and smaller, and the size of the semiconductor integrated circuit is gradually reduced and the density of the functional elements is gradually increased. Therefore, while the size of the semiconductor integrated circuit is reduced, the short channel effect is more and more obvious, and the threshold voltage of the gate is reduced, and the increase of the density of the functional elements is easy to cause the drain leakage current in the overlapping region of the drain and the gate, which affects the normal use of the semiconductor integrated circuit. Accordingly, embodiments of the present invention provide a buried gate structure formed on a semiconductor substrate and a method for forming the same, which are used to solve the problem of drain leakage caused by a gate.

As shown in fig. 1, 2 and 19, the present invention discloses a semiconductor device, which includes a semiconductor substrate 100, shallow trenches 101 are uniformly disposed on the semiconductor substrate 100, the number of the shallow trenches 101 is according to the actual required etching, the semiconductor substrate 100 has uniformly distributed gate trenches 102, which may be, for example, 2, etched between every two adjacent shallow trenches 101, and a buried gate structure 200 is disposed in each gate trench 102.

As shown in fig. 2 and fig. 19, the buried gate structure 200 of the present disclosure includes a dielectric layer 201 disposed on a semiconductor substrate 100, an inverted U-shaped structure 202 is formed in a gate trench 102 of the dielectric layer 201, and a first conductive metal layer 203 and a second conductive metal layer 204 are disposed between the inverted U-shaped structure 202 and the bottom of the gate trench 102, wherein in each gate trench 102, the first conductive metal layer 203 is distributed along two sidewalls of the gate trench 102, and the first conductive metal layer 203 is in a clamping shape, so as to clamp the second conductive metal layer 204 between the first conductive metal layers 203 on two sides.

As shown in fig. 2 and fig. 19, a gate oxide layer 205 and a metal barrier layer 206 are further disposed between the gate trench 102 and the first conductive metal layer 203, the gate oxide layer 205 is silicon dioxide, and the metal barrier layer 206 is a tantalum compound, such as tantalum nitride.

As shown in fig. 1 and fig. 19, the gate oxide layer 205 is disposed on the surface of the substrate 100 and the inner side surface of the gate trench 102, the metal blocking layer 206 is divided into two parts, the first part is disposed on the substrate 100 and on the gate oxide layer 205, the second part is disposed in the gate trench 102 and is U-shaped, and is attached to the gate oxide layer 205 disposed in the gate trench 102, the height of the metal blocking layer 206 of the second part in the gate trench 102 is lower than that of the first conductive metal layer 203, and the metal blocking layer 206 of the second part is abutted to the inverted U-shaped structure 202 to wrap the first conductive metal layer 203 and the second conductive metal layer 204 therein.

The present invention should satisfy the condition that the work function of the first conductive metal layer 203 is smaller than that of the second conductive metal layer 204 when selecting the material of the conductive metal layer. Specifically, the work function of the first conductive metal layer 203 may be in a range of 4.1 to 4.9, such as one or a mixture of several of scandium, zirconium, hafnium, aluminum, titanium, and tantalum, and the work function of the second conductive metal layer may be in a range of 4.7 to 5.0, such as one or a mixture of several of tungsten, platinum, ruthenium, and molybdenum, but it is required to ensure that the work function of the first conductive metal layer 203 is smaller than the work function of the second conductive metal layer 204.

The dielectric layer 201 of the present invention is made of one or more of silicon nitride, silicon dioxide and a high dielectric constant material, wherein the high dielectric constant is a material having a dielectric constant higher than that of silicon dioxide, such as one or more of hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, and hafnium zirconium oxide.

As shown in fig. 1 to 22, the method for forming the buried gate structure on the semiconductor device of the present invention at least includes the following steps:

s1, a semiconductor substrate 100 is provided.

It should be noted that, when the semiconductor substrate 100 is provided, the semiconductor substrate 100 is formed with a shallow trench 101, and the shallow trench 101 is used for isolating two identical functional nodes. Specifically, as shown in fig. 3, shallow trenches 101 may be etched in a semiconductor substrate 100 by, for example, dry etching (e.g., plasma dry etching), etching, or other etching methods.

When the semiconductor substrate 100 is selected, the material used for the semiconductor substrate 100 is any one or a mixture of several of a silicon crystal, a germanium crystal, a silicon-on-insulator structure, a silicon-on-silicon epitaxial layer structure, a compound semiconductor, and an alloy semiconductor. The compound semiconductor is any one or a mixture of more of silicon carbide, gallium arsenide, gallium phosphide, indium arsenide and indium dysprosium, and the alloy semiconductor is any one or a mixture of more of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP.

As shown in fig. 3, after the shallow trench 101 is etched, a barrier layer 300, a first mask layer 301, a second mask layer 302, a third mask layer 303, an anti-reflection layer 304, and a photoresist layer 305 are sequentially deposited on the surface of the semiconductor substrate 100 from bottom to top by using a chemical vapor deposition method or other methods, or a barrier layer 300, a first mask layer 301, a second mask layer 302, a third mask layer 303, an anti-reflection layer 304, and a photoresist layer 305 are sequentially formed on the surface of the substrate 100 by using a spin coating process or other process methods, so as to prepare for etching the gate trench 102.

Specifically, the barrier layer 300 is formed, for example, a silicon nitride barrier layer, the first mask layer 301 is, for example, an amorphous carbon mask layer, the second mask layer 302 is, for example, a silicon oxynitride mask layer, and the third mask layer 303 is, for example, an amorphous carbon mask layer.

When forming the barrier layer 300, the first mask layer 301, the second mask layer 302, the third mask layer 303, the anti-reflection layer 304, and the photoresist layer 305, as shown in fig. 3, it is necessary to ensure that the surfaces of the barrier layer 300, the first mask layer 301, the second mask layer 302, the third mask layer 303, the anti-reflection layer 304, and the photoresist layer 305 are flat.

S2, the gate trench 102 is etched on the semiconductor substrate 100.

Specifically, as shown in fig. 4, the photoresist layer 305 on the top is exposed and developed, and then an excess portion of the photoresist layer 305 is removed by plasma dry etching or wet cleaning or other methods, and a first pattern 306 is formed.

The first pattern 306 is formed in the middle of the photoresist layer 305, and the cross section of the first pattern 306 is rectangular, when the first pattern 306 is formed, the length of the first pattern 306 is ensured to be consistent with the distance between the two adjacent sidewalls of the finally etched gate trench 102, so as to facilitate the need of subsequently etching the gate trench 102.

Then, as shown in fig. 5, a fourth mask layer 307 is formed on the anti-reflective layer 304 by, for example, a chemical vapor deposition method, and when the fourth mask layer 307 is formed, since the first pattern 306 is formed on the anti-reflective layer 304, a recess matching the pattern I306 is formed at the bottom of the fourth mask layer 307.

Specifically, the fourth mask layer 307 of the present embodiment is, for example, silicon dioxide.

Then, as shown in fig. 6, the fourth mask layer 307 is etched by dry etching (e.g., plasma dry etching), etching or other etching methods, so that the fourth mask layer 307 forms spacers 308 on both sides of the first pattern 306.

While the spacers 308 are etched, the excess portion of the fourth mask layer 307 is removed by a plasma dry etching method or other methods, and the distance between the gap of the spacers 308 and the two adjacent sidewalls of the finally etched gate trench 102 is the same.

As shown in fig. 6, the spacers 308 are formed as two blocks with gaps, and the blocks are formed on the anti-reflective layer 304. The block, when formed, has a width greater than the width of the finally formed gate trench 102.

Then, as shown in fig. 7, the first pattern 306 formed by the photoresist layer 305 is removed by plasma dry etching or wet cleaning or other methods, so that the spacers 308 form a second pattern 309.

Specifically, the second pattern 309 includes at least two blocks forming the spacer 308, and after the first pattern 306 between the two blocks is removed, the two blocks are in a state of having a gap therebetween, and the two blocks and the gap therebetween at this time together constitute the second pattern 309.

As shown in fig. 8, after the second pattern 309 is formed, the second pattern 309 is transferred downward layer by using dry etching (such as plasma dry etching), etching or other etching methods until the second pattern 309 reaches the second mask layer 302, and during the transfer, the anti-reflection layer 304 and the third mask layer 303 are removed by using dry etching or other methods in sequence.

As shown in fig. 8, in the process of transferring the second pattern 309 downward, the width of the two blocks constituting the second pattern 309 coincides with the width of the finally formed gate trench 102, so as to subsequently etch the gate trench 102.

As shown in fig. 9, after the second pattern 309 is transferred, a fifth mask layer 310 is deposited on the second mask layer 302 by cvd, pvd or other methods, and a bottom surface of the fifth mask layer 310 is provided with a recess corresponding to the second pattern 309 at the position of the second pattern 309.

Specifically, the fifth mask layer 310 of the present embodiment is, for example, silicon dioxide.

As shown in fig. 9, when depositing the fifth mask layer 310, the fifth mask layer 310 needs to be filled into the gap of the second pattern 309 in order to serve as a protection structure when etching the gate trench 102.

As shown in fig. 10, after the fifth mask layer 310 is deposited, a polishing operation is performed on the fifth mask layer 310 by a chemical mechanical polishing method or other methods.

As shown in fig. 10, the second pattern 309 is removed while the fifth mask layer 310 is polished, so that the fifth mask layer 310 forms a recess at the position of the second pattern 309, the carbon layer surface of the second mask layer 302 is exposed at the recess, and then the carbon film on the carbon layer surface is removed.

Then, as shown in fig. 11, the recess of the fifth mask layer 310 is etched downward by dry etching (e.g., plasma dry etching), etching or other etching methods, so as to form the gate trench 102 in the semiconductor substrate 100, and then the fifth mask layer 310 and the second mask layer 302 are removed by plasma dry etching in sequence.

As shown in fig. 12, after the gate trench 102 is etched, the initially formed first mask layer 301 and the barrier layer 300 are removed by dry etching (such as plasma dry etching), etching or other etching methods in sequence, so as to expose the surface of the semiconductor substrate 100.

S3, sequentially depositing a first conductive metal layer 203 and a second conductive metal layer 204 in the gate trench.

Specifically, as shown in fig. 13, before depositing the first conductive metal layer 203 and the second conductive metal layer 204, a gate oxide layer 205 is deposited on the surface of the semiconductor substrate 100 and in the gate trench 102 by a chemical vapor deposition method, a physical vapor deposition method, or other methods. The gate oxide layer 205 is U-shaped at the bottom of the gate trench 102.

Specifically, the gate oxide layer 205 is, for example, silicon dioxide.

As shown in fig. 14, after the gate oxide layer 205 is deposited, a metal barrier layer 206 is deposited on the outer side of the gate oxide layer 205 by chemical vapor deposition, physical vapor deposition or other methods.

Specifically, the metal barrier layer 206 is, for example, tantalum nitride.

As shown in fig. 15 and 20, after the metal barrier layer 206 is deposited, a first conductive metal layer 203 is deposited on the outer side of the metal barrier layer 206 by a chemical vapor deposition method, a physical vapor deposition method, or other methods.

The metal of the first conductive metal layer 203 may be one or a mixture of scandium, zirconium, hafnium, aluminum, titanium, and tantalum, and the work function of the first conductive metal layer 203 is, for example, within a range of 4.1 to 4.9.

As shown in fig. 16 and 21, after the first conductive metal layer 203 is deposited, the first conductive metal layer 203 is etched by dry etching (such as plasma dry etching), etching or other etching methods, a portion of the first conductive metal layer 203 on the surface of the semiconductor substrate 100 and a portion of the first conductive metal layer 203 at the bottom of the gate trench 102 are removed, and portions of the first conductive metal layer 203 at two side walls of the gate trench 102 are remained, which are labeled as 203 a.

As shown in fig. 17, a second conductive metal layer 204 is deposited on the outer side of the metal barrier layer 206 after the first conductive metal layer 203 is removed and the portion of the gate trench 102 between the first conductive metal layers 203a on both sides by a chemical vapor deposition method, a physical vapor deposition method, or other methods.

Specifically, the metal of the second conductive metal layer 204 may be one or a mixture of several of tungsten, platinum, ruthenium, and molybdenum, but it is required to ensure that the work function interval of the second conductive metal layer 204 is 4.7 to 5.0.

Meanwhile, when selecting the first conductive metal layer 203 and the second conductive metal layer 204, it is necessary to ensure that the work function of the first conductive metal layer 203 is smaller than that of the second conductive metal layer 204.

The thickness of the deposited first conductive metal layer 203 is smaller than that of the second conductive metal layer 204, wherein the thickness of the first conductive metal layer 203 is 4-20nm, and specifically may be, for example, 10nm or 15 nm.

As shown in fig. 18 and 22, after the second conductive metal layer 204 is deposited, the second conductive metal layer 204, the first conductive metal layer 203, and the metal barrier layer 206 are alternately etched by dry etching (such as plasma dry etching), etching, or other etching methods, so that the height of the metal barrier layer 206 in the gate trench 102 is lower than that of the first conductive metal layer 203, and the second conductive metal layer 204 and the first conductive metal layer 203 form an ohmic gate.

As shown in fig. 18 and 22, during the alternating etching, the second conductive metal layer 204 is etched first, and when the etching reaches the edge of the gate trench 102, the metal barrier layer 206 is selectively etched, and after the metal barrier layer 206 is etched, the first conductive metal layer 203 and the second conductive metal layer 204 are etched together. The finally etched first metal layer 203 is flush with the top of the second metal layer 204, and the deposited second conductive metal layer 204 and the first conductive metal layer 203 form a metal gate having a continuous planar upper surface, the height of the metal gate is lower than the height of the top end of the gate trench 102, and the height difference between the metal gate and the top end of the gate trench 102 is 40-60nm, which may be 45nm or 50nm, for example.

S4, depositing a dielectric layer 201 on the semiconductor substrate 100.

As shown in fig. 2 and 19, after the first metal layer 203, the second metal layer 204 and the metal barrier layer 206 are etched, a dielectric layer 201 is deposited in the gate trench 102 and outside the metal barrier layer 206 on the semiconductor substrate 100 by using a chemical vapor deposition method or other methods, and the dielectric layer 201 forms, for example, an inverted U-shaped structure 202 in the gate trench 102, where the inverted U-shaped structure 202 cooperates with the second conductive metal layer 204, the first conductive metal layer 203 and the metal barrier layer 206 to cooperate and clamp the second conductive metal layer 204, the first conductive metal layer 203 and the metal barrier layer 206 in the gate trench 102.

A polishing process is performed on the upper surface of the dielectric layer 201 by using a chemical mechanical polishing or other methods, so as to form a semiconductor device having the buried gate structure as shown in fig. 2 and 19.

When the embedded gate structure is formed, the double-layer metal gate is formed through the first conductive metal layer 203 and the second conductive metal layer 204, so that the threshold voltage of the gate is increased, and further, the stability of the semiconductor device is increased.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.

Claims

1. A buried gate structure, comprising:

the second conductive metal layer is filled in the grid groove between the first conductive metal layers, and the height of the filled second conductive metal layer does not exceed that of the first conductive metal layer;

2. The buried gate structure of claim 1, wherein: the thickness of the first conductive metal layer is 4-20 nm.

3. The buried gate structure of claim 1, wherein: the work function of the first conductive metal layer is larger than that of the second conductive metal layer, and the work function range of the first conductive metal layer is 4.1-4.9; the work function range of the second conductive metal layer is 4.7-5.0.

4. The buried gate structure of claim 3, wherein: the metal of the first conductive metal layer is one or a mixture of scandium, zirconium, hafnium, aluminum, titanium and tantalum; the metal of the second conductive metal layer is one or a mixture of tungsten, platinum, ruthenium and molybdenum.

5. The buried gate structure of claim 1, wherein: the second conductive metal layer and the first conductive metal layer form a metal gate having a continuous planar upper surface.

6. The buried gate structure of claim 5, wherein: and the height difference of the metal gate and the top end of the gate groove is 40-60 nm.

7. The buried gate structure of claim 1, further comprising:

8. The buried gate structure of claim 7, wherein: the metal barrier layer and the first conductive metal layer have a height difference, and the height of the first conductive metal layer is larger than that of the metal barrier layer.

9. The buried gate structure of claim 8, wherein: the first conductive metal layer and the barrier layer have a height difference of 5-10 nm.

10. A method for fabricating a buried gate structure includes the steps of:

providing a semiconductor substrate;

and filling a dielectric layer on the semiconductor substrate, wherein the dielectric layer is filled in the gate trench except the first conductive metal layer and the second conductive metal layer.

11. The method of claim 10, wherein the first conductive metal layer is filled to a thickness of 4-20nm when the first conductive metal layer is filled.

12. The method as claimed in claim 11, wherein the second conductive metal layer and the first conductive metal layer are formed into a metal gate having a continuous planar upper surface while the second conductive metal layer is filled.

13. The method as claimed in claim 12, wherein a height difference of 40-60nm is formed between the top of the gate trench and the metal gate when the metal gate is formed.

14. The method of claim 13, wherein a capping metal barrier layer is filled on sidewalls of the gate oxide layer before the first conductive metal layer is filled in the gate trench.

15. The method of claim 14, wherein a height difference is formed between the metal barrier layer and the first conductive metal layer when the first conductive metal layer is filled.